Abstract: A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation.

Abstract: A method for fabricating a semiconductor device is provided. A nickel layer is deposited on a semiconductor substrate and plasma-processed. Rapid thermal processing is performed on the plasma-processed nickel layer to form a nickel silicide layer. The portion of the nickel layer that has not reacted with silicon is then removed.

Abstract: The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semiconductor substrate in the vicinity of the gate electrode. A silicide film is formed on each of the gate electrode and the source-drain diffusion layer. The silicide film positioned on the gate electrode is thicker than the silicide film positioned on the source-drain diffusion layer. The present invention also provides a method of manufacturing a semiconductor device, in which a gate electrode is formed on a gate insulating film covering a semiconductor substrate, followed by forming a source-drain diffusion layer within the semiconductor substrate.

Abstract: Disclosed is a method for manufacturing an image sensor. The method includes forming a polysilicon layer on a semiconductor substrate having an active region, forming a sacrificial layer on the polysilicon layer, forming a photoresist pattern on the sacrificial layer, implanting conductive impurities onto the polysilicon layer using the photoresist pattern as an ion implantation mask, removing the photoresist pattern, and removing the sacrificial layer from the polysilicon layer, thereby removing photoresist residues remaining on the sacrificial layer.

Abstract: A silicon integrated circuit device comprising a near intrinsic silicon substrate in which there are one or more ohmic contact regions. An insulating layer lies above the substrate, and on top of the insulating layer is a lower layer of one or more aluminium gates. The surface of each of the lower gates is oxidised to insulate them from an upper aluminium gate that extends over the lower gates.

Abstract: A semiconductor device having excellent characteristics is provided without deteriorated film quality. A first oxide film is divided into three regions A, B and C. Lengths I, II and III of the regions A, B and C in a plane direction of the silicon substrate are set equal to each other. In the first oxide film, a thermal treatment is carried out such that the film thicknesses of the regions A and C are increased. The thermal treating time, the thermal treating temperature and other parameters are adjusted such that sectional areas of the regions A and C become 1.5 times of a sectional area of the region B, while a film thickness of the region B is maintained.

Abstract: A method that combines alternate low/medium ion dose implantation with rapid thermal annealing at relatively low temperatures. At least one dopant is implanted in one of a single crystal and an epitaxial film of the wide band gap compound by a plurality of implantation cycles. The number of implantation cycles is sufficient to implant a predetermined concentration of the dopant in one of the single crystal and the epitaxial film. Each of the implantation cycles includes the steps of: implanting a portion of the predetermined concentration of the one dopant in one of the single crystal and the epitaxial film; annealing one of the single crystal and the epitaxial film and implanted portion at a predetermined temperature for a predetermined time to repair damage to one of the single crystal and the epitaxial film caused by implantation and activates the implanted dopant; and cooling the annealed single crystal and implanted portion to a temperature of less than about 100° C.

Abstract: Disclosed herein is a method for fabricating a semiconductor memory device that can prevent oxidation of bit lines when forming an interlayer dielectric for isolating the bit lines. The bit line is formed on a semiconductor substrate where an underlying structure is formed. A silicon on dielectric (SOD) layer is formed on the resulting structure where the bit line is formed. A heat treatment can be performed on the SOD layer with a partial pressure ratio of water vapor (H2O) to hydrogen (H2) in a range of about 1×10?11 to about 1.55 at a temperature in a range of about 600° C. to about 1,100° C.

Abstract: The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step. A selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.

Abstract: An integrated circuit includes copper lines, wherein the crystal structure of the copper has a greater than 30% <001 > crystal orientation and a less than 20% <111> crystal orientation.

Abstract: An electrical device in which an interface layer is disposed between and in contact with a metal and a Si-based semiconductor, the interface layer being of a thickness effective to depin of the Fermi level of the semiconductor while still permitting current to flow between the metal and the semiconductor. The interface layer may include a layer of a passivating material (e.g., made from nitrogen, oxygen, oxynitride, arsenic, hydrogen and/or fluorine) and sometimes also includes a separation layer. In some cases, the interface layer may be a monolayer of a semiconductor passivating material. The interface layer thickness corresponds to a minimum specific contact resistance of less than or equal to 10?-?m2 or even less than or equal to 1?-?m2 for the electrical device.

Abstract: A method for forming a stabilized metal silicide film, e.g., contact (source/drain or gate), that does not substantially agglomerate during subsequent thermal treatments, is provided In the present invention, ions that are capable of attaching to defects within the Si-containing layer are implanted into the Si-containing layer prior to formation of metal silicide. The implanted ions stabilize the film, because the implants were found to substantially prevent agglomeration or at least delay agglomeration to much higher temperatures than in cases in which no implants were used.

Abstract: The invention relates to a process for the formation of a structure comprising a thin layer made of semiconductor material on a substrate, including the steps of providing a zone of weakness in a donor substrate; bonding the donor substrate to a support substrate; detaching a portion of the donor substrate to transfer it to the support substrate, wherein the detaching includes applying heat treating the donor substrate to weaken the zone of weakness without initiating detachment and applying an energy pulse to provoke self-maintained detachment of the donor substrate portion to transfer it to the support substrate; and subjecting the transferred portion of the donor substrate to a finishing operation to form a thin layer.

Abstract: The present invention is related to the field of semiconductor processing and, more particularly, to the formation of low resistance layers on germanium substrates. One aspect of the present invention is a method comprising: providing a substrate on which at least one area of a germanium layer is exposed; depositing over the substrate and said germanium area a metal, e.g., Co or Ni; forming over said metal, a capping layer consisting of a silicon oxide containing layer, of a silicon nitride layer, or of a tungsten layer, preferably of a SiO2 layer; then annealing for metal-germanide formation; then removing selectively said capping layer and any unreacted metal, wherein the temperature used for forming said capping layer formation is lower than the annealing temperature.

Abstract: Apparatus for dynamic surface annealing of a semiconductor wafer includes a source of laser radiation emitting at a laser wavelength and comprising an array of lasers arranged in rows and columns, the optical power of each the laser being individual adjustable and optics for focusing the radiation from the array of lasers into a narrow line beam in a workpiece plane corresponding to a workpiece surface, whereby the optics images respective columns of the laser array onto respective sections of the narrow line beam. A pyrometer sensor is provided that is sensitive to a pyrometer wavelength. An optical element in an optical path of the optics is tuned to divert radiation emanating from the workpiece plane to the pyrometry sensor. As a result, the optics images each of the respective section of the narrow line beam onto a corresponding portion of the pyrometer sensor.

Abstract: The present invention prevents the diffusion of an aluminum element into a polysilicon layer in a heating step when an aluminum-based conductive layer is used in a source/drain electrode which is in contact with low-temperature polysilicon whereby the occurrence of defective display can be obviated. An aluminum-based conductive layer is used in a source/drain electrode and a barrier layer made of molybdenum or a molybdenum alloy layer is formed between the aluminum-based conductive layer and a polysilicon layer. Further, a molybdenum oxide nitride film formed by the rapid heat treatment (rapid heat annealing) in a nitrogen atmosphere is formed over a surface of the molybdenum or the molybdenum alloy which constitutes the barrier layer.

Abstract: A method is disclosed for controlling the formation of an interfacial oxide layer in a polysilicon emitter transistor device. The interfacial oxide layer is formed between an underlying substrate of single crystal silicon and an upper layer of polysilicon. The current gain and the emitter resistance of the transistor device are related to the thickness of the interfacial oxide layer. The oxide of the interfacial oxide layer is grown in a low pressure, low temperature pure oxygen (O2) environment that greatly reduces the oxidation rate. The low oxidation rate allows the thickness of the interfacial oxide layer to be precisely controlled and sources of variation to be minimized in the manufacturing process.

Abstract: A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the nMOS transistor is enhanced.

Abstract: To form a wiring electrode having excellent contact function, in covering a contact hole formed in an insulating film, a film of a wiring material comprising aluminum or including aluminum as a major component is firstly formed and on top of the film, a film having an element belonging to 12 through 15 groups as a major component is formed and by carrying out a heating treatment at 400° C. for 0.5 through 2 hr in an atmosphere including hydrogen, the wiring material is provided with fluidity and firm contact is realized.

Abstract: There is presented a method of forming a semiconductor device. The method comprises forming gate structures including forming gate electrodes over a semiconductor substrate and forming spacers adjacent the gate electrodes. Source/drains are formed adjacent the gate structures, and a laminated stress layer is formed over the gate structure and the semiconductor substrate. The formation of the laminated stress layer includes cycling a deposition process to form a first stress layer over the gate structures and the semiconductor substrate and at least a second stress layer over the first stress layer. After the laminated layer is formed, it is subjected to an anneal process conducted at a temperature of about 900° C. or greater.

Abstract: An apparatus for annealing a substrate includes a substrate stage having a substrate mounting portion configured to mount the substrate; a heat source having a plurality of heaters disposed under the substrate mounting portion, the heaters individually preheating a plurality areas defined laterally in the substrate through a bottom surface of the substrate; and a light source facing a top surface of the substrate, configured to irradiate a pulsed light at a pulse width of about 0.1 ms to about 100 ms on the entire top surface of the substrate.

Abstract: Generally disclosed is a method of a device comprising forming a polysilicon stack including a first and a second polysilicon layer with an intervening etch stop layer, wherein the first polysilicon layer height is at least one third a height of the polysilicon stack height, removing the second polysilicon layer and the etch stop layer, and reacting the first polysilicon layer with a metal to fully silicide the first polysilicon layer. Fully silicided (FUSI) gates can hence be formed with uniform gate height. The thin first polysilicon layer allows for siliciding with a lower thermal budge and with better uniformity of the silicide concentration throughout the layer.

Abstract: A gate insulation layer with a high dielectric constant for a CMOS image sensor formed by a damascene process. A silicide layer on a gate electrode layer is formed in both a pixel region and a peripheral circuit region, and a silicide layer on a source/drain region is formed only in a peripheral circuit.

Abstract: A method of forming an aluminum contact including forming a barrier metal layer on an interlayer insulation layer pattern defining a contact hole, and forming an aluminum layer on the barrier metal layer so as to fill the contact hole. The method further includes forming a photoresist pattern for ion implantation, implanting ions into the aluminum layer, and annealing by using a rapid thermal process.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of forming an insulating material layer. The method includes forming an interface layer, removing a portion of the interface layer, annealing the interface layer, and forming a dielectric material over the interface layer.

Abstract: A method for fabricating a semiconductor device is provided. A nickel layer is deposited on a semiconductor substrate and plasma-processed. Rapid thermal processing is performed on the plasma-processed nickel layer to form a nickel silicide layer. The portion of the nickel layer that has not reacted with silicon is then removed.

Abstract: By improving the purity of metal lines and the crystalline structure, the overall performance of metal lines, especially of highly scaled copper-based semiconductor devices, may be enhanced. The modification of the crystalline structure of the metal lines may be performed by a heat treatment generating locally restricted heating zones, which are scanned along the length direction of the metal lines, and/or a heat treatment comprising a heating step in a vacuum ambient followed by a heating step in a reducing ambient.

Abstract: A method is disclosed for a multi-zone interference correction processing for a rapid thermal processing (RTP) system. This processing allows for improved calibration/tuning of RTP systems by accounting for zone coupling. The disclosed method includes establishing baseline characteristic data and zone characteristic data, and then using the baseline and zone characteristic data to determine lamp-control parameters, such as temperature offset values, for temperature sensors of the RTP system. The baseline characteristic data includes information regarding baseline heating uniformity of an RTP system. The zone characteristic data is collected for a plurality of heating zones within the heating chamber of the RTP system, each zone being associated with a respective temperature probe. The zone characteristic data is collected based on controlled temperature sensor variations.

Abstract: A CMOS gate stack that increases the inversion capacitance compared to a conventional CMOS gate stack has been described. Using a poly-SiGe gate, instead of the conventional poly-Si gate near the gate dielectric layer, increases the amount of implanted dopant that can be activated. This increase overcomes the polysilicon depletion problem that limits the inversion capacitance in the conventional CMOS gate stack. To integrate the poly-SiGe layer into the gate stack, a thin ?-Si layer is deposited between the gate dielectric layer and the poly-SiGe layer. To ensure proper salicide formation, a poly-Si layer is capped over the poly-SiGe layer. In order to obtain a fined-grained poly-Si over poly-SiGe, a second ?-Si layer is deposited between the poly-Si layer and the poly-SiGe layer.

Abstract: The invention relates to a method of manufacturing a semiconductor device (10) with a field effect transistor, in which method a semiconductor body (1) of silicon is provided at a surface thereof with a source region (2) and a drain region (3) of a first conductivity type, which both are provided with extensions (2A,3A) and with a channel region (4) of a second conductivity type, opposite to the first conductivity type, between the source region (2) and the drain region (3) and with a gate region (5) separated from the surface of the semiconductor body (1) by a gate dielectric (6) above the channel region (4), and wherein a pocket region (7) of the second conductivity type and with a doping concentration higher than the doping concentration of the channel region (4) is formed below the extensions (2A,3A), and wherein the pocket region (7) is formed by implanting heavy ions in the semiconductor body (1), after which implantation a first annealing process is done at a moderate temperature and a second annealing

Abstract: A silicide 160 is formed in exposed silicon on a semiconductor wafer 10 by a method that includes forming a thin interface layer 140 over the semiconductor wafer 10 and performing a first low temperature anneal to create the silicide 160. The method further includes removing an unreacted portion of the interface layer 140 and performing a second low temperature anneal to complete the formation of a low resistance silicide 160.

Abstract: Cu-based interconnections are fabricated in a semiconductor device by depositing a thin film of Cu or Cu alloy on a dielectric film by sputtering, the dielectric film having trenches and/or via holes at least one groove and being arranged on or above a substrate, and carrying out high temperature and high pressure treatment to thereby embed the Cu or Cu alloy into the trenches and/or via holes, in which the sputtering is carried out at a substrate temperature of ?20° C. to 0° C. using, as a sputtering gas, a gaseous mixture containing hydrogen gas and an inert gas in a ratio in percentage of 5:95 to 20:80.

Abstract: A method of fabricating a semiconductor device, includes (a) forming an oxide film entirely over a silicon substrate on which a MOS transistor is fabricated, (b) carrying out first thermal-annealing to the silicon substrate, (c) removing the oxide film in an area where later mentioned silicide is to be formed, (d) forming a metal film entirely over the silicide substrate, (e) carrying out second thermal-annealing to the silicon substrate to form silicide in the area, and (f) removing the metal film having been not reacted with the silicon substrate.

Abstract: By using an implantation mask having a high intrinsic stress, SMT sequences may be provided in which additional lithography steps may be avoided. Consequently, a strain source may be provided without significantly contributing to the overall process complexity.

Abstract: In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extension structure is previously obtained. This correspondence satisfies that the transistor has a given threshold voltage. After formation of the gate electrode and measurement of the size of the gate electrode, ion implantation conditions or heat treatment conditions for forming the drain extension structure are set based on the previously-obtained correspondence and the measured size of the gate electrode. Ion implantation or heat treatment for forming the drain extension structure is performed under the ion implantation conditions or heat treatment conditions that have been set.

Abstract: Processes for forming semiconductor structure comprising a transfer layer transferred from a donor substrate are provided in which the resulting structure has improved quality with respect to defects and resulting structures therefrom. For example, a semiconductor on insulator (“SeOI”) structure can be formed using a donor substrate, a support substrate and an insulating layer. The donor substrate may be formed using CZ pulling of semiconductor material at a rate that results in the existence of vacancy clusters. An insulating layer for the SeOI structure can be formed by depositing an oxide layer on the donor or support substrate. An insulating layer can also be formed by thermal oxidizing the support substrate. An SeOI structure can be formed by combining the donor substrate, the support substrate, and the insulating layer there between, and detaching the combination including a thin layer of the donor substrate using a zone of weakness that was formed in the donor substrate.

Abstract: In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extension structure is previously obtained. This correspondence satisfies that the transistor has a given threshold voltage. After formation of the gate electrode and measurement of the size of the gate electrode, ion implantation conditions or heat treatment conditions for forming the drain extension structure are set based on the previously-obtained correspondence and the measured size of the gate electrode. Ion implantation or heat treatment for forming the drain extension structure is performed under the ion implantation conditions or heat treatment conditions that have been set.

Abstract: A method of producing a semiconductor device includes the steps of forming a protrusion electrode on a semiconductor chip; and sealing the protrusion electrode and a semiconductor substrate with a resin layer. The method further includes the steps of polishing the resin layer until an upper surface of the protrusion electrode is exposed; polishing the exposed upper surface of the protrusion electrode; and forming a solder terminal on the polished upper surface of the protrusion electrode.

Abstract: A method and a deposition system for increasing deposition rates of metal layers from metal-carbonyl precursors using CO gas and a dilution gas. The method includes providing a substrate in a process chamber of a processing system, forming a process gas containing a metal-carbonyl precursor vapor and a CO gas, diluting the process gas in the process chamber, and exposing the substrate to the diluted process gas to deposit a metal layer on the substrate by a thermal chemical vapor deposition process.

Abstract: A method of forming a relaxed SiGe layer having a high germanium content in a semiconductor device includes preparing a silicon substrate; depositing a strained SiGe layer; implanting ions into the strained SiGe layer, wherein the ions include silicon ions and ions selected from the group of ions consisting of boron and helium, and which further includes implanting H+ ions; annealing to relax the strained SiGe layer, thereby forming a first relaxed SiGe layer; and completing the semiconductor device.

Abstract: A salicide process is provided. A metal layer selected from a group consisting of titanium, cobalt, platinum, palladium and an alloy thereof is formed over a silicon layer. A first thermal process is performed. Next, a second thermal process is performed, wherein the second thermal process includes a first step performed at 600˜700 degrees centigrade for 10˜60 seconds and a second step performed at 750˜850 degrees centigrade for 10˜60 seconds. If the metal layer is selected from a group consisting of nickel and an alloy thereof is formed on a silicon layer, the first step of the second thermal process is performed at 300˜400 degrees centigrade for 10˜60 seconds and the second step of the second thermal process is performed at 450˜550 degrees centigrade for 10˜60 seconds.

Abstract: A method of fabricating a metal silicide layer over a substrate is provided. First, a hard mask layer is formed over a gate formed on a substrate and a portion of the substrate is exposed. Thereafter, a first metal silicide layer, which is a cobalt silicide or a titanium silicide layer, is formed on the exposed substrate. After that, the hard mask layer is removed and a second metal silicide layer is formed over the gate, wherein a material of the second metal silicide layer is selected from a group consisting of nickel silicide, platinum silicide, palladium silicide and nickel alloy. Since different metal silicide layers are formed on the substrate and the gate, the problem of having a high resistance in lines with a narrow line width and the problem of nickel silicide forming spikes and pipelines in the source region and the drain region are improved.

Abstract: The present invention is directed to controlling wafer temperature during rapid thermal processing. Regions and devices in an integrated circuit may be surrounded, inlayed, and overlaid with high absorptive structures to increase the average absorptivity of a region. This technique is useful for increasing average absorptivity in dense capacitive regions of integrated circuits. These dense capacitive regions typically have large areas of exposed low absorptivity polysilicon during rapid thermal processing steps. The exposed low absorptivity regions absorb less energy than other regions of the integrated circuit. As such, the RTP temperature varies between regions of the integrated circuit, causing variance in device size and characteristics. Adding absorptivity structures increase the absorption of energy in these regions, reducing temperature variance during RTP. The reduced temperature variance results in uniform manufacture of device.

Abstract: A method of forming a pre-metal dielectric (PMD) layer is disclosed. In the method, after a nitride liner layer is formed on a substrate having a transistor, a USG layer is deposited thereon and then planarized. Next, ion implantation and annealing are performed for gettering, first in a gate region and then in a non-gate region of the USG layer. The USG layer is generally free from plasma damage and has a good gap-fill capability. Further, ion implantation and annealing after deposition of the USG layer may enhance a gap-fill capability, a gettering capability, and electrical properties of a transistor.

Abstract: The invention provides a semiconductor device, and a manufacturing method, comprising a semiconductor substrate, a gate insulating film, a gate electrode, and a source-drain diffusion layer. A silicide film is formed on the gate electrode and the source-drain diffusion layer. The silicide film is thicker on the gate electrode than on the source-drain diffusion layer. The manufacturing method comprises forming a gate electrode on a gate insulating film, followed by forming a source-drain diffusion layer. Then, atoms inhibiting a silicidation are selectively introduced into the source-drain diffusion layer, and a high melting point metal film is formed on the gate electrode and the source-drain diffusion layer. The high melting point metal film is converted into silicide films selectively on the gate electrode and the source-drain diffusion layer.

Abstract: The present invention is directed to a method for thermally processing a substrate in a thermal processing system. The method provides an amount of heat to the substrate and obtains information associated with the substrate when the amount of heat is provided. For example, the substrate is provided at a presoak position within the thermal processing system, wherein the presoak position, and one or more properties associated with the substrate, such as a position and temperature, are measured. An optimal process parameter value to provide an optimal thermal uniformity of the substrate is then determined, based, at least in part, on the information obtained from the substrate. For example, a soak position of the substrate is determined, wherein the determination is based, at least in part, on the one or more measured properties associated with the substrate, and a thermal uniformity associated with a reference data set.

Abstract: A method of forming a gate dielectric layer is disclosed. The method comprises the following steps. A substrate is provided having silicon regions containing surfaces upon which gate dielectrics are to be disposed. An oxide is formed over the surfaces. A silicon layer is formed over the oxide layer. A nitridation process is performed. An optional high temperature annealing step may be performed.

Abstract: Disclosed in a method of forming a copper wiring in a semiconductor device. A copper layer buries a damascene pattern in which an interlayer insulating film of a low dielectric constant. The copper layer is polished by means of a chemical mechanical polishing process to form a copper wiring within a damascene pattern. At this time, the chemical mechanical polishing process is overly performed so that the top surface of the copper wiring is concaved and is lower than the surface of the interlayer insulating film of the low dielectric constant neighboring it. Furthermore, an annealing process is performed so that the top surface of the copper wiring is changed from the concaved shape to a convex shape while stabilizing the copper wiring. A copper anti-diffusion insulating film is then formed on the entire structure including the top surface of the copper wiring having the convex shape.

Abstract: A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an NMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the NMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the NMOS transistor is enhanced.

Abstract: On a substrate are sequentially formed a first interconnection 203, a diffusion barrier film 205 and a second insulating film 207, and on the upper surface of the second insulating film 207 is then formed a sacrificial film 213. Next, a via hole 211 and an interconnection trench 217 are formed, and on the sacrificial film 213 are then formed a barrier metal film 219 and a copper film 221. CMP for removing the extraneous copper film 221 and barrier metal film 219 are conducted in a two-step process, i. e., the first polishing where polishing is stopped on the surface of the barrier metal film 219 and the second polishing where the remaining barrier metal film 219 and the tapered sacrificial film 213 are polished.