Abstract: A process and related product in which ohmic contacts are formed in High Electron Mobility Transistors (HEMTs) employing compound substrates such as gallium nitride. An improved device and an improvement to a process for fabrication of ohmic contacts to GaN/AlGaN HEMTs using a novel two step resist process to fabricate the ohmic contacts are described. This novel two-step process consists of depositing a plurality of layers having compounds of Group III V elements on a substrate; patterning and depositing a first photoresist on one of the layers; etching recessed areas into this layer; depositing ohmic metals on the recessed areas; removing the first photoresist; patterning and depositing a second photoresist, smaller in profile than the first photoresist, on the layer; depositing more ohmic metal on the layer allowing for complete coverage of the recessed areas; removing the second photoresist, and annealing the semiconductor structure.

Abstract: A method for forming ultra-shallow junctions in a semiconductor wafer with reduced silicon consumption during salicidation supplies additional silicon during the salicidation process. After the gate and source/drain junctions are formed in a semiconductor device, high-resistivity metal silicide regions are formed on the gate and source/drain junctions. Amorphous silicon is then deposited in a layer on the high resistivity metal silicide regions by high density plasma chemical vapor deposition. The deposition of the amorphous-silicon is at an elevated temperature which causes transforming of the high resistivity metal silicide regions to low resistivity metal silicide regions on the gate and source/drain junctions. The deposited amorphous-silicon acts as a source of silicon that is employed as a diffusion species during the transformation of the high resistivity metal silicide to the low resistivity metal silicide.

Abstract: A method that includes flowing an inert gas into an interior of a single wafer process chamber to create a pressure in the interior that is greater than an ambient pressure; and maintaining the greater interior pressure during a wafer transfer with the single wafer process chamber.

Abstract: A strained-silicon (Si) channel CMOS device shallow trench isolation (STI) oxide region, and method for forming same have been provided. The method comprises: forming a Si substrate; forming a relaxed-SiGe layer overlying the Si substrate, or a SiGe on insulator (SGOI) substrate with a buried oxide (BOX) layer; forming a strained-Si layer overlying the relaxed-SiGe layer; forming a silicon oxide layer overlying the strained-Si layer; forming a silicon nitride layer overlying the silicon oxide layer; etching the silicon nitride layer, the silicon oxide layer, the strained-Si layer, and the relaxed-SiGe layer, forming a STI trench with trench corners and a trench surface; forming a sacrificial oxide liner on the STI trench surface; in response to forming the sacrificial oxide liner, rounding and reducing stress at the STI trench corners; removing the sacrificial oxide liner; and, filling the STI trench with silicon oxide.

Abstract: A method of fabricating a copper-containing structure, preferably within a microelectronic device, including a rapid temperature ramp from about 20 degrees Celsius up to between about 300 and 500 degrees Celsius, preferably about 400 degrees Celsius, at a rate of between about 20 and 60 degrees Celsius per second, preferably about 40 degrees Celsius per second.

Abstract: The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. In one aspect, the invention includes a method of forming a conductive line comprising: a) forming a polysilicon layer; forming a silicide layer against the polysilicon layer; b) providing a conductivity-enhancing impurity within the silicide layer; and c) providing the polysilicon layer and the silicide layer into a conductive line shape. In another aspect, the invention includes a programmable-read-only-memory device comprising: a) a first dielectric layer over a substrate; b) a floating gate over the first dielectric layer; c) a second dielectric layer over the floating gate; d) a conductive line over the second dielectric layer; and e) a metal-silicide layer over the conductive line, the metal-silicide layer comprising a Group III dopant or a Group V dopant.

Abstract: Semiconductor wafer tray positioning, such as can be used in rapid thermal processing (RTP), rapid thermal annealing (RTA), and other semiconductor fabrication processes, is disclosed. A housing, such as a quartz tube, to receive a wafer tray includes at least four positioning kits. Each positioning kit includes a primary outside edge and an inside edge. The primary outside edge at least substantially corresponds to an interior sidewall of the housing. The inside edge is opposite of the primary outside edge, and has a groove that at least substantially corresponds to a part of a frame of the wafer tray. The groove is receptive to the part of the frame of the wafer tray, to assist maintaining the wafer tray in a stable position when the tray is completely positioned in the housing.

Abstract: A process for forming a first transistor of a first conductivity type and a second transistor of a second conductivity type in a semiconductor substrate is disclosed. The substrate has a first well of the first conductivity type and a second well of the second conductivity type. A gate dielectric is formed over the wells. A first metal layer is then formed over the gate dielectric. A portion of the first metal layer located over the second well is then removed. A second metal layer different from said first metal is then formed over the wells and a gate mask is formed over the second metal. The metal layers are then patterned to leave a first gate over the first well and a second gate over the second well. Source/drains are then formed in the first and second wells to form the first and second transistor.

Abstract: A gate insulating film 4, two polysilicon films 5 and 7, and a silicon nitride film 9 are successively laminated on a semiconductor substrate 1 in this order. Each of the polysilicon films 5 and 7 contains phosphorus. The polysilicon film 5 has a region having a phosphorus concentration higher than that of the polysilicon film 7. Gate electrodes 10n, 10p, 40n, and 40p are formed on the gate insulating film 4 by partly etching the polysilicon films 5 and 7 and the silicon nitride film 9. In this case, the etching rate of the region of the polysilicon film 5, having a phosphorus concentration higher than that of the polysilicon film 7, is higher than that of the polysilicon film 7. Due to this difference, notches are formed at the bottom portions on side surfaces of respective gate electrodes 10p, 40n, and 40p.

Abstract: The present invention relates to a method for fabricating a semiconductor device. The method comprises the steps of: 1. A method for fabricating a semiconductor device, which comprises the steps of: forming a gate line on a semiconductor substrate; forming junction regions in the semiconductor substrate at both sides of the gate line; forming and selectively removing an interlayer insulating film on the substrate to form contact holes exposing the junction regions; forming plugs in the contact holes; and implanting impurity ions into the plugs; and annealing the junction regions.

Abstract: A high temperature thermal annealing process creates a low resistance contact between a metal material and an organic material of an organic semiconductor device, which improves the efficiency of carrier injection. The process forms ohmic contacts and Schottky contacts. Additionally, the process may cause metal ions or atoms to migrate or diffuse into the organic material, cause the organic material to crystallize, or both. The resulting organic semiconductor device has enhanced operating characteristics such as faster speeds of operation. Instead of using heat, the process may use other forms of energy, such as voltage, current, electromagnetic radiation energy for localized heating, infrared energy and ultraviolet energy. An example enhanced organic diode comprising aluminum, carbon C60, and copper is described, as well as example insulated gate field effect transistors.

Abstract: A method of preventing formation of titanium oxide within a semiconductor device structure during a high temperature treatment of the device structure includes forming a passivation layer to preclude formation of titanium oxide at a titanium/oxide interface of a semiconductor device structure. The method includes providing a substrate assembly including at least an oxide region and forming a layer of titanium over a surface of the oxide region. The oxide region surface is treated with a plasma comprising nitrogen prior to forming the titanium layer so as to form a passivation layer upon which the titanium layer is formed. A thermal treatment is performed on the substrate assembly with the passivation layer substantially inhibiting diffusion of oxygen from the oxide layer during the thermal treatment of the substrate assembly. Generally, the passivation layer comprises SixOyNz.

Abstract: An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor deposition techniques, which may be followed by an anneal to better define and/or crystallize the at least two phases. The film may be formed over an underlying conductive layer. At least one of the at least two phases is selectively removed from the film, such as by an etch process that preferentially etches at least one of the at least two phases so as to leave at least a portion of the electrically conductive phase. Ruthenium and ruthenium oxide, both conductive, may be used for the two or more phases. Iridium and its oxide, rhodium and its oxide, and platinum and platinum-rhodium may also be used. A wet etchant comprising ceric ammonium nitrate and acetic acid may be used.

Abstract: A method for repairing a damaged gate oxide layer while making the gate oxide layer resistant to gate oxide degradation including providing a silicon substrate having an overlying gate oxide layer and a polysilicon layer overlying the gate oxide layer; forming a polycide layer over the polysilicon layer; photolithographically patterning the polycide layer for dry etching a gate structure; dry etching a gate structure including etching through a thickness of the polycide layer including a fluorine containing etching chemistry to produce implanted fluorine in the polycide layer; and, thermally annealing the silicon substrate including the gate structure to thermally diffuse the implanted fluorine to an interface region of the gate oxide and the silicon substrate to form chemical bonds with silicon.

Abstract: A method (40) of forming an integrated circuit (60) device including a substrate (64). The method including the step of first (42), forming a gate stack (62) in a fixed relationship to the substrate, the gate stack including a gate having sidewalls. The method further includes the step of second (42), implanting source/drain extensions (701, 702) into the substrate and self-aligned relative to the gate stack. The method further includes the steps of third (46, 48), forming a first sidewall-forming layer (72) in a fixed relationship to the sidewalls and forming a second sidewall-forming layer (74) in a fixed relationship to the sidewalls. The step of forming a second sidewall-forming layer includes depositing the second sidewall-forming layer at a temperature equal to or greater than approximately 850° C.

Abstract: In a method of fabricating a semiconductor device, a gate oxide layer is provided on a silicon substrate. A first polysilicon layer is provided on the gate oxide layer, a dielectric layer is provided on the first polysilicon layer, and a second polysilicon layer is provided on the dielectric layer. Upon appropriate masking, an etch step is undertaken, etching the second polysilicon layer, dielectric layer, first polysilicon layer, and gate oxide layer to remove portions thereof to expose the silicon substrate and to form a stacked gate structure on the silicon substrate. A rapid thermal anneal is undertaken for a short period of time, i.e., for example 10-20 seconds, to grow a thin oxide layer on the stacked gate structure. Then, another oxide layer is deposited over the oxide layer which was formed by rapid thermal anneal.

Abstract: A reaction chamber for processing a substrate wafer is described. The reaction chamber has a wafer holder for receiving the substrate wafer, a convection plate, which is disposed above the wafer holder, for suppressing convective movements over the substrate wafer, and a gas distributor plate which is disposed on a side face of the reaction chamber, for distributing process or purge gases that flow in. A flow plate is disposed on the gas distributor plate and extends substantially in a plane that is perpendicular to the gas distributor plate. This allows rapid and efficient purging of the reaction chamber.

Abstract: A method and an apparatus utilized for thermal processing of substrates during semiconductor manufacturing. The method includes heating the substrate to a predetermined temperature using a heating assembly, cooling the substrate to the predetermined temperature using a cooling assembly located such that a thermal conductance region is provided between the heating and cooling assemblies, and adjusting a thermal conductance of the thermal conductance region to aid in heating and cooling of the substrate. The apparatus includes a heating assembly, a cooling assembly located such that a thermal conductance region is provided between the heating and cooling assemblies, and a structure or configuration for adjusting a thermal conductance of the thermal conductance region.

Abstract: A flip chip method of joining a chip and a substrate is described. A thermo-compression bonder is utilized to align the chip and substrate and apply a contact force to hold solder bumps on the substrate against metal bumps on the chip. The chip is rapidly heated from its non-native side by a pulse heater in the head of the bonder until the re-flow temperature of the solder bumps is reached. Proximate with reaching the re-flow temperature at the solder bumps, the contact force is released. The solder is held above its re-flow temperature for several seconds to facilitate wetting of the substrate's metal protrusions and joining. A no-clean flux that has a volatilization temperature below the melting point of the solder bumps is utilized to minimize or eliminate the need for a post interconnection de-flux operation.

Abstract: A contact structure incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe2)4, as the precursor. The contact structure is fabricated by etching a contact opening through an dielectric layer down to a diffusion region to which electrical contact is to be made. Titanium metal is deposited over the surface of the wafer so that the exposed surface of the diffusion region is completely covered by a layer of the metal. At least a portion of the titanium metal layer is eventually converted to titanium silicide, thus providing an excellent conductive interface at the surface of the diffusion region. A titanium nitride barrier layer is then deposited using the LPCVD process, coating the walls and floor of the contact opening. Chemical vapor deposition of polycrystalline silicon or of a metal follows.

Abstract: A method of manufacturing a semiconductor device, according to the present invention comprises a step for forming an insulating film over a semiconductor wafer and thereafter subjecting the same to photolithography and etching to thereby define a contact hole, a step for forming an adhesive layer over the insulating film with the contact hole defined therein, a step for placing the interior of a processing chamber under an atmosphere uncontaining oxygen and subjecting the adhesive layer to heat treatment, a step for setting the temperature of the semiconductor wafer to less than or equal to a temperature equivalent to energy of such an extent as to cut the bonding between atoms which form the adhesive layer and thereafter taking the semiconductor wafer out of the processing chamber, and a step for forming an embedding film to be embedded in the contact hole.

Abstract: A semiconductor device, including: a diffusion barrier layer composed of ternary compound elements formed on a substrate, wherein the diffusion barrier contains ruthenium, titanium and nitrogen; and a capacitor formed on the diffusion barrier layer, wherein the capacitor includes a bottom electrode formed on the diffusion barrier layer, a dielectric layer formed on the bottom electrode and a top electrode formed on the dielectric layer.

Abstract: The present invention is directed to an apparatus and process for heating and cooling semiconductor wafers in thermal processing chambers. In particular, the apparatus of the present invention includes a cooling device for actively cooling the wafers after the wafers have been heated. During use, the cooling device can be movable towards and away from a wafer placed in the chamber for selectively cooling the wafer at desired times. In an alternative embodiment, a gas can be directed towards the wafer for rapidly reducing the temperature of the wafer at the completion of the process. Alternatively, the wafer can be lowered to close proximity of a cooling member to achieve active and selective cooling.

Abstract: This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized, sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduces the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.

Abstract: A method of performing a two stage anneal in the formation of an alloy interconnect can include forming a via aperture in a dielectric layer where the via aperture provides an area for formation of a via, providing a seed layer along lateral side walls of the via aperture, rapid thermal annealing the seed layer to facilitate copper grain growth in the via, and slowly annealing the seed layer to facilitate desired distribution of alloy doping. The use of two anneals-one fast (e.g., 60 seconds) at lower temperatures (e.g., 150° C. to 250° C.) and one slow (e.g., minutes to several hours) at higher temperatures (e.g., 200° C. to 450° C.)—helps to control grain growth and alloy doping distribution.

Abstract: An integrated circuit has a multi-layer stack such as a gate stack or a digit line stack disposed on a layer comprising silicon. A conductive film is formed on the transition metal boride layer. A process for fabricating such devices can include forming the conductive film using a vapor deposition process with a reaction gas comprising fluorine. In the case of a gate stack, the transition metal boride layer can help reduce or eliminate the diffusion of fluorine atoms from the conductive film into a gate dielectric layer. Similarly, in the case of digit line stacks as well as gate stacks, the transition metal boride layer can reduce the diffusion of silicon from the polysilicon layer into the conductive film to help maintain a low resistance for the conductive film.

Abstract: The invention provides a method for forming a metal nitride film by depositing a metal oxide film on the substrate and exposing the metal oxide film to a nitrating gas to densify the metal oxide and form a metal nitride film. The metal oxide film is deposited by the decomposition of a chemical vapor deposition precursor. The nitrating step comprises exposing the metal oxide film to a thermally or plasma enhanced nitrating gas preferably comprising nitrogen, oxygen, and ammonia. The invention also provides a process for forming a liner/barrier scheme for a metallization stack by forming a metal nitride layer over the substrate by the densification of a metal oxide layer by a nitrating gas depositing a metal liner layer. Optionally, a metal liner layer may be deposited over substrate prior to the metal nitride layer to forma metal/metal nitride liner/barrier scheme.

Abstract: A system for fabricating an integrated circuit is disclosed that includes providing a semiconductor substrate (10), and forming a gate oxide layer (12) on an active area on the substrate. A polysilicon gate (14) is formed, on top of the gate oxide, by etching. Etch damage (16) on the substrate surface is repaired by anneal in an inert gas environment—e.g., He, Ne, N2, Ar gas, or combinations thereof.

Abstract: The invention enables a layer of metal to be formed on a substrate with few or no voids formed in the layer, with increased throughput and without raising the temperature of the substrate to a level that may damage the substrate. A layer of metal can be formed on a substrate using a cold deposition step followed by a hot deposition step. The cold deposition step need only be performed for a time sufficient to deposit metal over the entire surface on which the metal layer is to be formed. In the hot deposition step, further metal is deposited while the substrate is rapidly heated to a target temperature. The rapid heating quickly mobilizes the atoms of the deposited metal, making the deposited metal far less susceptible to cusping and voiding than has been the case with previous methods for depositing a metal layer on a substrate that include a cold deposition step followed by a hot deposition step.

Abstract: A method of reducing electromigration in copper interconnect lines by restricting Cu-diffusion pathways along a Cu surface via doping the Cu surface with Zn from an interim copper-zinc alloy (Cu—Zn) thin film electroplated on the copper (Cu) surface from a stable chemical solution, and controlling the Zn-doping thereof, which also improves interconnect reliability and corrosion resistance, and a semiconductor device thereby formed. The method involves using interim reduced-oxygen Cu—Zn alloy thin films for forming an encapsulated dual-inlaid interconnect structure. The films are formed by electroplating a Cu surface via by electroplating, the Cu surface in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants; and annealing the interim electroplated Cu—Zn alloy thin films and a Cu-fill; and planarizing the interconnect structure.

Abstract: An epitaxial rare earth oxide (001)/silicon (001) structure is realized by epitaxially growing a rare earth oxide such as cerium dioxide in the (001) orientation on a (001)-oriented silicon substrate. For this purpose, the surface of the (001)-oriented Si substrate is processed into a dimer structure by 2×1, 1×2 surface reconstruction, and a rare earth oxide of a cubic system or a tetragonal system, such as CeO2 film, is epitaxially grown in the (001) orientation on the Si substrate by molecular beam epitaxy, for example. During this growth, a source material containing at least one kind of rare earth element is supplied after the supply of an oxidic gas is supplied onto the surface of the Si substrate. If necessary, annealing is conducted in vacuum after the growth.

Abstract: A semiconductor device of the present invention includes a conductive film made up of a polysilicon film, a barrier metal film and a high melting point, metal nitride film sequentially laminated in this order. The conductive film is annealed to lower the resistance of the metal nitride film. Annealing causes the metal nitride film, which is formed in an amorphous state, to release nitrogen and increases the crystal size of metal having a high melting point. This successfully improves the crystallization of the high melting point metal and lowers the resistance of the metal nitride film without regard to the crystallization of the underlying barrier metal film. It is therefore possible to improve the crystallization of the metal nitride film or to obviate the step of providing the barrier metal film with a double-layer structure, i.e., to simplify the production procedure. A method of producing the semiconductor device is also disclosed.

Abstract: A liquid precursor for forming a layered superlattice material is applied to an integrated circuit substrate. The precursor coating is annealed in oxygen using a rapid temperature pulsing anneal (“RPA”) technique with a ramp rate of 30° C./second at a hold temperature of 650° C. for a holding time of 30 minutes. The RPA technique includes applying a plurality of rapid-temperature heat pulses in sequence.

Abstract: The present invention provides a method for filling an aperture on a substrate by depositing a metal film on the substrate of insufficient thickness to fill the sub half-micron aperture and then annealing the substrate in a low pressure chamber at a temperature below a melting point of the deposited metal film. The present invention further provides forming a planarized film over the void-free aperture by physical vapor depositing a metal film over the annealed film.

Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.

Abstract: A method for forming a silicide of a metal with high-melting-point in a semiconductor device includes the step of removing a higher-density impurity area which acts for prevention of forming the metal-silicide layer on the surface of the impurity-diffused region between the steps of implanting impurities to form an impurity-implanted region and annealing for reactions of cobalt and silicon of the diffused layer. The above-mentioned method of forming the metal-silicide layer on the surface of the impurity-diffused region proceeds smoothly to thereby prevent degradation of the initial gate withstand voltage and a higher sheet resistance.

Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.

Abstract: A method of preventing formation of titanium oxide within a semiconductor device structure during a high temperature treatment of the device structure includes forming a passivation layer to preclude formation of titanium oxide at a titanium/oxide interface of a semiconductor device structure. The method includes providing a substrate assembly including at least an oxide region and forming a layer of titanium over a surface of the oxide region. The oxide region surface is treated with a plasma comprising nitrogen prior to forming the titanium layer so as to form a passivation layer upon which the titanium layer is formed. A thermal treatment is performed on the substrate assembly with the passivation layer substantially inhibiting diffusion of oxygen from the oxide layer during the thermal treatment of the substrate assembly. Generally, the passivation layer comprises SixOyNz.

Abstract: A thin film photovoltaic devices is described, having a glass substrate 11 over which is formed a thin film silicon device having an n++ layer 12, a p layer 13 and a dielectric layer 14 (typically silicon oxide or silicon nitride). To create a connection through the p layer 13 to the underlying n++ layer 12, a column of semi-conductor material is heated, the column passing through the various doped layers and the material in the column being heated or melted to allow migration of dopant between layer of the device in the region of the column.

Abstract: A polysilicon layer is formed on a semiconductor substrate followed by performing a collimator physical vapor deposition (PVD) process to form a titanium nitride layer on the polysilicon layer. A rapid thermal nitridation (RTN) process is then performed to tighten the structure of the titanium nitride layer. Finally, a silicide layer is formed on the barrier layer. By using the titanium nitride layer, the interface between the silicide layer and the polysilicon layer is effective prevented from occurring a spike.

Abstract: The present invention provides an improved semiconductor device of a Silicon/Amorphous Silicon/Metal Structure (SASM) and a method of making an improved semiconductor device by a salicide process by using an anneal to form a thick silicide film on shallow source/drain regions and a chemical-mechanical polish (CMP) step is then performed to remove the silicide over the top of the spacers at the gate, thus breaking the continuity of the silicide film extending from the gate to the source drain region.

Abstract: Conductive contacts in a semiconductor structure, and methods for forming the conductive components are provided. The method comprises depositing a conductive material over a substrate to fill a contact opening, removing excess material from the substrate leaving the contact within the opening, and then heating treating the contact at a high temperature, preferably with a rapid thermal anneal process, in a reactive gas to remove an undesirable component from the contact, for example, thermal annealing a TiCl4-based titanium nitride in ammonia to remove chlorine from the contact, which can be corrosive to an overlying aluminum interconnect at a high concentration. The contacts are useful for providing electrical connection to active components in integrated circuits such as memory devices. In an embodiment of the invention, the contacts comprise boron-doped and/or undoped TiCl4-based titanium nitride having a low concentration of chlorine.

Abstract: Method for fabricating a polycide dual gate in a semiconductor device fabricates a dual gate having polycide gate electrodes. The polycide can be a cobalt polycide, for example. The method can include forming polysilicon pattern layers on a first and a second regions of a semiconductor substrate, forming a blocking layer to expose top surfaces of the polysilicon pattern layers and mask the substrate, and forming a metal layer on an entire surface and then is annealed to form a gate electrode having a stack of the polysilicon pattern layer under a silicide layer. Impurity ions of opposite conductivities in the first and second regions can be respectively deposited and diffused to form source/drain regions in surfaces of the substrate on both sides of the gate electrode. The implanted impurity ions can further implant ions in the silicide/polysilicon pattern layer gate to reduce fabrication steps or simplify the fabrication process.

Abstract: Within a method for fabricating a microelectronic fabrication having formed therein a copper containing conductor layer passivated with a passivation layer, there is first: (1) pre-heated the copper containing conductor layer to a temperature of from about 300 to about 450 degrees centigrade for a time period of from about 30 to about 120 seconds to form a pre-heated copper containing conductor layer; and then (2) plasma treated the pre-heated copper containing conductor layer within a reducing plasma to form a plasma treated pre-heated copper containing conductor layer; prior to (3)forming upon the plasma treated pre-heated copper containing conductor layer the passivation layer. The foregoing process sequence provides for attenuated hillock defects within the plasma treated pre-heated copper containing conductor layer when forming the passivation layer thereupon.

Abstract: The invention includes a method of forming a semiconductor construction. A metal-rich metal silicide layer is formed on a silicon-comprising substrate, and a metal nitride layer is formed on the metal-rich metal silicide layer. The metal-rich metal silicide layer and metal nitride layer are thermally processed to convert some of the metal-rich metal silicide into a stoichiometric metal silicide region. The thermal processing also drives nitrogen from the metal nitride layer into the metal-rich metal silicide layer to convert some of the metal-rich metal silicide layer into a region comprising metal, silicon and nitrogen. The invention also includes semiconductor constructions comprising a layer of MSi2 and a layer of MSiqNr, where M is Ta, W or Mo, and both q and r are greater than 0 and less than 2.

Abstract: The present invention is related to a method for depositing a metal-containing film from a metal plating bath, comprising the steps of subsequently depositing a metal-containing layer from a metal plating bath followed by a heating step and/or a vacuum step, said subsequent steps being repeated for a number of times in different sequences.

Abstract: This invention relates to a method for decreasing the resistivity of the gate and leaky junction of the source/drain, more particularly, to the method for forming a metal silicide layer at the gate region and the source/drain region by using two times in depositing metal layer. This condition will form a thicker metal silicide layer at the gate region to decrease the resistivity of the gate and will form a thinner metal silicide layer at the source/drain region to decrease defects in leaky junction at the source/drain region. At first, a semiconductor substrate is provided and a MOS is formed on the substrate and a shallow trench isolation is formed in the substrate. The MOS comprises a gate region, a source region, a drain region, and a spacer which is formed on the sidewall of the gate. The first metal layer is formed over the MOS and a oxide layer is formed over the first metal layer. Partial oxide layer is etched to show the first metal layer which is formed on the gate.

Abstract: First of all, a semiconductor substrate that has a memory array and a periphery region thereon is provided. Then a barrier layer is formed on the gate devices of the memory array and the periphery region and on the semiconductor substrate. Next, an organic layer is formed on the barrier layer. Afterward, removing the organic layer and the barrier layer until exposing the gate devices of the memory array and the periphery region. The remainder of the organic layer is then removed by way of using an ashing process. Subsequently, a photoresist layer is formed on the memory array, and the barrier layer of the periphery region is etched until exposing the surface of the semiconductor substrate. Finally, performing a silicide process after removing the photoresist layer, so as to individually form a salicide layer on the gate devices of the memory array and the periphery region, and on the semiconductor substrate of the periphery region.

Abstract: An apparatus and method is provided for rapid thermal processing (RTP) of semiconductor wafers that compensates for variations in heat absorption characteristics of the wafers. Wafer-to-wafer temperature variation is substantially eliminated using a model of the heat absorption characteristics of different wafer types to predict a steady state temperature of a wafer undergoing processing. This prediction is used to detect potential variations in wafer temperature during the RTP process and correct for these variations by adjusting the output of the heat source.

Abstract: A semiconductor device which can reduce contact resistance, is disclosed. A semiconductor device according to the present invention includes a lower conductor pattern and an upper conductor pattern. The lower conductor pattern is in contact with the upper conductor pattern. The lower conductor pattern includes a first doped polysilicon layer, a first tungsten silicide layer and a cap layer formed sequentially. Here, the cap layer is formed to a doped polysilicon layer containing a small amount of tungsten and has stoichiometrical equivalent ratio x of Si higher than the first tungsten silicide layer. The upper conductor pattern includes a second doped polysilicon layer and a second tungsten layer formed sequentially. The contact of lower conductor pattern and the upper conductor pattern is substantially formed between the cap layer and the second doped polysilicon layer. Preferably, stoichiometrical equivalent ratio x of Si for the first tungsten silicide layer is 2.3 to 2.