Abstract: A method is provided for manufacturing a semiconductor device with a highly controlled impurity layer without influence from the heat treatment involved in epitaxial growth. The method comprises: forming a dummy gate layer above a semiconductor substrate; forming a spacer layer closely adjacent to each side of the dummy gate layer; selectively forming a silicon layer by epitaxial growth above the semiconductor substrate; forming a gate electrode after removing the dummy gate layer; forming a source/drain region by introducing an impurity into the semiconductor substrate through the silicon layer; and changing the silicon layer into silicide.

Abstract: A method for repairing a damaged gate oxide layer while making the gate oxide layer resistant to gate oxide degradation including providing a silicon substrate having an overlying gate oxide layer and a polysilicon layer overlying the gate oxide layer; forming a polycide layer over the polysilicon layer; photolithographically patterning the polycide layer for dry etching a gate structure; dry etching a gate structure including etching through a thickness of the polycide layer including a fluorine containing etching chemistry to produce implanted fluorine in the polycide layer; and, thermally annealing the silicon substrate including the gate structure to thermally diffuse the implanted fluorine to an interface region of the gate oxide and the silicon substrate to form chemical bonds with silicon.

Abstract: Direct focused ion beam (FIB) mixing is given as a method for patterning of metal silicide structures on a silicon surface. This technique allows the fabrication of submicron structures without the use of resist-based lithography methods. VLSI containing metal silicide connects, interconnects and structures may be prepared by the method. Fast semiconductor devices having good circuit speed and reduced RC time delay including the technologies MEMS, MOSFET, CMOS, pMOS, nMOS and BiCMOS result.

Abstract: The present invention discloses a method for forming a self-aligned silicidation of a metal oxide semiconductor. The feature of the present invention is to perform an ionic implanting step before carrying on the self-aligned silicidation. The implanted ion of the present invention, such as fluorine, chlorine, bromine, iodine, boron and trifluroborane, will react with the silicon on the surface of the gate structure and the silicon substrate and a barrier effect will be formed during silicidation. Therefore, a spike phenomenon because of the penetration of cobalt or the cobalt silicide into the gate structure or the source/drain regions is prevented. The junction leakage current and the breakdown voltage of the metal oxide semiconductor are avoided.

Abstract: The present invention provides a semiconductor device having a metal suicide layer and a method for forming the metal silicide layer, the semiconductor device having a metal silicide-semiconductor contact structure, wherein the semiconductor device includes a substrate, an insulation layer with an opening, in which a metal silicide layer is formed using a native metal silicide with a first phase and a second phase, upon which a conductive layer is formed. The second phase has a first stoichiometrical composition ratio different from a second stoichiometrical composition ratio of the first phase. A reaction between the metal silicide layer of the first phase and the silicon results in the metal silicide layer of the second phase having high phase stability and low resistance.

Abstract: An integrated circuit device, and a method of manufacturing the same, comprises an epitaxial nickel silicide on (100) Si, or a stable nickel silicide on amorphous Si, fabricated with a cobalt interlayer. In one embodiment the method comprises depositing a cobalt (Co) interface layer between the Ni and Si layers prior to the silicidation reaction. The cobalt interlayer regulates the flux of the Ni atoms through the cobalt/nickel/silicon alloy layer formed from the reaction of the cobalt interlayer with the nickel and the silicon so that the Ni atoms reach the Si interface at a similar rate, i.e., without any orientation preference, so as to form a uniform layer of nickel silicide. The nickel silicide may be annealed to form a uniform crystalline nickel disilicide. Accordingly, a single crystal nickel silicide on (100) Si or on amorphous Si is achieved wherein the nickel silicide has improved stability and may be utilized in ultra-shallow junction devices.

Abstract: A main electrode is connected to an n-type semiconductor layer selectively formed on a major surface of a silicon substrate. A silicide layer is interposed between the main electrode and the semiconductor layer. The silicide layer is heat-treated at 600° C. to 850° C. for at least 30 minutes, to have an epitaxial layer selectively epitaxially growing in a specific direction such as the <110> direction toward the semiconductor layer. Therefore, irregularities are formed on the interface between the suicide layer and the semiconductor layer. The interface resistivity between the silicide layer and the semiconductor layer is low due to the presence of the epitaxial layer, and besides the contact area of the interface is large due to the irregularities of the interface. Consequently, the contact resistance between the main electrode and the semiconductor layer is effectively reduced. Thus, the contact resistance between the main electrode and the semiconductor substrate is reduced.

Abstract: Silicide interfaces for integrated circuits, thin film devices, and backend integrated circuit testing devices are formed using a barrier layer, such as titanium nitride, disposed over a porous, thin dielectric layer which is disposed between a silicon-containing substrate and a silicidable material which is deposited to form the silicide interfaces for such devices. The barrier layer prevents the formation of a silicide material within imperfections or voids which form passages through the thin dielectric layer when the device is subjected to a high temperature anneal to form the silicide contact from the reaction of the silicidable material and the silicon-containing substrate.

Abstract: A method for making a flexible metal silicide local interconnect structure. The method includes forming an amorphous or polycrystalline silicon layer on a substrate including at least one gate structure, forming a layer of silicon nitride over the silicon layer, removing a portion of the silicon nitride layer, oxidizing the exposed portion of the silicon layer, removing the remaining portion of the silicon nitride layer, optionally removing the oxidized silicon layer, forming a metal layer over the resulting structure, annealing the metal layer in an atmosphere comprising nitrogen, and removing any metal nitride regions. The local metal silicide interconnect structure may overlie the at least one gate structure. The methods better protect underlying silicon regions (e.g., substrate), as well as form TiSix local interconnects with good step coverage. Intermediate and resulting structures are also disclosed.

Abstract: Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices are formed by a salicide process wherein a blanket nickel layer is formed in contact with the exposed portions of the substrate surface adjacent the sidewall spacers, the top surface of the gate electrode, and the sidewall spacers. Embodiments include forming the blanket layer of nickel is formed by the sequential steps of: (i) forming a layer of nickel by sputtering with xenon gas; and, (ii) forming a layer of nickel by sputtering with argon gas. The two step process for forming the blanket layer of nickel advantageously prevents the formation of nickel silicide on the outer surfaces of the insulative sidewall spacers.

Abstract: A method for forming silicide contacts includes forming a layer on silicon-containing active device regions such as source, drain, and gate regions. The layer contains a metal that is capable of forming one or more metal silicides and a material that is soluble in a first metal silicide but not soluble in a second metal silicide, or is more soluble in the first metal silicide than in the second metal silicide. The layer may be formed by vapor deposition methods such as physical vapor deposition, chemical vapor deposition, evaporation, laser ablation, or other deposition method. A method for forming silicide contacts includes forming a metal layer, then implanting the metal layer and/or underlying silicon layer with a material such as that described above. The material may be implanted in the silicon layer prior to formation of the metal layer. Contacts formed include a first metal silicide and a material that is more soluble in a first metal silicide than in a second metal silicide.

Abstract: A refractory metal film is formed over a semiconductor substrate, and a first nitride film is formed over the refractory metal film. Thereafter, the refractory metal film and the nitride film are patterned and the sides of the patterned refractory metal film are nitrided.

Abstract: The invention includes a method of forming a semiconductor construction. A metal-rich metal suicide layer is formed on a silicon-comprising substrate, and a metal nitride layer is formed on the metal-rich metal silicide layer. The metal-rich metal silicide layer and metal nitride layer are thermally processed to convert some of the metal-rich metal silicide into a stoichiometric metal silicide region. The thermal processing also drives nitrogen from the metal nitride layer into the metal-rich metal silicide layer to convert some of the metal-rich metal silicide layer into a region comprising metal, silicon and nitrogen. The invention also includes semiconductor constructions comprising a layer of MSi2 and a layer of MSiqNr, where M is Ta, W or Mo, and both q and r are greater than 0 and less than 2.

Abstract: In a crystalline silicon body a shallow trench insulation is made by etching a groove and filling it with silicon oxide. Ridges of polysilicon are made on the surface of the silicon body by applying a layer of polysilicon and patterning it with a known technique. Spacers of silicon nitride are provided on the side walls of the polysilicon ridges. A first layer of silicon nitride, a second layer of TEOS and a patterned resist layer are applied. The TEOS layer is etched by immersion in a solution of 0.36% HF for 14 minutes. Subsequently, the resist is stripped in H2SO4 or peroxide. The silicon nitride layer is etched by immersion in phosphoric acid of 165° C. for 15 minutes using the TEOS layer as a mask. A titanium layer is applied. Subsequently, the body is rapidly heated to a temperature of 760° C. at which it is kept for 20 seconds. During this rapid thermal treatment titanium silicide is formed at locations where the titanium is in contact with silicon i.e.

Abstract: A cluster tool and a number of different processes for making a cobalt-silicide material are disclosed. Combinations of alloyed layers of Co—Ti— along with layers of Co— are arranged and heat treated so as to effectuate a silicide reaction. The resulting structures have extremely low resistance, and show little line width dependence, thus making them particularly attractive for use in semiconductor processing. A cluster tool is configured with appropriate sputter targets/heat assemblies to implement many of the needed operations for the silicide reactions, thus resulting in higher savings, productivity, etc.

Abstract: A method for manufacturing a semiconductor device can simply form a silicide film for reducing ohmic contact between a metal line and a substrate and a ternary phase thin film as an amorphous diffusion prevention film between a metal line and the silicide film. The method for manufacturing a semiconductor device includes the steps of sequentially forming a first refractory metal and a second refractory metal on a semiconductor substrate, forming a silicide film on an interface between the semiconductor substrate and the first refractory metal, and reacting the semiconductor substrate with the first and second refractory metals on the silicide film to form a ternary phase thin film.

Abstract: A method (and structure formed thereby) of forming a metal silicide contact on a non-planar silicon containing region having controlled consumption of the silicon containing region, includes forming a blanket metal layer over the silicon containing region, forming a silicon layer over the metal layer, etching anisotropically and selectively with respect to the metal the silicon layer, reacting the metal with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal layer, annealing at a second temperature to form an alloy of metal-Si2, and selectively etching the unreacted silicon layer.

Abstract: A method for forming a thicker silicide over a MOS device is described. This is achieved using a process where the gate structure is formed by conventional techniques upon a substrate. A low-energy implantation is performed to form lightly doped source and drain (LDD) regions in the substrate in the areas not protected by the gate structure. A first spacer composed of tetraethyl-oxysilane (TEOS oxide), for example, is formed along the sidewalls of the gate structure. A second low-energy implantation is performed to form the source and drain (S/D) in the areas not protected by the gate structure and first spacer. A layer of metal such as titanium (Ti), for example, is then deposited over the surface of the gate structure. A second sidewall spacer composed of titanium nitride (TiN), for example, is formed along the sidewalls of the gate structure covering the metal over the first sidewall spacer and covering the metal over isolation regions.

Abstract: A semiconductor device is fabricated by providing a substrate, and providing a dielectric layer on the substrate. A polysilicon body is formed on the dielectric layer, and a metal layer is provided on the polysilicon body. A silicidation process is undertaken to silicidize substantially the entire polysilicon body to form a gate on the dielectric. In an alternative process, a cap layer is provided on the polysilicon body, which cap layer is removed prior to the silicidation process. The polysilicon body is doped with a chosen specie prior to the silicidation process, which dopant, during the silicidation process, is driven toward the dielectric layer to form a gate portion having a high concentration thereof adjacent the dielectric, the type and concentration of this specie being instrumental in determining the work function of the formed gate.

Abstract: A method for forming a gate stack having a silicide layer that can subsequently undergo a SAC etch is disclosed. The present method provides a layer of insulating material on top of the silicide layer. The insulating material is sufficient to protect the gate stack, including the silicide layer when the low-resistance gate stack is used in subsequent self-aligned contact etch processes.

Abstract: A method of manufacturing a semiconductor device (2) on a substrate (1), the semiconductor device including an active area (5, 6, 16) in the substrate (1) demarcated by spacers (10-13,20-23) and arranged so as to contact an interconnect (29) including TiSi2; the method includes: depositing an oxide layer (26) on the substrate (1); depositing and patterning a resist layer (27) on the oxide (26); reactive ion etching of the oxide (26) to demarcate the active area (5, 6, 16), using the patterned resist layer (27); removing the resist (27) by a dry strip plasma containing at least oxygen; depositing titanium (28) on the oxide (26) and the active area (5, 6, 16); forming the interconnect (29) as self-aligned TiSi2 by a first anneal, a selective wet etch, and a second anneal; the dry strip plasma including, as a second gaseous constituent, at least fluoride.

Abstract: Bridging between nickel suicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by recessing the silicon nitride spacers and forming barrier spacers on top of the silicon nitride spacers. The barrier spacers prevent silicon migration and hence the formation of bridging silicide on the silicon nitride sidewall spacers.

Abstract: Disclosed are methods and systems for forming salicide, in which a semiconductor substrate is provided with at least one exposed silicon surface. The semiconductor substrate is placed into a sputtering chamber. A silicide-forming metal layer, formed of a metal such as Co, Ni, is sputter-deposited over the exposed silicon surface. A process temperature is controlled below room temperature during the sputter deposition and preferably between approximately 0° C. to 10° C. The silicide-forming metal layer formed on the exposed silicon surface is first annealed to convert the silicide-forming metal layer into a salicide layer. Also, the system of the present invention is comprised of a sputter chamber including a mount for mounting a semiconductor substrate and a cooling mechanism coupled with the mount for cooling the semiconductor substrate. The cooling mechanism includes a controller to maintain a process temperature below room temperature.

Abstract: A method for preventing polycide gate spiking, which essentially comprises the following steps: forms an oxide layer on a substrate; forming a polysilicon layer on the oxide layer; sputtering a barrier layer on the polysilicon layer; performing a first rapid thermal process; sputtering a silicide layer on the barrier layer; performing a photolithography process and an etching process to remove part of the silicide layer, part of the barrier layer and part of the polysilicon layer to form a polycide gate; and performing a second rapid thermal process. Further, as it is necessary to use both rapid thermal processes, the invention can be expanded such that only one rapid thermal process is applied. Both rapid thermal processes use almost no oxygen.

Abstract: Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat.

Abstract: A method is disclosed in which differing metal layers are sequentially deposited on silicon-containing regions so that the type and thickness of the metal layers may be adapted to specific characteristics of the underlying silicon-containing regions. Subsequently, a heat treatment is performed to convert the metals into metal silicides so as to improve the electrical conductivity of the silicon-containing regions. In this way, silicide portions may be formed that are individually adapted to specific silicon-containing regions so that device performance of individual semiconductor elements or the overall performance of a plurality of semiconductor elements may significantly be improved. Moreover, a semiconductor device is disclosed comprising at least two silicon-containing regions having formed therein differing silicide portions, wherein at least one silicide portion comprises a noble metal.

Abstract: A first silicide protection film is deposited on a silicon substrate, a first resist pattern having an opening at a prescribed position is formed, a portion of the first silicide protection film exposed from the opening of the first resist pattern is removed to form a first opening in the first silicide protection film, an N+ diffusion layer is formed in a portion of the silicon substrate exposed from the first opening, the first resist pattern is removed, and a metallic film is deposited to form a first silicide layer on the N+ diffusion layer according to a silicide process.

Abstract: In one embodiment of the present inventions, an exhaust outlet in a vacuum processing chamber includes a nonsealing flow restrictor which can facilitate rapid opening and closing of the flow restrictor in some applications. Because the flow restrictor is a nonsealing flow restrictor, the conductance of the flow restrictor in the closed position may not be zero. However, the flow restrictor can restrict the flow of an exhaust gas from the chamber to permit the retention of sufficient processing gas in the chamber to deposit a film on the substrate or otherwise react with the substrate. After a film has been deposited, typically in a thin atomic layer, the exhaust flow restrictor may be opened such that the flow restrictor conductance is significantly increased to a second, higher flow rate to facilitate exhausting residue gas from the chamber. The nonsealing flow restrictor may be closed again to deposit a second layer, typically of a different material onto the substrate.

Abstract: A process for forming a local interconnect includes applying a layer of metal over a semiconductor layer. A layer of metal silicide is formed over the layer of metal. The layer of metal silicide is patterned to define the boundaries of the local interconnect. The metal silicide is reacted with the layer of metal to form a composite structure. The composite structure includes the metal silicide, another metal silicide formed as silicon from the metal silicide reacts with the underlying layer of metal and an intermetallic compound of the metal from the layer of metal and metal from the layer of metal silicide. The unreacted layer of metal is removed with the composite structure remaining as the local interconnect.

Abstract: The invention includes methods of forming a conductive silicide layers on silicon comprising substrates, and methods of forming conductive silicide contacts. In one implementation, a method of forming a conductive silicide layer on a silicon comprising substrate includes reacting oxygen with silicon of a silicon comprising substrate to form oxides of silicon from silicon of the substrate. The oxides of silicon include stoichiometric silicon dioxide and substoichiometric silicon dioxide. The stoichiometric silicon dioxide and substoichiometric silicon dioxide are exposed to ozone to transform at least some of the substoichiometric silicon dioxide to stoichiometric silicon dioxide. After the exposing, a conductive metal silicide is formed in electrical connection with silicon of the silicon comprising substrate.

Abstract: A method for implementing a self-aligned metal silicide gate is achieved by confining a metal within a recess overlying a channel and annealing to cause metal and its overlying silicon to interact to form the self-aligned metal silicide gate. A gate dielectric layer formed of oxynitride or a nitride/oxide stack is formed on the bottom and sidewalls of the recess prior to depositing the silicon. The metal is removed except for the portion of the metal in the recess. A planarization step is performed to remove the remaining unreacted silicon by chemical mechanical polishing until no silicon is detected.

Abstract: A single rapid thermal anneal (RTA) process is used to form a low resistivity titanium silicide layer atop a polysilicon gate layer for a MOSgated device. The process employs an amorphous silicon layer formed atop the polysilicon layer, followed by forming a titanium layer atop the amorphous silicon. A single RTA process at a temperature below the temperature of contamination diffusion is carried out, preferably at about 650° C. for 30 seconds. The top of the annealed titanium silicide layer is then stripped, and the remaining layer has a sheet Rho of less than about 2 ohms per square.

Abstract: Silicide interfaces for integrated circuits, thin film devices, and backend integrated circuit testing devices are formed using a barrier layer, such as titanium nitride, disposed over a porous, thin dielectric layer which is disposed between a silicon-containing substrate and a silicidable material which is deposited to form the silicide interfaces for such devices. The barrier layer prevents the formation of a silicide material within imperfections or voids which form passages through the thin dielectric layer when the device is subjected to a high temperature anneal to form the silicide contact from the reaction of the silicidable material and the silicon-containing substrate.

Abstract: A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.

Abstract: The invention includes a method of forming a semiconductor construction. A metal-rich metal silicide layer is formed on a silicon-comprising substrate, and a metal nitride layer is formed on the metal-rich metal silicide layer. The metal-rich metal silicide layer and metal nitride layer are thermally processed to convert some of the metal-rich metal silicide into a stoichiometric metal silicide region. The thermal processing also drives nitrogen from the metal nitride layer into the metal-rich metal silicide layer to convert some of the metal-rich metal silicide layer into a region comprising metal, silicon and nitrogen. The invention also includes semiconductor constructions comprising a layer of MSi2 and a layer of MSiqNr, where M is Ta, W or Mo, and both q and r are greater than 0 and less than 2.

Abstract: A non-volatile memory device and a fabrication method thereof are provided. A first polysilicon layer, an inter-gate dielectric layer, a second polysilicon layer and a capping layer are stacked sequentially. A first opening is formed through the inter-gate dielectric layer, the second polysilicon layer and the capping layer, thereby exposing the first polysilicon layer. A second opening is formed through the capping layer, thereby exposing the second polysilicon layer. On the resultant structure, a metal layer is formed and then thermally treated. As a result a metal silicide layer can be formed on the exposed portion of the first polysilicon layer and the exposed portion of the second polysilicon layer.

Abstract: A first metal film of a first metal is deposited on a silicon-containing film containing silicon as a principal constituent, and a second metal film of a nitride of a second metal is deposited on the first metal film. Thereafter, a metal film with a high melting point is deposited on the second metal film, so as to form a multi-layer film of the silicon-containing film, the first metal film, the second metal film and the metal film with a high melting point. The multi-layer film is then subjected to annealing at a temperature of 750° C. or more. In this case, the first metal is nitrided to be changed into a nitride of the first metal and a silicide layer of the first metal is not formed in a surface portion of the silicon-containing film before the annealing.

Abstract: A process for formation of metal silicide on elements of an NMOS device and on elements of a PMOS device, wherein the metal silicide formed on elements of the PMOS device is thinner than the metal silicide simultaneously formed on elements of said NMOS device, has been developed. The process features the implantation of metal ions such as titanium, tantalum, vanadium, or rhenium, during the implantation procedure used for formation of the heavily doped P type source/drain region of the PMOS device. The presence of the implanted metal ions in PMOS regions retard the formation of metal silicide resulting in a thinner metal silicide layer on the heavily doped P type source/drain region, when compared to the thicker metal silicide counterparts simultaneously formed on elements of the NMOS device.

Abstract: A new method of forming MOS transistors with self-aligned silicide has been achieved. A gate oxide layer is formed overlying a semiconductor substrate. A polysilicon layer is deposited. The polysilicon layer and the gate oxide layer are patterned to form gates. Ions are implanted to form lightly doped drain regions. A dielectric layer is deposited. The dielectric layer is polished down to expose the top surface of the gates. The dielectric layer is then anisotropically etched down to form dielectric sidewall spacers. The dielectric sidewall spacers cover a portion of the vertical sidewalls of the gates while exposing a portion of the vertical sidewalls of the gates. Ions are implanted to form source and drain regions. A metal layer is deposited. Contact surfaces are formed between the metal layer with: the exposed top surfaces of the gates, the exposed portions of the vertical sidewalls of the gates, and the exposed source and drain regions.

Abstract: A method for establishing low sheet resistance for the Titanium Salicide process that teaches a C-54 TiSix process by means of an additional vacuum bake. The present invention teaches an additional vacuum bake step prior to pre-metal HF dip during the Si-ion mixing process, an additional vacuum bake step prior to PAI during the PAI process, an additional vacuum bake step prior to pre-metal HF dip during the PAI process.

Abstract: A method of fabricating a semiconductor device having the steps of forming an isolation layer in a silicon substrate to define an active region and a device isolation region; forming a junction region in the active region of the silicon substrate; forming an interlayer dielectric layer on the silicon substrate; forming a contact hole exposing the junction region by selectively removing the interlayer dielectric layer; selectively removing an exposed portion of the junction region under the contact hole; sequentially forming a thin metal layer and a buffer layer on the resultant structure including over the selectively removed portion of the junction region; and forming a silicide layer in the selectively removed portion of the junction region by performing a heat treatment.

Abstract: Process for forming salicide on active areas of MOS transistors, each MOS transistor comprising a gate and respective source and drain regions, the source and drain regions each comprising a first lightly doped sub-region adjacent the gate and a second highly doped sub-region spaced apart from the gate. The salicide is formed selectively at least over the second highly doped sub-regions of the source and drain regions of the MOS transistors, and not over the first lightly doped sub-region.

Abstract: A method for forming a silicide of a metal with high-melting-point in a semiconductor device includes the step of removing a higher-density impurity area which acts for prevention of forming the metal-silicide layer on the surface of the impurity-diffused region between the steps of implanting impurities to form an impurity-implanted region and annealing for reactions of cobalt and silicon of the diffused layer. The above-mentioned method of forming the metal-silicide layer on the surface of the impurity-diffused region proceeds smoothly to thereby prevent degradation of the initial gate withstand voltage and a higher sheet resistance.

Abstract: A silicide film is selectively formed at least on diffusion layers of a MOS transistor. In the method for forming the silicide film includes, a first metal film is selectively formed at least on diffusion layers. A first annealing is applied to allow at least the diffusion layers to react with the first metal film. A part of the sidewalls is removed to form a gap with reacted film of the first metal film. A second annealing is performed at a temperature higher than that of the first annealing to form a reacted film. This makes it possible to form a silicide film having preferable electric characteristics on a gate and diffusion layers being fine in dimension and high in impurity concentration, in a self-aligning fashion without producing “bite of silicide.

Abstract: A transistor device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The device includes a gate defining a channel interposed between a source and a drain formed within the active region of the SOI substrate. Further, the device includes a plurality of thin silicide layers formed on the source and the drain. Additionally, at least an upper silicide layer of the plurality of thin silicide layers extends beyond a lower silicide layer. Further still, the device includes a disposable spacer used in the formation of the device. The device further includes a second plurality of thin silicide layers formed on a polysilicon electrode of the gate.

Abstract: After a cobalt film is deposited on a silicon-containing film formed on a semiconductor substrate, a first heat treatment at a relatively low temperature is performed with respect to the semiconductor substrate to cause a reaction between the cobalt film and the silicon layer and thereby form a Co2Si layer or CoSi layer in at least a surface portion of the silicon layer. Then, a silicon-containing film is deposited on the Co2Si layer or CoSi layer and a second heat treatment at a relatively high temperature is performed with respect to the semiconductor substrate to cause a reaction between the silicon-containing film and the Co2Si layer or CoSi layer and thereby form a CoSi2 layer in at least a surface portion of the silicon layer.

Abstract: There is provided a method of fabricating a MOSFET having a source region and a drain region, having a LDD region, respectively, in respective regions directly beneath the edges of the gate electrode even without forming the sidewalls of the gate electrode. A silicide layer 18 is formed on the surface of a polysilicon layer 16 through selective growth of material used for a gate silicide {FIG. 1(A)}, and thereby a gate electrode made up of the polysilicon layer 16 and the silicide layer 18 is formed. Subsequently, a first implantation of ions in low concentration is performed whereby arsenic ions As+ or phosphorus ions P+, in low concentration, are implanted into the surface of a silicon substrate 10 from a direction at a slant to the surface thereof such that a dopant is implanted into respective regions directly beneath the edges of the polysilicon layer 16, within a region set to form a source and a drain, respectively, on respective sides of the gate electrode {FIG. 1(B)}.

Abstract: A method is provided for making ultra-shallow diffused junctions using an elemental dopant. A semiconductor wafer is cleaned for providing a clean reaction surface. The cleaned wafer in loaded onto a stage located in a doping system. A quantity of elemental dopant atoms are placed in a partially enclosed elemental dopant source which is within a secondary vacuum enclosure. A quantity of the elemental dopant atoms having thermal velocities are deposited onto a surface of the wafer, and the wafer is heated for diffusing the elemental dopant into the wafer. In one embodiment, the heating is conducted by heating the wafer in ultra-high vacuum for diffusing the portion of the doping atoms into the wafer, and the deposition and heating occur simultaneously. In another embodiment, the surface of the wafer is hydrogen terminated, the wafer is removed from the UHV system, and the heating of the wafer is conducted outside of the UHV system by heating the wafer in a furnace.

Abstract: A method for forming a silicide of a metal with high-melting-point in a semiconductor device includes the step of removing a higher-density impurity area which acts for prevention of refractory-metal-silicification of diffused regions between the steps of implanting impurities to form an impurity-implanted region and annealing for refractory-metal-silicification of the diffused layer. The refractory-metal-silicification of the diffused regions proceeds smoothly to thereby prevent degradation of the initial gate withstand voltage and a higher sheet resistance.

Abstract: A method of forming a semiconductor device with a polysilicon layer having a multi-layer tungsten-silicide (WSix) film formed on a surface thereof includes the steps of (1) forming a first layer of tungsten-silicide on the surface of the polysilicon layer; (2) forming a second layer of a material selected from tungsten and silicon on the first layer; (3) forming a third layer of tungsten-silicide on the second layer; and (4) thermally treating the multi-layer film resulting from steps (a)-(c) to form a multi-layer WSix film on the surface of the polysilicon layer, the multi-layer WSix film having a uniform small grain size. In various embodiments, steps (1)-(3) may be repeated one or more times. A semiconductor device includes a semiconductor body having a polysilicon layer formed on a surface thereof and a multilayered WSix film formed on a surface of the polysilicon layer by the process described above.