Abstract: Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat.

Abstract: The present invention can protect from degradation of product reliability of a semiconductor caused during formation of a salicide suppression layer. In order to achieve this, unlike the conventional method in which the sidewall spacer of the gate electrode and the salicide suppression layer in the non-salicide region are formed through two etching processes, the salicide suppression layer and the sidewall spacer are formed at the same time with one etching process after the salicide suppression substance and the sidewall spacer substance are sequentially formed in the present invention, such that it is possible to efficiently prevent an undercut effect from occurring at the spacer side during the etching process for forming the salicide suppression layer, and to effectively prevent the surface of the semiconductor substrate from being damaged.

Abstract: A breakdown voltage of a capacitive element is improved by re-crystallizing a tungsten silicide film under a dielectric film. In forming the capacitive element which uses a polycrystalline silicon film and the tungsten silicide film as a lower electrode, the tungsten silicide film is re-crystallized by heating using an RTA (Rapid Thermal Annealing) system before forming a silicon oxide film used as the dielectric film. By doing so, an interface between the silicon oxide film and the tungsten silicide film is prevented from becoming uneven and a breakdown voltage of the dielectric film is improved drastically. Thus an amount of electric charge stored in the capacitive element is increased as well as it is made possible that the capacitive element is applied to a semiconductor device operating at higher voltage.

Abstract: A method of forming a silicided gate of a field effect transistor on a substrate having active regions is provided. The method includes the following steps: (a) forming a silicide in at least a first portion of a gate; (b) after step (a), depositing a metal over the active regions and said gate; and (c) annealing to cause the metal to react to form silicide in the active regions, wherein the thickness of said gate silicide is greater than the thickness of said silicide in said active regions.

Abstract: A method of forming and a structure of an integrated circuit are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform silicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.

Abstract: The present invention pertains to forming respective silicides on multiple transistors in a single process. High performance is facilitated with simple and highly integrated process flows. As such, transistors, and an integrated circuit containing the transistors, can be fabricated efficiently and at a low cost. The different silicides can be formed with different materials and/or to different thicknesses. As such, the silicides can have different electrical characteristics, such as resistivity and conductivity. These different attributes instill the transistors with different work functions when formed as gate contacts thereon. This provides an integrated circuit containing the transistors with diverse operating capabilities allowing for the execution of operations requiring more flexibility and/or functionality.

Abstract: A method (and resulting structure) for fabricating a silicide for a semiconductor device, includes depositing a metal or an alloy thereof on a silicon substrate, reacting the metal or the alloy to form a first silicide phase, etching any unreacted metal, depositing a silicon cap layer over the first silicide phase, reacting the silicon cap layer to form a second silicide phase, for the semiconductor device, and etching any unreacted silicon. The substrate can be either a silicon-on-insulator (SOI) substrate or a bulk silicon substrate.

Abstract: The invention includes a method of forming a crystalline phase material which includes providing a stress inducing material within or operatively adjacent a crystalline material of a first crystalline phase and annealing the crystalline material of the first crystalline phase to transform it to a second crystalline phase. The stress inducing material induces compressive stress within the first crystalline phase during the anneal to produce a more dense second crystalline phase. Example compressive stress inducing layers include SiO2 and Si3N4, while example stress inducing materials for providing into layers are Ge, W and Co. Example and preferred crystalline phase materials having two phases are refractory metal silicides, such as TiSix. The invention additionally includes incorporating the crystalline phase material into a conductive line.

Abstract: A diffusion layer 3a of a silicon substrate, a polycrystalline silicon material 10, or a gate electrode 12 is connected to a conductive film 8 through a titanium silicide film 6 within a contact hole 5 provided in an insulating film 4. The titanium silicide film 6 is formed by the silicide reaction between a titanium film 7 and the silicon. The upper limit of the thickness of the titanium silicide film 6, and the upper limit of the titanium film 7 are specified by the internal stress within the conductive film 8.

Abstract: The invention includes methods of forming conductive metal silicides by reaction of metal with silicon. In one implementation, such a method includes providing a semiconductor substrate comprising an exposed elemental silicon containing surface. At least one of a crystalline form TiN, WN, elemental form W, or SiC comprising layer is deposited onto the exposed elemental silicon containing surface to a thickness no greater than 50 Angstroms. Such layer is exposed to plasma and a conductive reaction layer including at least one of an elemental metal or metal rich silicide is deposited onto the plasma exposed layer.

Abstract: Nickel silicide formation with significantly reduced interface roughness is achieved by forming a diffusion modulating layer between the underlying silicon and nickel silicide layers. Embodiments include ion implanting nitrogen into the substrate and gate electrode, depositing a thin layer of titanium or tantalum, depositing a layer of nickel, and then heating to form a diffusion modulating layer containing nitrogen at the interface between the underlying silicon and nickel silicide layers.

Abstract: A method of forming a metal plug. First, a dielectric layer is formed on a substrate. Next, a patterned hard mask is formed on the dielectric layer. The dielectric layer is etched through the patterned hard mask to form a contact hole in the dielectric layer so as to expose parts of the substrate. An isolated layer is formed on the patterned hard mask. A barrier is then formed conformally on the isolated layer and the exposed substrate of the contact hole. A metal layer is formed to fill the contact hole and cover the barrier. A thermal treatment is performed to form a silicide between the barrier layer and the substrate. Finally, parts of the metal layer, barrier, isolated layer, and patterned hard mask are removed. The metal plug with a planar surface is thus formed in the contact hole.

Abstract: A method of forming a crystalline phase material includes, a) providing a stress inducing material within or operatively adjacent a crystalline material of a first crystalline phase; and b) annealing the crystalline material of the first crystalline phase under conditions effective to transform it to a second crystalline phase. The stress inducing material preferably induces compressive stress within the first crystalline phase during the anneal to the second crystalline phase to lower the required activation energy to produce a more dense second crystalline phase. Example compressive stress inducing layers include SiO2 and Si3N4, while example stress inducing materials for providing into layers are Ge, W and Co. Where the compressive stress inducing material is provided on the same side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is less than the first phase crystalline material.

Abstract: The present invention provides metallic films containing a Group IVB or VB metal, silicon and optionally nitrogen by utilizing atomic layer deposition (ALD). In particularly, the present invention provides a low temperature thermal ALD method of forming metallic silicides and a plasma-enhanced atomic layer deposition (PE-ALD) method of forming metallic silicon nitride film. The methods of the present invention are capable of forming metallic films having a thickness of a monolayer or less on the surface of a substrate. The metallic films provided in the present invention can be used for contact metallization, metal gates or as a diffusion barrier.

Abstract: A cobalt-containing film on a silicon-containing conductive region, and a titanium-rich capping layer is formed on cobalt-containing film. The atomic % ratio of titanium to other elements (if any) in the titanium-rich capping layer is more than one (1). The resultant structure is annealed so that cobalt of the cobalt-containing film and silicon of the silicon-containing conductive region react with each other to form a cobalt silicide film. When the formation of the cobalt-containing film is carried out at a high temperature, a diffusion restraint interface film is also formed.

Abstract: Disclosed is a method for fabricating a silicide layer of a flat cell memory device.

Abstract: A semiconductor device having a plurality of silicidation steps is provided. In the preferred embodiment in which the semiconductor device is a MOSFET, the source/drain regions are silicided. A dielectric layer is formed and the etch stop layer is removed from the gate electrode of the MOSFET. A second silicidation process is performed to silicide the gate electrode. The process may be performed individually for each transistor, allowing the electrical characteristics of each transistor to be determined individually.

Abstract: Methods of forming thermal oxide layers on a side wall of gate electrodes are disclosed. In particular, thermal oxide layers can be formed on a side wall of a gate electrode by forming a gate electrode on an integrated circuit substrate and forming a thermal oxide layer on a side wall of the gate electrode using a thermal oxidation process. A silicide layer can be formed on the gate electrode after the formation of the thermal oxide layer.

Abstract: The invention concerns a method for forming, in a substrate (1) having a first type of conductivity, a MOS transistor, comprising the following steps: a) forming on the substrate an insulated gate (3); b) implanting a doping agent having a second type of conductivity; c) forming on the edges of the gate silicon nitride spacers; d) simultaneously oxidising the apparent surfaces of the substrate, the gate and the spacers; and e) drain and source implantation.

Abstract: A process for fabricating interconnects is provided. First, a substrate having a dielectric layer and silicon-containing mask layer on the dielectric layer is provided. The dielectric layer is patterned to form an opening. Thereafter, a metallic glue layer is formed over the silicon-containing mask layer and the interior surfaces of the opening. A metallic layer is formed over the substrate to fill the opening and cover the metallic glue layer. A thermal treatment process is next carried out so that the metallic glue layer reacts with the silicon-containing mask layer to form a metal silicide layer. A portion of the metallic layer is removed to expose the metal silicide layer. A solution mixture containing hydrogen peroxide, sulfuric acid, water and hydrofluoric acid is used to remove the metal silicide layer. The silicon-containing mask layer is also removed to expose the dielectric layer.

Abstract: Silicide interfaces for integrated circuits, thin film devices, and back-end integrated circuit testing devices are formed using a barrier layer, such as titanium nitride, disposed over a porous, thin dielectric layer which is disposed between a silicon-containing substrate and a silicidable material which is deposited to form the silicide interfaces for such devices. The barrier layer prevents the formation of a silicide material within imperfections or voids which form passages through the thin dielectric layer when the device is subjected to a high-temperature anneal to form the silicide contact from the reaction of the silicidable material and the silicon-containing substrate.

Abstract: A gate structure having associated (LDD) regions and source and drain is formed as is conventional. A first oxide spacer, for example, is formed along the sidewalls of the gate structure. A layer of metal such as titanium is then deposited over the surface of the gate structure. Second sidewall spacers are formed covering the metal over the first sidewall spacer and covering the metal over isolation regions. A layer of polysilicon is deposited over the surface of the gate structure. A rapid thermal annealing (RTA) is performed causing the metal to react with both the silicon in the junction below the metal and the polysilicon above the metal forming a metal silicide. Metal along the sidewalls between the first and second sidewall spacers and over the isolation regions does not react and is etched away. By providing an additional source of silicon in the polysilicon layer above the metal, a thicker silicide is achieved.

Abstract: An integrated circuit having a gate region, a source drain region, and an electrically nonconductive spacer separating the gate region and the source drain region. A local interconnect electrically connects the gate region to the source drain region across the electrically nonconductive spacer. The local interconnect is formed of a semiconducting material reacted with a metal. The local interconnect may be formed by implanting a precursor species into the electrically nonconductive spacer. A metal layer is deposited over at least the electrically nonconductive spacer, and the integrated circuit is heated to form an electrically conductive local interconnect from the metal layer and the precursor species implanted in the electrically nonconductive spacer.

Abstract: The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semiconductor substrate in the vicinity of the gate electrode. A silicide film is formed on each of the gate electrode and the source-drain diffusion layer. The silicide film positioned on the gate electrode is thicker than the silicide film positioned on the source-drain diffusion layer. The present invention also provides a method of manufacturing a semiconductor device, in which a gate electrode is formed on a gate insulating film covering a semiconductor substrate, followed by forming a source-drain diffusion layer within the semiconductor substrate.

Abstract: A semiconductor substrate has a memory region and a logic region isolated by an isolation insulating film. Plural memory transistors are provided in the form of a matrix in the memory region, and a logic transistor is provided in the logic region. Gate electrodes of memory transistors arranged along the word line direction out of the plural memory transistors are formed as a common gate electrode extending along the word line direction, and impurity diffusion layers working as source/drain regions of memory transistors arranged along the bit line direction are formed as a common impurity diffusion layer extending along the bit line direction. An inter-gate insulating film having its top face at a lower level than the gate electrodes is formed on the semiconductor substrate between the gate electrodes of the plural memory transistors. A sidewall insulating film is formed on the side face of a gate electrode of the logic transistor.

Abstract: Semiconductor devices exhibiting reduced gate resistance and reduced silicide spiking in source/drain regions are fabricated by forming thin metal silicide layers on the gate electrode and source/drain regions and then selectively resilicidizing the gate electrodes. Embodiments include forming the thin metal silicide layers on the polysilicon gate electrodes and source/drain regions, depositing a dielectric gap filling layer, as by high density plasma deposition, etching back to selectively expose the silicidized polysilicon gate electrodes and resilicidizing the polysilicon gate electrodes to increase the thickness of the metal silicide layers thereon. Embodiments further include resilicidizing the polysilicon gate electrodes including a portion of the upper side surfaces forming mushroom shaped metal silicide layers.

Abstract: A memory device and method of manufacturing thereof, wherein a silicide material is selectively formed over active regions of a memory device. A silicide material may also be formed on the top surface of wordlines adjacent the active regions during the selective silicidation process. A single nitride insulating layer is used, and portions of the workpiece are covered with photoresist during the formation of the silicide material.

Abstract: Methods of forming complementary metal oxide semiconductor (CMOS) devices having multiple-threshold voltages which are easily tunable are provided. Total salicidation with a metal bilayer (representative of the first method of the present invention) or metal alloy (representative of the second method of the present invention) is provided. CMOS devices having multiple-threshold voltages provided by the present methods are also described.

Abstract: A method of forming a crystalline phase material includes, a) providing a stress inducing material within or operatively adjacent a crystalline material of a first crystalline phase; and b) annealing the crystalline material of the first crystalline phase under conditions effective to transform it to a second crystalline phase. The stress inducing material preferably induces compressive stress within the first crystalline phase during the anneal to the second crystalline phase to lower the required activation energy to produce a more dense second crystalline phase. Example compressive stress inducing layers include SiO2 and Si3N4, while example stress inducing materials for providing into layers are Ge, W and Co. Where the compressive stress inducing material is provided on the same side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is less than the first phase crystalline material.

Abstract: A method for forming ultra-shallow junctions in a semiconductor wafer with reduced silicon consumption during salicidation supplies additional silicon during the salicidation process. After the gate and source/drain junctions are formed in a semiconductor device, high-resistivity metal silicide regions are formed on the gate and source/drain junctions. Amorphous silicon is then deposited in a layer on the high resistivity metal silicide regions by high density plasma chemical vapor deposition. The deposition of the amorphous-silicon is at an elevated temperature which causes transforming of the high resistivity metal silicide regions to low resistivity metal silicide regions on the gate and source/drain junctions. The deposited amorphous-silicon acts as a source of silicon that is employed as a diffusion species during the transformation of the high resistivity metal silicide to the low resistivity metal silicide.

Abstract: The polysilicon gate electrode of a MOS transistor may be substantially completely converted into a metal silicide without sacrificing the drain and source junctions in that a thickness of the polysilicon layer, for forming the gate electrode, is targeted to be substantially converted into metal silicide in a subsequent silicidation process. The gate electrode, substantially comprised of metal silicide, offers high conductivity even at critical dimensions in the deep sub-micron range, while at the same time the effect of polysilicon gate depletion is significantly reduced. Manufacturing of the MOS transistor, having the substantially fully-converted metal silicide gate electrode, is essentially compatible with standard MOS process technology.

Abstract: A protective layer is formed on a metallic layer prior to forming a metallic silicide layer, and the protective layer has a thickness thicker than that of the metallic layer.

Abstract: A method of fabricating an integrated circuit device comprises forming a refractory metal layer on a silicon-containing substrate, processing the refractory metal layer to form an amorphous metal silicide layer, and depositing an insulating material on the amorphous metal silicide layer. The insulating material is deposited at a temperature that maintains at least a portion of the amorphous metal silicide layer in an amorphous state, to form a capping structure that contains the amorphous metal silicide layer. The method further includes crystallizing the contained amorphous metal silicide layer, and forming an etching stop layer on the capping structure.

Abstract: A system and method for analyzing sheet resistivity of a layer on a wafer employing electrical methods and for controlling rapid thermal annealing (RTA) of the layer is provided. The system includes components for performing RTA on the layer and components for analyzing the sheet resistivity of one or more portions of the layer upon which RTA was performed. The system further includes a feedback generator adapted to accept sheet resistivity data and to produce feedback information that can be used to control the RTA components. The system further includes a data store that can be employed in machine learning and/or to facilitate generating feedback information that can be employed to control RTA and a monitoring application that can be employed to schedule maintenance on the various components in the system.

Abstract: A process for forming a low resistivity titanium silicide layer on the surface of a silicon semiconductor substrate. In the process, an effective amount of a metallic element such as indium, gallium, tin, or lead is implanted or deposited on the surface of the silicon substrate. A titanium layer is deposited on the surface of the silicon substrate, and a rapid thermal annealing of the titanium-coated silicon substrate is performed to form low resistivity titanium silicide. In preferred processes, the metallic element is indium or gallium, and more preferably the metallic element is indium. A semiconductor device that has a titanium silicide layer on the surface of a silicon substrate is also provided.

Abstract: In order to prevent silicides from getting under side walls when the silicides are formed over MOSFET formed over an SOI substrate, trenches are defined in the SOI substrate and side walls are formed over the trenches, whereby the silicides are blocked so as not to get under a gate insulator with a lower portion of each side wall as a structure convex in a downward direction of the substrate. Thus, an increase in gate withstand voltage, a decrease in gate leakage current and control on a short channel effect are achieved.

Abstract: A MOS field effect transistor for reducing the resistance between a source and a drain includes a gate insulation layer and a gate electrode sequentially formed on a semiconductor substrate includes deep source/drain regions formed in upper portions of the semiconductor substrate at both sides of the gate electrode. Source/drain extension regions are formed in upper portions of the semiconductor substrate extending from the deep source/drain regions toward a channel region below the gate electrode to be thinner than the deep source/drain regions. A first silicide layer having a first thickness is formed on the surface of each of the deep source/drain regions. A second silicide layer having a second thickness thinner than the first thickness of the first silicide layer is formed to extend from the first silicide layer in a predetermined upper portion of each of the source/drain extension regions.

Abstract: Process for forming salicide on active areas of MOS transistors, each MOS transistor comprising a gate and respective source and drain regions, the source and drain regions each comprising a first lightly doped sub-region adjacent the gate and a second highly doped sub-region spaced apart from the gate. The salicide is formed selectively at least over the second highly doped sub-regions of the source and drain regions of the MOS transistors, and not over the first lightly doped sub-region.

Abstract: A gate electrode structure in a semiconductor device has a doped polysilicon (DOPOS) film, a tungsten silicide film, a tungsten silicide nitride film, a tungsten nitride film and a tungsten film consecutively as viewed from the substrate. The tungsten silicide nitride film is formed between the tungsten silicide film and the tungsten nitride film by a plurality of heat treatments. The tungsten silicide nitride film has a small thickness of 2 to 5 nm and has a lower interface resistance for achieving a low-resistance gate electrode, suited for a higher-speed operation of the semiconductor device.

Abstract: A process of siliciding uses alloys to reduce the adverse affects of germanium on silicide regions. The alloy can include nickel and at least one of vanadium, tantalum, and tungsten. The process can utilize one or two annealing steps. The process allows better silicidation in SMOS devices. The silicided regions can be provided above a silicon/germanium substrate.

Abstract: Semiconductor devices, such as transistors, with a supersaturated concentration of dopant in the source/drain extension and metal silicide contacts enable the production of smaller, higher speed devices. Supersaturated source/drain extensions are subject to dopant diffusion out from the source/drain extension during high temperature metal silicide contact formation. The formation of lower temperature metal silicide contacts, such as nickel silicide contacts, prevents dopant diffusion and maintains the source/drain extensions in a supersaturated state throughout semiconductor device manufacturing.

Abstract: Methods for reducing the contact resistance presented by the interface between a silicide and a doped silicon region are presented. In a first method, a silicide layer and a doped silicon region form an interface. Either a damage-only species or a heavy, metal is implanted through the silicide layer into the doped silicon region immediately adjacent the interface. In a second method, a second metal is added to the refractory metal before formation of the silicide. After annealing the refractory metal and the doped silicon region, the second metal diffuses into the doped silicion region immediately adjacent the interface without forming additional phases in the silicide.

Abstract: In a semiconductor device using a polysilicon contact, such as a poly plug between a transistor and a capacitor in a container cell, an interface is provided where the poly plug would otherwise contact the bottom plate of the capacitor. The interface bars silicon from the plug from diffusing into the capacitor's dielectric. The interface can also include an oxygen barrier to prevent the poly plug from oxidizing during processing. Below the interface is a silicide layer to help enhance electrical contact with the poly plug. In a preferred method, the interface is created by selectively depositing a layer of titanium over a recessed poly plug to the exclusion of the surrounding oxide. The deposition process allows for silicidation of the titanium. The top half of the titanium silicide is then nitridized. A conformal ruthenium or ruthenium oxide layer is subsequently deposited, covering the titanium nitride and lining the sides and bottom of the container cell.

Abstract: A novel method for forming a C54 phase titanium disilicide film in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A titanium layer is deposited overlying the silicon regions to be silicided. The substrate is subjected to a first annealing whereby the titanium is transformed to phase C40 titanium disilicide where it overlies the silicon regions and wherein the titanium not overlying the silicon regions is unreacted. The unreacted titanium layer is removed. The substrate is subjected to a second annealing whereby the phase C40 titanium disilicide is transformed to phase C54 titanium disilicide to complete formation of a phase 54 titanium disilicide film in the manufacture of an integrated circuit.

Abstract: In one embodiment of the invention, source and drain regions are formed as well as source and drain contact regions. Thereafter source and drain extension regions are formed. In another embodiment, elevated source and drain regions are formed as well as source and drain extension regions. Thereafter source and drain contact regions are formed at a temperature up to about 600° C. and an annealing time of up to about one minute.

Abstract: Metal silcides form low resistance contacts on semiconductor devices such as transistors. Conventional formation of semiconductor devices with metal silicide contacts requires multiple high temperature annealing steps, which can result in crystal damage from dislocations and increased leakage currents. A single, lower temperature annealing step is employed in the invention to produce semiconductor devices with the source/drain regions formed in amorphous regions of a semiconductor substrate and nickel silicide contacts over the source/drain regions. The amorphization of the source/drain regions allows a lower temperature anneal to be performed, and the use of nickel silicide permits a single anneal to be used to both activate the dopants and form the nickel silicide contacts.

Abstract: A semiconductor device which includes a silicon substrate, an oxide layer formed on the silicon substrate, a polysilicon layer formed on the oxide layer, a first metal silicide layer formed on the polysilicon layer, and a second metal silicide layer formed on the first metal silicide layer, and a method for fabricating the same. The first metal silicide layer is preferably comprised of a metal silicide, such as molybdenum, tungsten, or tantalum silicide, having a melting point which is higher than that of the second metal silicide layer. The second metal silicide layer is preferably comprised of titanium silicide. In an embodiment, the method comprises forming the polysilicon layer on the oxide layer, depositing a tantalum layer on the polysilicon layer, rapidly annealing the resulting structure.

Abstract: An aspect of the present invention provides a method of manufacturing a semiconductor device, including, forming an insulating film on a silicide layer formed at the surface of a silicon semiconductor substrate, etching the insulating film to form a contact hole in which the silicide layer is exposed, forming a metal nitride film on the bottom and side wall of the contact hole, carrying out a first heating process at 600° C. or lower on the substrate, carrying out, during the first heating process, a second heating process for 10 msec or shorter with light whose main wavelength is shorter than a light absorbing end of silicon, forming a contact conductor in the contact hole after the second heating process, and forming, on the insulating film, wiring that is electrically connected to the substrate through the contact conductor.

Abstract: A method of manufacturing a semiconductor device comprises steps of: forming a first metal film having a reducing property on a semiconductor substrate; thermal treating the resulting semiconductor substrate for reducing a native oxide film naturally formed on the semiconductor substrate and for forming a first silicide film on the semiconductor substrate; removing an unreacted first metal film selectively; forming a second metal film on the semiconductor substrate; and thermal treating the resulting semiconductor substrate for forming a second silicide film on a surface of the semiconductor substrate which includes a region where the first silicide film is formed.

Abstract: A cobalt layer is formed over an entire surface including over a device isolation region. Silicon ions are selectively implanted into only the cobalt layer on the device isolation region and thereafter a silicidation reaction is done, whereby local interconnects are formed between source and drain regions of adjacent MOS transistors.