Abstract: One illustrative method disclosed herein involves forming a contact opening in a layer of insulating material, forming a layer of conductive material above the layer of insulating material that overfills the contact opening, performing at least one chemical mechanical polishing process to remove portions of the conductive material positioned outside of the contact opening and thereby define a conductive contact positioned in the contact opening and, after performing the chemical mechanical polishing process, performing a selective metal deposition process to selectively form additional metal material on an upper surface of the conductive contact.

Abstract: A method of manufacturing a semiconductor device according to an embodiment, includes forming a wiring in a surface of a first insulating film on a semiconductor substrate, exposing the first insulating film in whose surface the wiring is formed to a plasma containing a rare gas so as to form a densified layer on the surface of the first insulating film, removing an oxide film formed on the wiring, after the densified layer is formed and forming a second insulating film on the wiring from which the oxide film is removed and on the densified layer, wherein the processes from the removal of the oxide film to the formation of the second insulating film are carried out without being atmospherically-exposed.

Abstract: A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate.

Abstract: A semiconductor device and method are disclosed. The semiconductor device includes a substrate having a first region and a second region and an insulating layer arranged on the substrate. A first conductive layer is arranged in or on insulating layer in the first region and a second conductive layer is arranged in or on the insulating layer in the second region. The first conductive layer comprises a first conductive material and the second conductive layer comprises a second conductive material wherein the first conductive material is different than the second conductive material. A metal layer is arranged on the first conductive layer.

Abstract: A method for fabricating an integrated circuit includes the steps of: providing a substrate having a semiconductor surface; providing a hardmask material on the semiconductor surface. For at least one masking level of the integrated circuit: providing a mask pattern for the masking level partitioned into a first mask and at least one second mask, the first mask providing features in a first grid pattern and the at least one second mask providing features in a second grid pattern, wherein the first and the second grid pattern have respective features which interleave with one another over at least one area; applying a first photoresist layer with the first mask; exposing the first grid pattern using the first mask; developing the first photoresist layer; etching the hardmask material to transfer the first grid pattern in the surface of the substrate; removing the first photoresist layer.

Abstract: A method of making templated circuitry employs a template system that includes a template of an insulator material on a carrier having a conductive surface. The template includes multiple levels and multiple regions, wherein a first level exposes the conductive surface of the carrier. A first metal is electrochemically deposited on the conductive surface in first regions of the first level. A circuit material is deposited to cover the first metal. The template is etched until a second level of the template exposes the conductive surface in second regions on opposite sides of the first regions. A second metal is electrochemically deposited on the conductive surface in the second regions. The template of deposited materials is transferred from the carrier to a substrate.

Abstract: A step of forming wiring using first solution ejection means for ejecting a conductive material, a step of forming a resist mask on the wiring using second solution ejection means, and a step of etching the wiring using an atmospheric-pressure plasma device having linear plasma generation means or an atmospheric-pressure plasma device having a plurality of linearly-arranged plasma-generation-means using the resist mask as a mask are included.

Abstract: A structure for wireless communication having a plurality of conductor layers, an insulator layer separating each of the conductor layers, and at least one connector connecting two of the conductor layers wherein an electrical resistance is reduced when an electrical signal is induced in the resonator at a predetermined frequency.

Abstract: Methods of metal assisted chemical etching III-V semiconductors are provided. The methods can include providing an electrically conductive film pattern disposed on a semiconductor substrate comprising a III-V semiconductor. At least a portion of the III-V semiconductor immediately below the conductive film pattern may be selectively removed by immersing the electrically conductive film pattern and the semiconductor substrate into an etchant solution comprising an acid and an oxidizing agent having an oxidation potential less than an oxidation potential of hydrogen peroxide. Such methods can form high aspect ratio semiconductor nanostructures.

Abstract: A process to form a via hole in a semiconductor wafer is disclosed. The process includes steps of, preparing a metal mask and etching the wafer by the metal mask as the etching mask. The preparation of the metal mask includes steps of: coating a nega-resist on the back surface of the wafer, carrying out the photolithography for the coated nega-resist, plating a metal selectively by the patterned photoresist, and removing the patterned photoresist.

Abstract: Described are manganese-containing films, as well as methods for providing the manganese-containing films. Doping manganese-containing films with Co, Mn, Ru, Ta, Al, Mg, Cr, Nb, Ti or V allows for enhanced copper barrier properties of the manganese-containing films. Also described are methods of providing films with a first layer comprising manganese silicate and a second layer comprising a manganese-containing film.

Abstract: A method of manufacturing a semiconductor device comprises forming a contact hole within an interlayer insulating film of a substrate and forming a contact plug while the substrate is heated. In forming the contact plug, the substrate is held on a stage within the chamber of a sputtering apparatus through a chuck, and an ESC voltage applied to the chuck is increased stepwise in a plurality of steps. First target power is applied to a target within the chamber to form a first Al film in the contact hole. Next, second target power higher than the first target power is applied to the target within the chamber to form a second Al film on the first Al film.

Abstract: A chip package includes a substrate having an upper surface and a lower surface, a plurality of conducting pads located under the lower surface of the substrate, and a dielectric layer located between the conducting pads. A hole is provided in the substrate, which extends from the upper surface towards the lower surface of the substrate. A sidewall or a bottom of the hole exposes a portion of the conducting pads. The upper opening of the hole near the upper surface is smaller than a lower opening of the hole near the lower surface. An upper conducting pad has at least an opening or a trench exposing a lower conducting pad of the conducting pads. A conducting layer is disposed in the hole, which electrically contacting at least one of the conducting pads.

Abstract: The invention relates to a method for masking a semiconductor substrate including the following steps: providing a planar semiconductor substrate having a first side and a second side lying opposite thereto, applying a mask to at least one of the sides, an extrusion printing method being used for applying the mask.

Abstract: Electrode arrays and methods of fabricating the same using a printing plate to arrange conductive particles in alignment with an array of electrodes are provided. In one embodiment, a semiconductor device comprises: a semiconductor topography comprising an array of electrodes disposed upon a semiconductor substrate; a dielectric layer residing upon the semiconductor topography; and at least one conductive particle disposed in or on the dielectric layer in alignment with at least one of the array of electrodes.

Abstract: A method for fabricating a semiconductor device includes etching a substrate to form a plurality of bodies isolated by a first trench, forming a buried bit line gap-filling a portion of the first trench, etching the top portions of the bodies to form a plurality of pillars isolated by a plurality of second trenches extending across the first trench, forming a passivation layer gap-filling a portion of the second trenches, forming an isolation layer that divides each of the second trenches into isolation trenches over the passivation layer, and filling a portion of the isolation trenches to form a buried word line extending in a direction crossing over the buried bit line.

Abstract: Provided are semiconductor devices and methods for fabricating the same. A method for fabricating a semiconductor device includes: forming an interlayer dielectric layer including an opening in which a lower conductive layer is exposed; forming a barrier layer on the interlayer dielectric layer and on the lower conductive layer the opening; forming an anti-seed generation region on a surface of the barrier layer which is provided on a top surface of the interlayer dielectric layer and an upper sidewall of the opening; and filling the opening with conductive material to form a conductive layer.

Abstract: Vertical devices and methods of forming the same are provided. One example method of forming a vertical device can include forming a trench in a semiconductor structure, and partially filling the trench with an insulator material. A dielectric material is formed over the insulator material. The dielectric material is modified into a modified dielectric material having an etch rate greater than an etch rate of the insulator material. The modified dielectric material is removed from the trench via a wet etch.

Abstract: A three-dimensional integrated circuit (3D-IC) which incorporates a glass interposer and a method for fabricating the three-dimensional integrated circuit (3D-IC) with the glass interposer are described herein. In one embodiment, the 3D-IC incorporates a glass interposer which has vias formed therein which are not filled with a conductor that allow for precision metal-to-metal interconnects (for example) between redistribution layers. In another embodiment, the 3D-IC incorporates a glass interposer which has vias and has a coefficient of thermal expansion (CTE) that is different than the CTE of silicon which is 3.2 ppm/° C.

Abstract: A method of manufacturing a semiconductor device includes forming an insulating film on a surface of a semiconductor layer, forming a resist on a surface of the insulating film, the resist having an opening, forming a hardened layer on an inner circumference of the resist by attaching a pattern shrinking agent to the resist, the pattern shrinking agent undergoing a cross-linking reaction with the resist, etching the insulating film using the resist and the hardened layer as masks, removing the hardened layer, and forming a metal layer on a surface of the semiconductor layer, on a surface of the insulating film, and on a surface of the resist. The method further includes removing the resist and the portion of the metal layer on the surface of the resist by lift-off.

Abstract: A template for feeding a processing solution to predetermined positions of a substrate has multiple opening portions formed in positions on a front surface corresponding to the predetermined positions, flow channels penetrating from the opening portions to a back surface in a thickness direction for flowing a processing solution, first hydrophilic regions set to be hydrophilic around the opening portions on the front surface, and second hydrophilic regions set to be hydrophilic on inner surfaces of flow channels. The first hydrophilic regions are formed in positions corresponding to hydrophilic patterns set to be hydrophilic around the predetermined positions on a substrate surface.

Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a seed layer over a dielectric layer and a patterned resist layer over the seed layer. Next, metal lines are formed on regions of the seed layer not covered by the patterned resist layer. The patterned resist layer is removed using a plasma process, which involves using an oxidizing species and a reducing species in the plasma. The reducing species substantially prevents the oxidation of the metal lines and the seed layer during the plasma process.

Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).

Abstract: Disclosed herein are a variety of microfluidic devices and solid, typically electrically conductive devices that can be formed using such devices as molds. In certain embodiments, the devices that are formed comprise conductive pathways formed by solidifying a liquid metal present in one or more microfluidic channels (such devices hereinafter referred to as “microsolidic” devices). In certain such devices, in which electrical connections can be formed and/or reformed between regions in a microfluidic structure; in some cases, the devices/circuits formed may be flexible and/or involve flexible electrical components. In certain embodiments, the solid metal wires/conductive pathways formed in microfluidic channel(s) may remain contained within the microfluidic structure. In certain such embodiments, the conductive pathways formed may be located in proximity to other microfluidic channel(s) of the structure that carry flowing fluid, such that the conductive pathway can create energy (e.g.

Abstract: Array of nanoholes and method for making the same. The array of nanoholes includes a plurality of nanoholes. Each of the plurality of nanoholes corresponds to a first end and a second end, and the first end and the second end are separated by a first distance of at least 100 ?m. Each of the plurality of nanoholes corresponds to a cross-sectional area associated with a distance across, and the distance across ranges from 5 nm to 500 nm. Each of the plurality of nanoholes is separated from at least another nanohole selected from the plurality of nanoholes by a semiconductor material associated with a sidewall thickness, and the sidewall thickness ranges from 5 nm to 500 nm.

Abstract: Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines.

Abstract: A method for opening a one-side contact region of a vertical transistor is provided. The one-side contact region of the vertical transistor is opened using a polysilicon layer, a certain portion of which can be selectively removed by a selective ion implantation process. In order to selectively remove the polysilicon layer formed on one of both sides of an active region, at which the one-side contact is to be formed, impurity ion implantation is performed in a direction vertical to the polysilicon layer by a plasma doping process, and a tilt ion implantation using an existing ion implantation process is performed. In this manner, the polysilicon layer is selectively doped, and the undoped portion of the polysilicon layer is selectively removed.

Abstract: According to one embodiment, a pattern formation method includes, before forming a circuit pattern on a substrate using imprinting, a wall pattern with a predetermined height is formed to surround the periphery of an area serving as imprint shots on the substrate in each imprint shot and to allow the imprint shots to be separated from one another. The circuit pattern is formed in the imprint shots surrounded by the wall pattern through imprinting.

Abstract: A method for tone inversion for integrated circuit fabrication includes providing a substrate with an underlayer on top of the substrate; creating a first pattern, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; covering the first pattern with a layer of image reverse material (IRM); and etching the second pattern into the substrate.

Abstract: The present invention relates to a method for forming metal-silicide catalyst nanoparticles with controllable diameter. The method according to embodiments of the invention leads to the formation of ‘active’ metal-suicide catalyst nanoparticles, with which is meant that they are suitable to be used as a catalyst in carbon nanotube growth. The nano-particles are formed on the surface of a substrate or in case the substrate is a porous substrate within the surface of the inner pores of a substrate. The metal-silicide nanoparticles can be Co-silicide, Ni-silicide or Fe-silicide particles. The present invention relates also to a method to form carbon nanotubes (CNT) on metal-silicide nanoparticles, the metal-silicide containing particles hereby acting as catalyst during the growth process, e.g. during the chemical vapor deposition (CVD) process. Starting from very defined metal-containing nanoparticles as catalysts, the diameter of grown CNT can be well controlled and a homogeneous set of CNT will be obtained.

Abstract: A method of depositing a metal film on a substrate with patterned features includes placing a substrate with patterned features into a photo-induced chemical vapor deposition (PI-CVD) process chamber. The method also includes depositing a metal film by PI-CVD to fill the patterned features from bottom up.

Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

Abstract: A structure is provided with a self-aligned resist layer on a surface of metal interconnects for use in forming air gaps in an insulator material and method of fabricating the same. The non-lithographic method includes applying a resist on a structure comprising at least one metal interconnect formed in an insulator material. The method further includes blanket-exposing the resist to energy and developing the resist to expose surfaces of the insulator material while protecting the metal interconnects. The method further includes forming air gaps in the insulator material by an etching process, while the metal interconnects remain protected by the resist.

Abstract: The method for making a hole in a layer includes the provision of first and second adhesion areas on a surface of a support. The first area has dimensions corresponding to the dimensions of the hole. The method includes depositing a layer on the first and second adhesion areas. The material of the layer has an adhesion coefficient to the first area lower than the adhesion coefficient to the second area. The part of layer arranged above the first area is eliminated by a fluid jet.

Abstract: Memory cells in integrated circuit devices may be formed on the basis of functional molecules which may be positioned within via openings on the basis of appropriate patterning techniques, which may also be used for forming semiconductor-based integrated circuits. Consequently, memory cells may be formed on a “molecular” level without requiring extremely sophisticated patterning regimes, such as electron beam lithography and the like.

Abstract: A method for fabricating a semiconductor device includes forming an etch target layer including an insulation layer and a metal layer over a substrate, forming a hard mask layer pattern over the etch target layer, forming a protective layer pattern which includes a region having a shape of an overhang formed in an upper portion of the hard mask layer pattern, etching the insulation layer of the etch target layer by using the first region as an etch barrier, and etching the metal layer of the etch target layer by using the second region as an etch barrier.

Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. A metal oxide second electrode layer is formed above the dielectric layer. The metal oxide second electrode layer has a crystal structure that is compatible with the crystal structure of the dielectric layer. Optionally, a second electrode bulk layer is formed above the metal oxide second electrode layer.

Abstract: A method for forming three-dimensional multilayer circuit includes forming an area distributed CMOS layer configured to selectively address a set of first vias and a set of second vias. A template is then aligned with the first set of vias and lower crossbar segments are created using the template. The template is then removed, rotated, and aligned with the set of second vias. Upper crossbar segments which attach to the second set of vias are then created.

Abstract: A high-throughput, low cost, patterning platform is provided that is an alternative to conventional photolithography and direct laser ablation patterning techniques. The processing methods are useful for making patterns of microsized and/or nanosized structures having accurately selected physical dimensions and spatial orientation that comprise active and passive components of a range of microelectronic devices. Processing provided by the methods is compatible with large area substrates, such as device substrates for semiconductor integrated circuits, displays, and microelectronic device arrays and systems, and is useful for fabrication applications requiring patterning of layered materials, such as patterning thin film layers in thin film electronic devices.

Abstract: A passivation film is formed on a compound semiconductor layered structure, an electrode formation scheduled position for the passivation film is thinned by dry etching, a thinned portion of the passivation film is penetrated by wet etching to form an opening, and a gate electrode is formed on the passivation film so as to embed this opening by an electrode material.

Abstract: An electric functional layer is produced on a surface of a substrate, having at least an electronic component, particularly a semiconductor chip, provided thereof. The electric functional layer is formed using particles in powder of an electrically conductive material. The functional layer is blown on the surface of the substrate to form a thick and strong adhesive layer on impact with the substrate.

Abstract: There is provided a method of manufacturing a semiconductor device including: preparing a semiconductor substrate, forming a first insulating layer, a first redistribution layer, a second insulating layer, a second redistribution layer, and at least one of first processing, in which, after the first electrically conductive material is filled in the first opening to form a first via interconnect, the first redistribution layer is formed on the first insulating layer with the first electrically conductive material such that the first redistribution layer is electrically connected to the first via interconnect; or second processing, in which, after the second electrically conductive material is filled in the second opening to form a second via interconnect, the second redistribution layer is formed on the second insulating layer with the second electrically conductive material such that the second redistribution layer is electrically connected to the second via interconnect.

Abstract: In a substrate wiring method, copper is embedded all the way to the lowest parts of a wiring pattern formed on a substrate. The method is used to wire a substrate in a processing chamber kept in a vacuum state, the substrate having a wiring pattern formed thereon. The method includes a preprocessing step in which the wiring pattern on the substrate is cleaned using a desired cleaning gas and an embedding step in which, after the preprocessing step, metal nanoparticles are embedded in the wiring pattern using a clustered metal gas.

Abstract: A printing plate and method for fabricating the same is disclosed. A metal layer is first formed on a glass substrate. The metal layer is then patterned in a predetermined shape. The glass substrate is next etched to a predetermined depth using the patterned metal layer as a mask and the metal layer removed. If necessary, additional metal layers have the same or different patterns may be formed on the glass substrate and the glass substrate etched after each metal layer is formed thereon until a desired etching depth in the glass is achieved.

Abstract: A method for manufacturing semiconductor device includes forming an interlayer dielectric layer including a contact plug defined therein to electrically couple a semiconductor substrate on which a cell region and a dummy region are defined. A sacrificial layer is formed over the interlayer dielectric layer. An etch stop pattern is formed over the sacrificial layer, the etch stop pattern being vertically aligned to the dummy region. A storage electrode region through the sacrificial layer is defined to expose a first storage electrode contact of the cell region, the second storage electrode contact of the dummy region remaining covered by the sacrificial layer. A conductive layer is deposited within the storage electrode region to form a storage electrode contacting the first storage electrode contact of the cell region.

Abstract: A system and method for forming photoresists over semiconductor substrates is provided. An embodiment comprises a photoresist with a concentration gradient. The concentration gradient may be formed by using a series of dry film photoresists, wherein each separate dry film photoresist has a different concentration. The separate dry film photoresists may be formed separately and then placed onto the semiconductor substrate before being patterned. Once patterned, openings through the photoresist may have a tapered sidewall, allowing for a better coverage of the seed layer and a more uniform process to form conductive materials through the photoresist.

Abstract: A method of forming a semiconductor device includes the following processes. A dummy insulating film is formed over a semiconductor substrate by using a source material that is free of carbon as an essential component. A hole that penetrates the dummy insulating film is formed. A conductive film is formed, which covers at least a side wall of the hole of the dummy insulating film. The dummy insulating film is removed to expose an outer surface of the conductive film.

Abstract: There are provided an evaporation mask with which an evaporated film is allowed to be formed with a fine pattern, a method of manufacturing the same, and a method of manufacturing an electronic device using such an evaporation mask. Further, there is provided an electronic device having a film-formation pattern that is precisely formed with a fine pattern. The evaporation mask including: a substrate including one or a plurality of first opening sections; and a polymer film provided on a first main surface side of the substrate, the polymer film including one or a plurality of second opening sections communicated with the respective first opening sections.

Abstract: In one implementation, an apparatus includes a semiconductor die, a lead, a non-conductive epoxy, and a conductive epoxy. The semiconductor die includes an upper surface and a lower surface opposite the upper surface. The lead is electrically coupled to the upper surface of the semiconductor die. The non-conductive epoxy is disposed on a first portion of the lower surface of the semiconductor die. The conductive epoxy is disposed on a second portion of the lower surface of the semiconductor die. In some implementations, a conductive wire extends from the lead to the upper surface of the semiconductor die to electrically couple the lead to the upper surface of the semiconductor die.

Abstract: Embodiments of the invention are directed to a method of printing lines. The method may include depositing material on a substrate from a plurality of nozzles to form a multi-layered line of a desired cross section area or a desired height by dispensing the material in at least two layers in a single scan. Each layer may be printed by different nozzles and the number of layers in the line is determined based on the desired cross section area or height.