Combined Mechanical And Chemical Material Removal Patents (Class 438/691)
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Patent number: 8129277Abstract: A method of machining a wafer in which, at the time of grinding the back-side surface of the wafer, only a back-side surface region corresponding to a device formation region where semiconductor chips are formed is thinned by grinding, to form a recessed part on the back side of the wafer. An annular projected part surrounding the recessed part is utilized to secure rigidity of the wafer. Next, the recessed part is etched to cause metallic electrodes to project from the bottom surface of the recessed part, thereby forming a back-side electrode parts, then an insulating film is formed in the recessed part, and the insulating film and end surfaces of the back-side electrode parts are cut.Type: GrantFiled: June 18, 2008Date of Patent: March 6, 2012Assignee: Disco CorporationInventors: Yusuke Kimura, Kuniaki Tsurushima
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Patent number: 8124526Abstract: In methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device, a preliminary ferroelectric layer is formed on a substrate by depositing a metal oxide including lead, zirconium and titanium. The surface of the preliminary ferroelectric layer is polished using a slurry composition including an acrylic acid polymer, abrasive particles, and water to form a thin ferroelectric layer on the substrate. The slurry composition may reduce a polishing rate of the preliminary ferroelectric layer such that removal of a bulk portion of the preliminary ferroelectric layer may be suppressed and the surface roughness of the preliminary ferroelectric layer may be improved.Type: GrantFiled: July 15, 2009Date of Patent: February 28, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Suk-Hun Choi, Jong-Won Lee, Chang-Ki Hong, Bo-Un Yoon
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Patent number: 8114774Abstract: The invention relates to a method of manufacturing a semiconductor device with a substrate and a semiconductor body, whereby in the semiconductor body a semiconductor element is formed by means of a mesa-shaped protrusion of the semiconductor body, which is formed on the surface of the semiconductor device as a nano wire, whereupon a layer of a material is deposited over the semiconductor body and the resulting structure is subsequently planarized in a chemical-mechanical polishing process such that an upper side of the nano wire becomes exposed. According to the invention, a further layer of a further material is deposited over the semiconductor body with the nano wire before the layer of the material is deposited, which further layer is given a thickness smaller than the height of the nano wire, and a material is chosen for the further material such that, viewed in projection, the transition between the layer and the further layer is discernible before the nano wire is reached.Type: GrantFiled: June 6, 2007Date of Patent: February 14, 2012Assignee: NXP B.V.Inventors: Godefridus Adrianus Maria Hurkx, Johannes Josephus Theodorus Marinus Donkers
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Publication number: 20120028439Abstract: A method for manufacturing a silicon-on-insulator structure including a substrate wafer, an active wafer, and an oxide layer between the substrate wafer and the active wafer. The method includes the steps of heat treating the structure, trapezoid grinding edges of the wafer, and grinding a surface of the wafer.Type: ApplicationFiled: July 30, 2010Publication date: February 2, 2012Applicant: MEMC ELECTRONIC MATERIALS, INC.Inventors: Guoqiang David Zhang, Roland R. Vandamme
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Patent number: 8105894Abstract: A formation method of an element isolation film according to which a high-voltage transistor with an excellent characteristic can be formed is provided. On a substrate, a gate oxide film is previously formed. A CMP stopper film is formed thereon, and thereafter, a gate oxide film and a CMP stopper film are etched. The semiconductor substrate is etched to form a trench. Further, before the trench is filled with a field insulating film, an liner insulating film is formed at a trench interior wall, and a concave portion at the side surface of the gate oxide film under the CMP stopper film is filled with the liner insulating film. In this manner, formation of void in the element isolation film laterally positioned with respect to the gate oxide film can be prevented.Type: GrantFiled: August 12, 2010Date of Patent: January 31, 2012Assignee: Sharp Kabushiki KaishaInventors: Masayuki Tajiri, Takayoshi Hashimoto, Hisashi Yonemoto, Toyohiro Harazono
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Patent number: 8105948Abstract: A process is described for making contact to the buried capping layers of GMR and MTJ devices without the need to form and fill via holes. CMP is applied to the structure in three steps: (1) conventional CMP (2) a Highly Selective Slurry (HSS) is substituted for the conventional slurry to just expose the capping layer, and (3) the HSS is diluted and used to clean the surface as well as to cause a slight protrusion of the capping layers above the surrounding dielectric surface, making it easier the contact them without damaging the devices below.Type: GrantFiled: February 14, 2008Date of Patent: January 31, 2012Assignee: MagIC Technologies, Inc.Inventors: Adam Zhong, Wai-Ming Kan, Tom Zhong, Chyu-Jiuh Torng
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Patent number: 8101523Abstract: A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 diamond granules and 0 wt %-40 wt % oxide granules, grinding and polishing a top surface of the wafer, etching the top surface for eliminating a top process-induced degradation layer and maintaining a 0.5 ?m-10 ?m thick edge process-induced degradation layer.Type: GrantFiled: November 5, 2010Date of Patent: January 24, 2012Assignee: Sumitomo Electric Industries, Ltd.Inventors: Keiji Ishibashi, Hidenori Mikami, Naoki Matsumoto
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Publication number: 20120009787Abstract: A method for forming a masking layer of a semiconductor device includes forming a plurality of pillar structures separated by a trench, forming a gap-fill material partially filling the trench and exposing an upper sidewall of each pillar structure, forming a masking layer that covers the pillar structures and the gap-fill material, performing an ion implantation to the masking layer to form an implanted portion covering upper portion of the gap-fill material and one side of the upper sidewalls of each pillar structure and a non-implanted portion covering the other side of the upper sidewalls of each pillar structure, forming a sacrificial layer over the masking layer, exposing the non-implanted portion of the masking layer, and selectively removing the exposed non-implanted portion.Type: ApplicationFiled: November 17, 2010Publication date: January 12, 2012Inventor: Won-Kyu KIM
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Patent number: 8092707Abstract: The disclosure pertains to compositions and methods for modifying or refining the surface of a wafer suited for semiconductor fabrication. The compositions include working liquids useful in modifying a surface of a wafer suited for fabrication of a semiconductor device. In some embodiments, the working liquids are aqueous solutions of initial components substantially free of loose abrasive particles, the components including water, a surfactant, and a pH buffer exhibiting at least one pKa greater than 7. In certain embodiments, the pH buffer includes a basic pH adjusting agent and an acidic complexing agent, and the working liquid exhibits a pH from about 7 to about 12. In further embodiments, the disclosure provides a fixed abrasive article comprising a surfactant suitable for modifying the surface of a wafer, and a method of making the fixed abrasive article. Additional embodiments describe methods that may be used to modify a wafer surface.Type: GrantFiled: August 15, 2007Date of Patent: January 10, 2012Assignee: 3M Innovative Properties CompanyInventors: L. Charles Hardy, Heather K. Kranz, Thomas E. Wood, David A. Kaisaki, John J. Gagliardi, John C. Clark, Patricia M. Savu, Philip G. Clark
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Patent number: 8088690Abstract: The instant invention is a method of polishing a substrate including contacting a substrate having at least one metal layer including copper with a chemical-mechanical polishing composition. The CMP composition includes an abrasive, a surfactant, an oxidizer, an organic acid including polyacrylic acid or polymethacrylic acid, a corrosion inhibitor, and a liquid carrier. A portion of the copper in the metal layer is abraded to polish the substrate. A second CMP composition contacts the abraded substrate, the second acrylate free composition including an abrasive, a surfactant, an oxidizer, and a corrosion inhibitor, and a liquid carrier. Any dendrites that may have formed on the substrate are removed through abrasion.Type: GrantFiled: March 31, 2009Date of Patent: January 3, 2012Assignee: International Business Machines CorporationInventors: Thomas L. McDevitt, Graham M. Bates, Eva A. Shah, Matthew T. Tiersch, Eric J. White
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Patent number: 8083964Abstract: A metal-polishing liquid used for chemical-mechanical polishing of a conductor film of copper or a copper alloy in a process for manufacturing a semiconductor device, the metal-polishing liquid comprising: (1) an amino acid derivative represented by the formula (I); and (2) a surfactant, wherein, in the formula (I), R1 represents an alkyl group having 1 to 4 carbon atoms and R2 represents an alkylene group having 1 to 4 carbon atoms.Type: GrantFiled: March 26, 2008Date of Patent: December 27, 2011Assignee: Fujifilm CorporationInventors: Toru Yamada, Makoto Kikuchi, Tadashi Inaba, Takahiro Matsuno, Takamitsu Tomiga, Kazutaka Takahashi
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Publication number: 20110309470Abstract: High Efficiency Diode (HED) rectifiers with improved performance including reduced reverse leakage current, reliable solderability properties, and higher manufacturing yields are fabricated by minimizing topography variation at various stages of fabrication. Variations in the topography are minimized by using a CMP process to planarize the HED rectifier after the field oxide, polysilicon and/or solderable top metal are formed.Type: ApplicationFiled: June 18, 2010Publication date: December 22, 2011Inventor: Thomas E. Grebs
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Patent number: 8080475Abstract: Embodiments of the present invention describe a removal chemistry for removing hard mask. The removal chemistry is a wet-etch solution that removes a metal hard mask formed on a dielectric layer, and is highly selective to a metal conductor layer underneath the dielectric layer. The removal chemistry comprises an aqueous solution of hydrogen peroxide (H2O2), a hydroxide source, and a corrosion inhibitor. The hydrogen peroxide and hydroxide source have the capability to remove the hard mask while the corrosion inhibitor prevents the metal conductor layer from chemically reacting with the hydrogen peroxide and hydroxide source during the hard mask removal.Type: GrantFiled: January 23, 2009Date of Patent: December 20, 2011Assignee: Intel CorporationInventors: Vijayakumar SubramanyaRao RamachandraRao, Kanwal Jit Singh
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Patent number: 8080476Abstract: To provide a polishing composition particularly useful for an application to polish a conductor layer made of copper in a semiconductor wiring process, and a polishing process employing it. A polishing composition comprising an anionic surfactant and a nonionic surfactant, characterized in that the composition is prepared so that the water contact angle of the surface of an object to be polished, after being polished by the composition, would be at most 60°.Type: GrantFiled: August 1, 2007Date of Patent: December 20, 2011Assignee: Fujimi IncorporatedInventors: Atsunori Kawamura, Masayuki Hattori
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Publication number: 20110306209Abstract: A group III nitride substrate in one embodiment has a surface layer. The surface layer contains 3 at. % to 25 at. % of carbon and 5×1010 atoms/cm2 to 200×1010 atoms/cm2 of a p-type metal element. The group III nitride substrate has a stable surface.Type: ApplicationFiled: August 18, 2011Publication date: December 15, 2011Inventor: Keiji ISHIBASHI
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Patent number: 8076246Abstract: A method comprises a first multilayer body forming step of forming a first multilayer body on a first cladding layer, the first multilayer body including a core layer and a first polishing stop layer in order from the first cladding layer side; a first multilayer body patterning step of pattering the first multilayer body, so as to expose the first cladding layer about the patterned first multilayer body; a second multilayer body forming step of forming a second multilayer body on the exposed first cladding layer and patterned first multilayer body, the second multilayer body including a second cladding layer and a second polishing stop layer in order from the first cladding layer side; and a removing step of polishing away a part of the second multilayer body formed on the first multilayer body.Type: GrantFiled: January 26, 2009Date of Patent: December 13, 2011Assignee: TDK CorporationInventors: Kosuke Tanaka, Koji Shimazawa
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Publication number: 20110300709Abstract: The present invention relates to a method of semiconductor wafer back processing, which includes applying a radiation-curable pressure-sensitive adhesive sheet comprising a base film and a pressure-sensitive adhesive layer disposed on one side of the base film to a front side of a semiconductor wafer, the front side of the semiconductor wafer having recesses and protrusions; grinding the back side of the semiconductor wafer in such a state that the radiation-curable pressure-sensitive adhesive sheet is adherent to the front side of the semiconductor; and irradiating the pressure-sensitive adhesive sheet with a radiation to thereby cure the pressure-sensitive adhesive layer, followed by subjecting said ground back side of the semiconductor wafer to a surface treatment; and a radiation-curable pressure-sensitive adhesive sheet for use in the method of semiconductor wafer back processing.Type: ApplicationFiled: August 12, 2011Publication date: December 8, 2011Applicant: NITTO DENKO CORPORATIONInventor: Toshio Shintani
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Patent number: 8071482Abstract: A manufacturing method for a silicon carbide semiconductor device is disclosed. It includes an etching method in which an Al film and Ni film are laid on an SiC wafer in this order and wet-etched, whereby a two-layer etching mask is formed in which Ni film portions overhang Al film portions. Mesa grooves are formed by dry etching by using this etching mask.Type: GrantFiled: May 20, 2008Date of Patent: December 6, 2011Assignee: Fuji Electric Co., Ltd.Inventor: Yasuyuki Kawada
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Patent number: 8071479Abstract: A method for chemical mechanical polishing of a substrate comprising a barrier material in the presence of at least one of an interconnect metal and a low-k dielectric material using a chemical mechanical polishing composition comprising water; 1 to 40 wt % abrasive having an average particle size of ?100 nm; 0.001 to 5 wt % quaternary compound; a material having a formula (I): wherein R is selected from C2-C20 alkyl, C2-C20 aryl, C2-C20 aralkyl and C2-C20 alkaryl; wherein x is an integer from 0 to 20; wherein y is an integer from 0 to 20; wherein x+y?1; and, wherein the chemical mechanical polishing composition has a pH?5.Type: GrantFiled: December 11, 2008Date of Patent: December 6, 2011Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.Inventor: Zhendong Liu
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Patent number: 8070843Abstract: Provided are several polishing compositions useful for modifying a surface, such as a semiconductor wafer suitable for fabrication of a semiconductor device, especially when used in fixed abrasive planarization techniques. The polishing compositions include a synergistic mixture of water, an oxidizing agent, a complexing agent, and metal ions. Also provided are various methods of surface planarization.Type: GrantFiled: September 3, 2008Date of Patent: December 6, 2011Assignee: 3M Innovative Properties CompanyInventor: Jeffrey S. Kollodge
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Patent number: 8058172Abstract: A polishing composition containing at least one or more aminocarboxylic acids selected from the group consisting of serine, cysteine and dihydroxyethylglycine, ceria particles and an aqueous medium; a polishing process of a semiconductor substrate, including the step of polishing a semiconductor substrate with a polishing composition for a semiconductor substrate, containing at least one or more aminocarboxylic acids selected from the group consisting of serine, cysteine and dihydroxyethylglycine, ceria particles and an aqueous medium; a method for manufacturing a semiconductor device including the step of polishing a semiconductor substrate having a film formed on its surface, the film containing a silicon atom and having a shape with dents and projections, with a polishing pad pressed against a semiconductor substrate at a polishing load of from 5 to 100 kPa in the presence of a polishing composition for a semiconductor substrate, containing at least one or more aminocarboxylic acids selected from the groupType: GrantFiled: March 18, 2009Date of Patent: November 15, 2011Assignee: Kao CorporationInventors: Yasuhiro Yoneda, Mami Shirota
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Patent number: 8058173Abstract: Methods for reducing the surface roughness of semiconductor wafers through a combination of rough polishing and thermally annealing the wafer.Type: GrantFiled: December 19, 2007Date of Patent: November 15, 2011Assignee: MEMC Electronic Materials, Inc.Inventors: Larry W. Shive, Brian L. Gilmore
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Patent number: 8048808Abstract: A slurry composition for polishing metal includes a polymeric polishing accelerating agent, the polymeric polishing accelerating agent including a backbone of hydrocarbon and a side substituent having at least one of a sulfonate ion (SO3?) and a sulfate ion (OSO3?), and an acidic aqueous solution.Type: GrantFiled: June 26, 2008Date of Patent: November 1, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Won Lee, Sang-Yeob Han, Chang-Ki Hong, Bo-Un Yoon, Jae-Dong Lee
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Patent number: 8048726Abstract: In sophisticated SOI devices, circuit elements, such as substrate diodes, may be formed in the crystalline substrate material on the basis of a substrate window, wherein the pronounced surface topography may be compensated for or at least reduced by performing additional planarization processes, such as the deposition of a planarization material, and a subsequent etch process when forming the contact level of the semiconductor device.Type: GrantFiled: October 28, 2010Date of Patent: November 1, 2011Assignee: GLOBALFOUNDRIES Inc.Inventors: Jens Heinrich, Kai Frohberg, Sven Mueller, Kerstin Ruttloff
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Patent number: 8048807Abstract: Provided is a method for fabricating a semiconductor device that includes providing a semiconductor substrate having a front side and a backside, where active or passive devices are formed in the front side, rotating the semiconductor substrate, and etching the backside of the semiconductor substrate by introducing a first etchant while the substrate is rotated, the first etchant including an R—COOH.Type: GrantFiled: September 5, 2008Date of Patent: November 1, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming Chyi Liu, Yao Fei Chuang, Martin Liu, Gwo-Yuh Shiau, Chia-Shiung Tsai
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Publication number: 20110263126Abstract: Method for manufacturing a silicon wafer free of point defect agglomerates by processes including adding pure carbon to raw material of polycrystalline silicon, melting to become a molten silicon liquid, pulling a single silicon crystal ingot comprising a perfect domain [P] from the molten silicon liquid by controlling a ratio of V/G (mm2/minute ° C.), lapping a silicon wafer cut out from the ingot, beveling the silicon wafer, chemical etching the beveled wafer so as to be removed damages of a surface of the wafer, and mirror-polishing the etched wafer, and the pure carbon is added to the raw material of polycrystalline silicon so that a density of carbon in the ingot becomes 1×1015 to 5×1015 atoms/cm3.Type: ApplicationFiled: April 29, 2011Publication date: October 27, 2011Applicant: SUMCO CORPORATIONInventors: Kazuhiro HARADA, Hisashi Furuya, Yukio MUROI
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Patent number: 8043970Abstract: Slurry compositions for selectively polishing silicon nitride relative to silicon oxide, methods of polishing a silicon nitride layer and methods of manufacturing a semiconductor device using the same are provided. The slurry compositions include a first agent for reducing an oxide polishing rate, an abrasive particle and water, and the first agent includes poly(acrylic acid). The slurry composition may have a high polishing selectivity of silicon nitride relative to silicon oxide to be employed in selectively polishing a silicon nitride layer in a semiconductor manufacturing process.Type: GrantFiled: July 3, 2008Date of Patent: October 25, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Won Lee, Sang-Yeob Han, Chang-Ki Hong, Jae-Dong Lee
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Patent number: 8034718Abstract: Disclosed are embodiments of a method of removing patterned circuit structures from the surface of a semiconductor wafer. The method embodiments comprise blasting the surface of the semiconductor wafer with particles so as to remove substantially all of the patterned circuit structures. The blasting process is followed by one or more grinding, polishing and/or cleaning processes to remove any remaining circuit structures, to remove any lattice damage and/or to achieve a desired smoothness across the surface of the semiconductor wafer.Type: GrantFiled: February 15, 2008Date of Patent: October 11, 2011Assignee: International Business Machines CorporationInventors: Steven R. Codding, David Domina, James L. Hardy, Jr., Timothy C. Krywanczyk
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Patent number: 8029687Abstract: The present invention provides a low-cost polishing slurry having excellent effect with respect to defects and smoothness of the surface to be polished. The polishing slurry comprises a silica abrasive and a ceria abrasive, wherein the silica abrasive content is less than 3 mass % and the ceria abrasive content is less than 1 mass %, based on the entire polishing slurry. Further, the present invention provides a method for producing a crystallized glass substrate for an information recording medium, wherein the method use a polishing slurry of the present invention. Furthermore, the present invention provides a method for producing an information recording medium, comprising forming a recording layer on a crystallized glass substrate for an information recording medium obtained by the present method.Type: GrantFiled: August 29, 2005Date of Patent: October 4, 2011Assignee: Showa Denko K.K.Inventors: Katsuaki Aida, Hiroyuki Machida, Kazuyuki Haneda
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Patent number: 8030213Abstract: To provide a polishing technique with which in production of a semiconductor integrated circuit device, when a plane to be polished is polished, an appropriate polishing rate ratio of a polysilicon film to another material can be obtained, whereby high level planarization of a plane to be polished including a polysilicon film can be realized. A polishing compound for chemical mechanical polishing, containing cerium oxide particles, a water-soluble polyamine and water and having a pH within a range of from 10 to 13, is used.Type: GrantFiled: September 17, 2007Date of Patent: October 4, 2011Assignees: Asahi Glass Company, Limited, AGC Seimi Chemical Co., Ltd.Inventors: Iori Yoshida, Yoshinori Kon
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Publication number: 20110237078Abstract: A method of manufacturing a SiC substrate which has a first principal surface and a second principal surface, includes the step of removing, by a vapor phase etching process, at least a portion of a work-affected layer which is formed by mechanical flattening or cutting on the first principal surface of the SiC substrate.Type: ApplicationFiled: June 3, 2011Publication date: September 29, 2011Applicant: HITACHI METALS, LTD.Inventor: Taisuke HIROOKA
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Patent number: 8021566Abstract: An apparatus and method suitable for the pre-conditioning of a polishing pad on a CMP apparatus prior to the polishing of production wafers on the apparatus. The apparatus includes a pre-conditioning arm on which is mounted an ingot of suitable material. In use, the ingot is pressed against the polishing surface of the rotating polishing pad for a selected period of time to increase the temperature of the polishing surface by friction. The pre-conditioned polishing pad facilitates uniform polishing rates of production semiconductor wafers subsequently polished on the apparatus.Type: GrantFiled: August 2, 2006Date of Patent: September 20, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Che Chuang, Wen-Chih Chiou, Hsin-Hsien Lu, Liang-Guang Chen
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Patent number: 8021983Abstract: A method of forming a pattern of an inorganic material film, which method is more versatile, easy, and practical. The method includes the steps of: (a) forming a sacrifice layer having a pattern on a substrate by employing a material having a different thermal expansion coefficient from that of an inorganic material of the inorganic material film; (b) forming an inorganic material layer on the substrate, on which the sacrifice layer has been formed, at a predetermined deposition temperature by employing the inorganic material; (c) lowering a temperature of at least the inorganic material layer to produce cracks in the inorganic material layer formed on the sacrifice layer; and (d) removing the sacrifice layer and the inorganic material layer formed thereon.Type: GrantFiled: August 15, 2007Date of Patent: September 20, 2011Assignee: FUJIFILM CorporationInventors: Yoshikazu Hishinuma, Takamichi Fujii
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Patent number: 8008172Abstract: A method of forming a semiconductor device includes: forming a pattern having trenches on a semiconductor substrate; forming a semiconductor layer on the semiconductor device that fills the trenches; planarizing the semiconductor layer using a first planarization process without exposing the pattern; performing an epitaxy growth process on the first planarized semiconductor layer to form a crystalline semiconductor layer; and planarizing the crystalline semiconductor layer until the pattern is exposed to form a crystalline semiconductor pattern.Type: GrantFiled: February 15, 2008Date of Patent: August 30, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Heun Lim, Chang-Ki Hong, Bo-Un Yoon, Seong-Kyu Yun, Suk-Hun Choi, Sang-Yeob Han
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Patent number: 8008201Abstract: Aqueous cerium oxide dispersion Aqueous cerium oxide dispersion, containing 5 to 60% by weight cerium oxide. It can be used to polish SiO2 in the semiconductor industry.Type: GrantFiled: March 8, 2006Date of Patent: August 30, 2011Assignee: Evonik Degussa GmbHInventors: Michael Kröll, Stefan Heberer, Stipan Katusic, Michael Krämer, Wolfgang Lortz
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Patent number: 8007676Abstract: A slurry composition includes an acidic aqueous solution and one or both of, an amphoteric surfactant and a glycol compound. Examples of the amphoteric surfactant include a betaine compound and an amino acid compound, and examples of the amino acid compound include lysine, proline and arginine. Examples of the glycol compound include diethylene glycol, ethylene glycol and polyethylene glycol.Type: GrantFiled: May 29, 2008Date of Patent: August 30, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hyun So, Sung-Taek Moon, Dong-Jun Lee, Nam-Soo Kim, Bong-Su Ahn, Kyoung-Moon Kang
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Patent number: 8003537Abstract: A method for the production of a planar structure is disclosed. The method comprises producing on a substrate a plurality of structures of substantially equal height, and there being a space in between the plurality of structures. The method further comprises providing a fill layer of electromagnetic radiation curable material substantially filling the space between the structures. The method further comprises illuminating a portion of the fill layer with electromagnetic radiation, hereby producing a exposed portion and an unexposed portion, the portions being separated by an interface substantially parallel with the first main surface of the substrate. The method further comprises removing the portion above the interface.Type: GrantFiled: July 18, 2007Date of Patent: August 23, 2011Assignees: IMEC, Katholieke Universiteit LeuvenInventors: Xavier Rottenberg, Phillip Ekkels, Hendrikus Tilmans, Walter De Raedt
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Patent number: 7998867Abstract: An epitaxial wafer is provided capable of eliminating particles in a device process, particles being generated from a scratch in a boundary area between a rear surface and a chamfered surface of a wafer. The scratch in the boundary area between the rear surface and the chamfered surface is removed in a scratch removal process. Thus, no particles exist caused by a scratch, at a time of immersion in an etching solution in the device process, and thus a device yield is increased.Type: GrantFiled: November 6, 2008Date of Patent: August 16, 2011Assignee: Sumco CorporationInventors: Kazushige Takaishi, Tomonori Miura
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Patent number: 7998866Abstract: The inventive method comprises chemically-mechanically polishing a substrate comprising at least one layer of silicon carbide with a polishing composition comprising a liquid carrier, an abrasive, and an oxidizing agent.Type: GrantFiled: March 5, 2008Date of Patent: August 16, 2011Assignee: Cabot Microelectronics CorporationInventors: Michael L. White, Lamon Jones, Jeffrey Gilliland, Kevin Moeggenborg
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Patent number: 7994057Abstract: The inventive method comprises chemically-mechanically polishing a substrate with an inventive polishing composition comprising a liquid carrier, a cationic polymer, an acid, and abrasive particles that have been treated with an aminosilane compound.Type: GrantFiled: September 19, 2008Date of Patent: August 9, 2011Assignee: Cabot Microelectronics CorporationInventors: Jeffrey Dysard, Sriram Anjur, Steven Grumbine, Daniela White, William Ward
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Patent number: 7989358Abstract: A method of preventing the formation of cracks on the backside of a silicon (Si) semiconductor chip or wafer during the processing thereof. Also provided is a method for inhibiting the propagation of cracks, which have already formed in the backside of a silicon chip during the processing thereof and prior to the joining thereto of a substrate during the fabrication of an electronic package. The methods entail either treating the backside with a wet etch, or alternatively, applying a protective film layer thereon prior to forming an electronic package incorporating the chip or wafer.Type: GrantFiled: April 22, 2008Date of Patent: August 2, 2011Assignee: International Business Machines CorporationInventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Jerome B. Lasky, Christopher D. Muzzy, Wolfgang Sauter
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Patent number: 7989348Abstract: A polishing method that carries out a multi-step polishing process with improved polishing conditions (polishing recipe) while omitting measurement of the surface conditions of a substrate, as carried out between polishing steps thereby increasing the throughput.Type: GrantFiled: August 23, 2006Date of Patent: August 2, 2011Assignee: Ebara CorporationInventors: Kuniaki Yamaguchi, Tsuneo Torikoshi
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Patent number: 7985681Abstract: A method for patterning a material during fabrication of a semiconductor device provides for the selective formation of either asymmetrical features or symmetrical features using a symmetrical photomask, depending on which process flow is chosen. The resulting features which are fabricated use spacers formed around a patterned material. If one particular etch is used to remove a base material, symmetrical features result. If two particular etches are used to remove the base material, asymmetrical features remain.Type: GrantFiled: June 22, 2007Date of Patent: July 26, 2011Assignee: Micron Technology, Inc.Inventors: Hongbin Zhu, Jeremy Madsen
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Patent number: 7981793Abstract: By suppressing the presence of free oxygen during a cleaning process and a subsequent electrochemical deposition of a seed layer, the quality of a corresponding interface between the barrier material and the seed layer may be enhanced, thereby also improving performance and the characteristics of the finally obtained metal region. Thus, by identifying free oxygen as a main source for negatively affecting the characteristics of metals during a “direct on barrier” plating process, efficient strategies have been developed and are disclosed herein to provide a reliable technique for volume production of sophisticated semiconductor devices.Type: GrantFiled: March 11, 2008Date of Patent: July 19, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Axel Preusse, Charlotte Emnet, Susanne Wehner
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Patent number: 7981801Abstract: A method for fabricating a semiconductor device is provided which includes providing a semiconductor substrate, forming a plurality of transistors, each transistor having a dummy gate structure, forming a contact etch stop layer (CESL) over the substrate including the dummy gate structures, forming a first dielectric layer to fill in a portion of each region between adjacent dummy gate structures, forming a chemical mechanical polishing (CMP) stop layer over the CESL and first dielectric layer, forming a second dielectric layer over the CMP stop layer, performing a CMP on the second dielectric layer that substantially stops at the CMP stop layer, and performing an overpolishing to expose the dummy gate structure.Type: GrantFiled: April 14, 2009Date of Patent: July 19, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry Chuang, Kong-Beng Thei, Su-Chen Lai, Gary Shen
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Patent number: 7981238Abstract: A method relaxing a strained thin film, secured via a first main face of an initial support, the second main face of the thin film being a contact face. The method supplies an intermediate support including a polymer layer having a main free contact face, the polymer's thermal expansion coefficient being greater than that of the thin film, adhesively brings into contact the contact face of the strained thin film with the contact face of the polymer layer, eliminates the initial support, realizing relaxation of the thin film through formation of wrinkles and revealing the first main face of the thin film, increases the polymer layer temperature to stretch the relaxed thin film and eliminate the wrinkles, secures the first main face of the thin film with one face of a receiving substrate, and eliminates the intermediate support to obtain a relaxed thin film integral with the receiving substrate.Type: GrantFiled: December 26, 2006Date of Patent: July 19, 2011Assignee: Commissariat a l'Energie AtomiqueInventors: Lea Di Cioccio, Damien Bordel, Genevieve Grenet, Philippe Regreny
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Patent number: 7972962Abstract: A method of planarizing a semiconductor device is provided. The semiconductor device includes a substrate, first and second components provided on the surface of the substrate, and a first material provided between and above the first and second components. The first component has a height greater than a height of the second component. The method includes performing a first polishing step on the semiconductor device to remove the first material above a top surface of the first component, to remove the first material above a top surface of the second component, and to level the top surface of the first component. The method also includes performing a second polishing step on the semiconductor device to planarize the top surfaces of the first and second components.Type: GrantFiled: September 21, 2010Date of Patent: July 5, 2011Assignees: Spansion LLC, Globalfoundries Inc.Inventors: David Matsumoto, Vidyut Gopal
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Patent number: 7972963Abstract: A polished semiconductor wafer has a front surface and a back surface and an edge R, which is located at a distance of a radius from a center of the semiconductor wafer, forms a periphery of the semiconductor wafer and is part of a profiled boundary of the semiconductor wafer. The maximum deviation of the flatness of the back surface from an ideal plane in a range between R-6 mm and R-1 mm of the back surface is 0.7 ?m or less. A process for producing the semiconductor wafer, comprises at least one treatment of the semiconductor wafer with a liquid etchant and at least one polishing of at least a front surface of the semiconductor wafer, the etchant flowing onto a boundary of the semiconductor wafer during the treatment, and the boundary of the semiconductor wafer which faces the flow of etchant being at least partially shielded from being struck directly by the etchant. The shielding extends in the direction of a thickness d of the semiconductor wafer and is at least d+100 ?m long.Type: GrantFiled: October 11, 2007Date of Patent: July 5, 2011Assignee: Siltronic AGInventors: Thomas Teuschler, Guenter Schwab, Maximilian Stadler
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Patent number: 7968443Abstract: A cross method for fabricating a CMOS integrated circuit (IC) includes providing a semiconductor wafer having a topside semiconductor surface, a bevel semiconductor surface, and a backside semiconductor surface, wherein the bevel semiconductor surface and backside semiconductor surface include silicon or germanium. A metal including high-k gate dielectric layer is formed on at least the topside semiconductor surface and on at least a portion of the bevel semiconductor surface and backside semiconductor surface. The high-k dielectric material on the bevel semiconductor surface and the backside semiconductor surface are selectively removed while protecting the high-k dielectric layer on the topside semiconductor surface. The selective removing includes a first oxidizing treatment, and a fluoride including wet etch follows the first oxidizing treatment. The fabrication of the IC is completed including forming at least one metal gate layer on the high-k gate dielectric layer after the selectively removing step.Type: GrantFiled: December 26, 2008Date of Patent: June 28, 2011Assignee: Texas Instruments IncorporatedInventors: Brian K. Kirkpatrick, James J. Chambers
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Patent number: 7964507Abstract: A method of manufacturing an electronic device (10) provides a substrate (20) that has a plastic material. A particulate material (16) is embedded in at least one surface of the substrate. A layer of thin-film semiconductor material is deposited onto the substrate (20).Type: GrantFiled: February 1, 2010Date of Patent: June 21, 2011Assignee: Eastman Kodak CompanyInventors: Timothy J. Tredwell, Roger S. Kerr