Abstract: A semiconductor device including a second magnetic tunnel junction stack aligned above a spin conductor layer above a first magnetic junction stack, a sidewall dielectric surrounding the second magnetic tunnel junction stack, a vertical side surface of the sidewall dielectric is aligned with vertical side surfaces of the spin conductor layer and the first magnetic junction stack. A method including forming a first magnetic tunnel junction stack, a spin conductor layer and a second magnetic tunnel junction stack, patterning the second magnetic tunnel junction stack, while not patterning the spin conductor layer and the first magnetic tunnel junction stack, forming a sidewall dielectric and a polymer layer on the sidewall dielectric. A method including patterning a second magnetic tunnel junction stack, while not patterning a spin conductor layer below the second magnetic tunnel junction stack nor a first magnetic tunnel junction stack below the spin conductor layer.

Abstract: A method of forming alignment marks includes providing a III-V compound substrate having a device region and an alignment mark region, forming a hardmask layer having a first set of openings on the alignment mark region exposing a first surface portion of the III-V compound substrate and a second set of openings on the device region exposing a second surface portion of the III-V compound substrate, etching the exposed surface of the III-V compound substrate using the hardmask layer as a mask to form a plurality of trenches, and epitaxially regrowing a semiconductor layer in the trenches to form the alignment marks extending to a predetermined height over the processing surface of the III-V compound substrate.

Abstract: A plasma processing method includes: supplying a gas into a processing container; and intermittently supplying microwave powers output from a plurality of microwave introducing modules into the processing container. In the intermittently supplying the microwave powers, the supply of all the microwave powers from the plurality of microwave introducing modules is periodically in an OFF state for a given time.

Abstract: Disclosed is a semiconductor processing approach wherein a wafer twist is employed to increase etch rate, at select locations, along a hole or space end arc. By doing so, a finished hole may more closely resemble the shape of the incoming hole end. In some embodiments, a method may include providing an elongated contact hole formed in a semiconductor device, and etching the elongated contact hole while rotating the semiconductor device, wherein the etching is performed by an ion beam delivered at a non-zero angle relative to a plane defined by the semiconductor device. The elongated contact hole may be defined by a set of sidewalls opposite one another, and a first end and a second end connected to the set of sidewalls, wherein etching the elongated contact hole causes the elongated contact hole to change from an oval shape to a rectangular shape.

Abstract: The present invention relates to: a method of manufacturing glass with hollow nanopillars, which includes a silicon oxide layer forming step in which a silicon oxide layer made of silicon oxide is formed on one side of a glass substrate, a first etching step in which the silicon oxide layer is etched and a plurality of silicon oxide clusters are formed on the glass substrate, and a second etching step in which the glass substrate, on which the silicon oxide clusters are formed, is etched and hollow nanopillars are formed; and glass with hollow nanopillars manufactured thereby.

Abstract: The method of dry-etching silicon oxide of the present disclosure includes reacting silicon oxide with any one of the following (A) to (C): (A) a gaseous hydrogen fluoride and a gaseous organic amine compound, (B) a gaseous hydrogen fluoride salt of an organic amine compound, and (C) a gaseous hydrogen fluoride, a gaseous organic amine compound, and a gaseous hydrogen fluoride salt of an organic amine compound in a non-plasma state.

Abstract: A semiconductor device may include a first semiconductor substrate having a first surface and a second surface opposite to each other, a first circuit layer provided on the first surface of the first semiconductor substrate, a connection pad provided on the second surface of the first semiconductor substrate, and a first penetration via and a second penetration via penetrating the first semiconductor substrate and at least a portion of the first circuit layer. The first penetration via and the second penetration via may be provided in a first penetration hole and a second penetration hole, respectively. Each of the first and second penetration holes may include a first portion, a second portion, and a third portion. A width of the first portion of the first penetration hole may be smaller than a width of the first portion of the second penetration hole.

Abstract: The invention relates to a method of fabricating a micro machined channel, comprising the steps of providing a substrate of a first material and having a buried layer of a different material therein, and forming at least two trenches in said substrate by removing at least part of said substrate. Said trenches are provided at a distance from each other and at least partly extend substantially parallel to each other, as well as towards said buried layer. The method comprises the step of forming at least two filled trenches by providing a second material different from said first material and filling said at least two trenches with at least said second material; forming an elongated cavity in between said filled trenches by removing at least part of said substrate extending between said filled trenches; and forming an enclosed channel by providing a layer of material in said cavity and enclosing said cavity.

Abstract: A probe head includes upper and lower die units, and a linear probe inserted therethrough and thereby defined with tail, body and head portions. A first bottom surface of the upper die unit and a second top surface of the lower die unit face each other, thereby defining an inner space wherein the body portion is located and includes a plurality of sections each having front width larger than or equal to back width, including a narrowest section whose upper and lower ends have a distance from the first bottom surface and the second top surface respectively. The head and tail portions are offset from each other along two horizontal axes and the body portion is thereby curved. The present invention is favorable in dynamic behavior control of the linear probe which is easy in manufacturing, lower in cost and has more variety in material.

Abstract: In some embodiments of the present disclosure, a method of manufacturing a semiconductor structure includes providing a substrate including a first atom and a second atom; forming a compound over the substrate by bonding the first atom with a ionized etchant; and removing the compound from the substrate by bombarding the compounds with a charged particle having a bombarding energy smaller than a bonding energy between the first atom and the second atom, wherein the charged particle and the ionized etchant include different ions.

Abstract: Disclosed is a semiconductor processing approach wherein a wafer twist is employed to increase etch rate, at select locations, along a hole or space end arc. By doing so, a finished hole may more closely resemble the shape of the incoming hole end. In some embodiments, a method may include providing an elongated contact hole formed in a semiconductor device, and etching the elongated contact hole while rotating the semiconductor device, wherein the etching is performed by an ion beam delivered at a non-zero angle relative to a plane defined by the semiconductor device. The elongated contact hole may be defined by a set of sidewalls opposite one another, and a first end and a second end connected to the set of sidewalls, wherein etching the elongated contact hole causes the elongated contact hole to change from an oval shape to a rectangular shape.

Abstract: The gallium arsenide single crystal substrate has a circular main surface, and when the diameter of the main surface of the gallium arsenide single crystal substrate is represented by D and the number of etch pits formed on the main surface by immersing the gallium arsenide single crystal substrate in molten potassium hydroxide at 500° C. for 10 minutes is counted, the number C1 of etch pits in a first circular region having a diameter of 0.2D around the center of the main surface is 0 or more and 10 or less.

Abstract: A semiconductor structure is provided in the present invention, including a substrate having a device region and an alignment mark region defined thereon, a dielectric layer disposed on the substrate, a conductive via formed in the dielectric layer on the device region, a first trench formed in the dielectric layer on the alignment mark, a plurality of second trenches formed in the dielectric layer directly under the first trench and exposed from a bottom surface of the first trench, and a memory stacked structure disposed on the dielectric layer, directly covering a top surface of the conductive via and filling into the first trench and the second trench.

Abstract: Disclosed are a gas showerhead, a method of manufacturing the same, and a plasma apparatus provided with the gas showerhead. The gas showerhead comprises a back plate and a gas distribution plate, the gas distribution plate including a plurality of annular gas distribution regions with the center of the gas distribution plate as their center; on each annular gas distribution region are provided a plurality of gas through-holes penetrating through the gas inlet face and the gas outlet face, the gas through-holes at least including a plurality of first gas through-holes inclined at a certain angle, and the gas through-holes further include a plurality of second gas through-holes, the second gas through-holes being parallel to the central axis or having a radial inclination direction different from the first gas through-holes; and in the same annular gas distribution region, gas flowing out of the first gas through-holes and gas flowing out of the second gas through-holes are kept away from each other.

Abstract: A method for fabricating a fluidic device includes depositing a sacrificial material on a pillar array arranged on a substrate. The method also includes removing a portion of the sacrificial material. The method further includes depositing a sealing layer on the pillar array to form a sealed fluidic cavity.

Abstract: In a disclosed method, etching a film by using plasma of a first processing gas and etching the film by using plasma of a second processing gas are alternately repeated. The first processing gas and the second processing gas each include a fluorocarbon gas. In etching the film by using the plasma of the first processing gas and etching the film by using the plasma of the second processing gas, radio frequency power is used to attract ions to the substrate. The first processing gas further includes an additive gas that is a source for nitrogen or sulfur and fluorine. In the first processing gas, the flow rate of the additive gas is smaller than the flow rate of the fluorocarbon gas.

Abstract: A method of fabricating a semiconductor structure including the following steps is provided. A mask layer is formed on a semiconductor substrate. The semiconductor substrate revealed by the mask layer is anisotropically etched until a cavity is formed in the semiconductor substrate, wherein anisotropically etching the semiconductor substrate revealed by the mask layer comprises performing a plurality of first cycles and performing a plurality of second cycles after performing the first cycles, each cycle among the first and second cycles respectively includes performing a passivating step and performing an etching step after performing the passivating step. During the first cycles, a first duration ratio of the etching step to the passivating step is variable and ramps up step by step. During the second cycles, a second duration ratio of the etching step to the passivating step is constant, and the first duration ratio is less than the second duration ratio.

Abstract: Techniques for planarizing surfaces are disclosed herein. One example includes orienting a surface of a sample to a charged particle beam axis, the sample including a first layer formed from first and second materials, the first material patterned into a plurality of parallel lines and disposed in the second material, where the surface is oriented to form a shallow angle with the charged particle beam axis and to arrange the plurality of parallel lines perpendicular to the charged particle beam axis, providing a charged particle beam toward the surface, providing a gas to the surface, and selectively etching, with ion induced chemical etching, the second material at least down to a top surface of the first material, the charged particle induced etching stimulated due to concurrent presence of the charged particle beam and the gas over the surface of the sample.

Abstract: There is provided an etching method which includes: preparing a target substrate having a silicon portion, a silicon nitride film and a silicon oxide film; and selectively etching the silicon portion with respect to the silicon nitride film and the silicon oxide film by supplying a fluorine-containing gas and an inert gas which stay in an excited state to the target substrate.

Abstract: A method for making carbon nanotube film includes providing a growth substrate having a first surface and a second surface opposite to the first surface. A catalyst layer is placed on the first surface. The growth substrate and the catalyst layer are placed in a reaction chamber. The carbon source gas and hydrogen are supplied into the reaction chamber at a growth temperature of a plurality of carbon nanotubes. An electric field is applied to the growth substrate, wherein an electric field direction of the electric field is from the first surface to the second surface. After the plurality of carbon nanotubes fly away from the growth substrate, the electric field is stopped applying to the growth substrate, and the carbon source gas and hydrogen are continually supplied into the reaction chamber.

Abstract: Disclosed is a semiconductor processing approach wherein a wafer twist is employed to increase etch rate, at select locations, along a hole or space end arc. By doing so, a finished hole may more closely resemble the shape of the incoming hole end. In some embodiments, a method may include providing an elongated contact hole formed in a semiconductor device, and etching the elongated contact hole while rotating the semiconductor device, wherein the etching is performed by an ion beam delivered at a non-zero angle relative to a plane defined by the semiconductor device. The elongated contact hole may be defined by a set of sidewalls opposite one another, and a first end and a second end connected to the set of sidewalls, wherein etching the elongated contact hole causes the elongated contact hole to change from an oval shape to a rectangular shape.

Abstract: Techniques are disclosed for fabricating a self-aligned spin-transfer torque memory (STTM) device with a dot-contacted free magnetic layer. In some embodiments, the disclosed STTM device includes a first dielectric spacer covering sidewalls of an electrically conductive hardmask layer that is patterned to provide an electronic contact for the STTM's free magnetic layer. The hardmask contact can be narrower than the free magnetic layer. The first dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer. In some embodiments, the STTM further includes an optional second dielectric spacer covering sidewalls of its free magnetic layer. The second dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer and may serve, at least in part, to protect the sidewalls of the free magnetic layer from redepositing of etch byproducts during such patterning, thereby preventing electrical shorting between the fixed magnetic layer and the free magnetic layer.

Abstract: A processing method including a first step of supplying a first gas including a carbon-containing gas and an inert gas into an inside of a chamber and a second step of generating plasma from the supplied first gas by applying high frequency power for generating plasma and causing a chemical compound including organic matter on a pattern of a predetermined film formed on an object to be processed, wherein a ratio of the carbon-containing gas relative to the inert gas included in the first gas is 1% or less.

Abstract: A method of fabricating a semiconductor structure including the following steps is provided. A mask layer is formed on a semiconductor substrate. The semiconductor substrate revealed by the mask layer is anisotropically etched until a cavity is formed in the semiconductor substrate, wherein anisotropically etching the semiconductor substrate revealed by the mask layer comprises performing a plurality of first cycles and performing a plurality of second cycles after performing the first cycles, each cycle among the first and second cycles respectively includes performing a passivating step and performing an etching step after performing the passivating step. During the first cycles, a first duration ratio of the etching step to the passivating step is variable and ramps up step by step. During the second cycles, a second duration ratio of the etching step to the passivating step is constant, and the first duration ratio is less than the second duration ratio.

Abstract: Embodiments of the present disclosure may be used for patterning a layer in a 5 nm node or beyond fabrication to achieve an end-to-end distance below 35 nm. Compared to the state of the art technology, embodiments of the present disclosure reduce cycle time and cost of production from three lithographic processes and four etching processes to one lithographic process and three etch processes.

Abstract: A method for manufacturing a semiconductor device includes patterning a plurality of fins on a semiconductor substrate, wherein a hardmask is formed on each of the plurality of fins, forming a dielectric layer on the semiconductor substrate between the plurality of fins, removing the hardmasks from each of the plurality of fins, forming a plurality of cap layers in place of the removed hardmasks on each of the plurality of fins, wherein the plurality of cap layers comprise at least one of amorphous silicon and polycrystalline silicon, and selectively recessing the dielectric layer with respect to the plurality of cap layers.

Abstract: The invention includes a method of promoting atomic layer etching (ALE) of a surface. In certain embodiments, the method comprises contacting a solid substrate comprising a first metal compound with an oxidant, optionally contacting the solid substrate with a second metal compound, and then contacting the modified solid substrate with a fluorinating agent, whereby ALE of the solid substrate is promoted.

Abstract: The invention relates to a method for texturing a semiconductor substrate (1), comprising steps consisting in forming a plurality of cavities of random shapes, depths and distribution, in an etch mask (2), by means of non-homogeneous reactive-ion etching, forming a first rough random design, and etching the substrate using the etch mask, by means of reactive-ion etching, in such a way as to transfer the first rough random design into the substrate and to produce a second rough random design (200), comprising cavities (20) of random shapes, depths (d2r) and distribution, on the surface of the substrate.

Abstract: A method of manufacturing a wafer. The method includes providing a wafer and testing the wafer. Based on a test result, a substance is selectively provided on the wafer to obtain an altered wafer that has at least one selected portion altered. The method includes forming a structural layer over the altered wafer.

Abstract: A carbonaceous material is removed using a low energy focused ion beam in the presence of an etch-assisting gas. Applicant has discovered that when the beam energy of the FIB is lowered, an etch-assisting gas, such as O2, greatly increases the etch rate. In one example, polyimide material etched using a Xe+ plasma FIB with a beam energy from 8 keV to 14 keV and O2 as an etch-assisting gas, the increase in etch rate can approach 30× as compared to the default mill rate.

Abstract: Devices and methods for forming semiconductor devices with wider FinFETs for higher tunability of the varactor are provided. One method includes, for instance: obtaining an intermediate semiconductor device; applying a spacer layer over the semiconductor device; etching the semiconductor device to remove at least a portion of the spacer layer to expose the plurality of mandrels; removing the mandrels; etching the semiconductor device to remove a portion of the dielectric layer; forming at least one fin; and removing the spacer layer and the dielectric layer. One intermediate semiconductor device includes, for instance: a substrate; a dielectric layer over the substrate; a plurality of mandrels formed on the dielectric layer, the mandrels including a first set of mandrels and a second set of mandrels, wherein the first set of mandrels have a width twice as large as the second set of mandrels; and a spacer layer applied over the mandrels.

Abstract: Some embodiments of the present disclosure relate to a contact formed to a source or drain region of a “finned” field-effect transistor (FinFET). An epitaxial material is formed over the source or drain region, which includes a diamond-shaped cross-section with top and bottom surfaces. A capping layer is formed over the top and bottom surfaces. The source or drain region is subjected to a first etch to remove the capping layer surrounding the top surfaces of the diamond-shaped cross-section. A protective layer is formed within the top surfaces. A second etch of the capping layer is performed to remove the capping layer surrounding the bottom surfaces of the diamond-shaped cross-section, while using the protective layer to prevent etching of the top surfaces by the second etch. A contact is formed to the source or drain region, which surrounds the source or drain region on the top and bottom surfaces.

Abstract: A method includes forming a patterned mask layer over a conductive layer; forming a first dielectric layer over the patterned mask layer and the conductive layer; selectively etching the first dielectric layer, thereby exposing an upper surface of the patterned mask layer, wherein the upper surface of the first dielectric layer is lower than a top surface of the patterned mask layer; removing the patterned mask layer; and selectively etching the conductive layer to form a conductive feature having a tapered profile.

Abstract: An electron beam plasma source is used in a soft plasma surface treatment of semiconductor surfaces containing Ge or group III-V compound semiconductor materials.

Abstract: Techniques herein include methods for etching an oxide layer with greater selectivity to underlying channel materials. Such an increase in etch selectivity reduces damage to channel materials thereby providing more reliable and better performing semiconductor devices. Techniques herein include using fluorocarbon gas to feed a plasma to create etchants, and also creating a flux of ballistic electrons to treat a given substrate during an etch process.

Abstract: A method of forming an array of nanostructures includes forming a plurality of seed points on a surface of a substrate, and growing masks from the seed points to create masked regions of the substrate underlying the masks. A remainder of the substrate comprises an unmasked region. Each mask and masked region increase in size with growth time while the unmasked region of the substrate decreases in size. During the growing, the unmasked region is etched to remove material from the substrate in a depth direction, and, simultaneously, unetched structures are formed from the masked regions of the substrate underlying the masks. Each of the unetched structures has a lateral size that increases with depth.

Abstract: A method of etching patterned heterogeneous silicon-containing structures is described and includes a remote plasma etch with inverted selectivity compared to existing remote plasma etches. The methods may be used to conformally trim polysilicon while removing little or no silicon oxide. More generally, silicon-containing films containing less oxygen are removed more rapidly than silicon-containing films which contain more oxygen. Other exemplary applications include trimming silicon carbon nitride films while essentially retaining silicon oxycarbide. Applications such as these are enabled by the methods presented herein and enable new process flows. These process flows are expected to become desirable for a variety of finer linewidth structures. Methods contained herein may also be used to etch silicon-containing films faster than nitrogen-and-silicon containing films having a greater concentration of nitrogen.

Abstract: This description relates to a method of making a semiconductor device including forming an inter-level dielectric (ILD) layer over a substrate and forming a layer set over the ILD layer. The method further includes etching the layer set to form a tapered opening in the layer set and etching the ILD layer using the layer set as a mask to form an opening in the ILD layer. The opening in the ILD layer has a line width roughness (LWR) of less than 3 nanometers (nm). This description also relates to a semiconductor device including an inter-level dielectric (ILD) layer over a substrate; and a layer set over the ILD layer. The layer set has a tapered opening within the layer set. Etching the layer set comprises forming the tapered opening having sidewalls at an angle with respect to a top surface of the ILD layer ranging from 85-degrees to 90-degrees.

Abstract: A mechanism for forming a semiconductor device is described. The semiconductor device includes a substrate and an inter-layer dielectric (ILD) layer over the substrate. The intermediate semiconductor device further includes a first layer set over the ILD layer and a second layer set over the first layer set. The intermediate semiconductor device further includes a photoresist layer over the second layer set. The method further includes etching the second layer set to form a tapered opening in the second layer set, the tapered opening having sidewalls at an angle with respect to a top surface of the ILD layer ranging from about 85-degrees to about 90-degrees, but less than 90-degrees. The method further includes etching the first layer set to form an opening in the first layer set and etching the ILD layer using the first layer set as a mask to form an opening in the ILD layer.

Abstract: Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and HCl can be used for selective etching copper with respect to the liner material, for example, the copper film can be recessed between 2 and 3 nm, and the barrier liner film can be recessed between 1.5 and 2 nm.

Abstract: A method and system for improved planar deprocessing of semiconductor devices using a focused ion beam system. The method comprises defining a target area to be removed, the target area including at least a portion of a mixed copper and dielectric layer of a semiconductor device; directing a precursor gas toward the target area; and directing a focused ion beam toward the target area in the presence of the precursor gas, thereby removing at least a portion of a first mixed copper and dielectric layer and producing a uniformly smooth floor in the milled target area. The precursor gas causes the focused ion beam to mill the copper at substantially the same rate as the dielectric. In a preferred embodiment, the precursor gas comprises methyl nitroacetate. In alternative embodiments, the precursor gas is methyl acetate, ethyl acetate, ethyl nitroacetate, propyl acetate, propyl nitroacetate, nitro ethyl acetate, methyl methoxyacetate, or methoxy acetylchloride.

Abstract: Methods for etching a substrate in a plasma processing chamber having at least a primary plasma generating region and a secondary plasma generating region separated from said primary plasma generating region by a semi-barrier structure. The method includes generating a primary plasma from a primary feed gas in the primary plasma generating region. The method also includes generating a secondary plasma from a secondary feed gas in the secondary plasma generating region to enable at least some species from the secondary plasma to migrate into the primary plasma generating region. The method additionally includes etching the substrate with the primary plasma after the primary plasma has been augmented with migrated species from the secondary plasma.

Abstract: Etched substrates, and particularly, light-absorbing etched substrates, and methods for making such substrates are described.

Abstract: A process for forming trenches in a target material includes forming a masking layer onto the target material, where the masking layer comprises a material having high selectivity to a plasma etch gas adapted for etching the target material. A pattern is formed in the masking layer to expose portions of the target material and the sample is placed on an angle mount at a pre-determined angle relative to a cathode of a reactive ion etcher so that the target material is within a plasma dark space of the plasma etch gas. Ballistic ions within the plasma dark space form a trench structure within the target material. The process may further include repeating the steps of positioning the sample and etching the exposed portions of the target material with the substrate at a dif ferent angle to define a triangular structure.

Abstract: In a method for making graphitic ribbons in a face of a carbide crystal (110), in which an elongated trench (120) is formed along a predetermined path in the face (112) of the carbide crystal (110), the trench (120) including a horizontal floor (124) coupling two vertical walls (122), the trench (120) following a path on which it is desired to form a graphitic ribbon (130). The carbide crystal (110) and the trench (120) are subjected to an annealing environment for an amount of time sufficient to cause a graphene ribbon (130) having a V-shaped cross section to form along the predetermined path of the trench (120).

Abstract: In some embodiments of the present disclosure, an apparatus includes an ionizer. The ionizer is configured to dispatch a reactive ion on a surface. The apparatus also has an implanter and the implanter has an outlet releasing an accelerated charged particle on the surface.

Abstract: A method for producing an optical semiconductor device includes the steps of determining a wafer size to make a section arrangement including a plurality of sections in each of which the optical semiconductor device including a semiconductor mesa is formed; obtaining an in-plane distribution of a thickness of a resin layer on a wafer; obtaining a correlation between a thickness of a resin layer and a trench width; forming a trench width map using the in-plane distribution of the thickness and the correlation; preparing an epitaxial substrate by forming a stacked semiconductor layer; forming, on the epitaxial substrate, a mask based on the trench width map; forming a trench structure including the semiconductor mesa by etching the stacked semiconductor layer using the mask; forming a resin layer on the trench structure; and forming an opening on the semiconductor mesa by etching the resin layer.

Abstract: Methods of selectively etching tungsten relative to silicon-containing films (e.g. silicon oxide, silicon carbon nitride and (poly)silicon) as well as tungsten oxide are described. The methods include a remote plasma etch formed from a fluorine-containing precursor and/or hydrogen (H2). Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the tungsten. The plasma effluents react with exposed surfaces and selectively remove tungsten while very slowly removing other exposed materials. Sequential and simultaneous methods are included to remove thin tungsten oxide which may, for example, result from exposure to the atmosphere.

Abstract: A method of etching a trench in a substrate is provided. The method repeatedly alternates between using a fluorine-based plasma to etch a trench, which has trench sidewalls, into a selected region of the substrate; and using a fluorocarbon plasma to deposit a liner on the trench sidewalls. The liner, when formed and subsequently etched, has an exposed sidewall surface that includes scalloped recesses. The trench, which includes the scalloped recesses, is then bombarded with a molecular beam where the molecules are directed on an axis parallel to the trench sidewalls to reduce the scalloped recesses.

Abstract: There is provided a plasma etching method including a first process of etching an intermediate layer, which contains silicon and nitrogen and is positioned below a resist mask formed on a surface of a substrate, to cause a silicon layer positioned below the intermediate layer to be exposed through the resist mask and the intermediate layer, a second process of subsequently supplying a chlorine gas to the substrate to cause a reaction product to attach onto sidewalls of opening portions of the resist mask and the intermediate layer, and a third process of etching a portion of the silicon layer corresponding to the opening portion of the intermediate layer using a process gas containing sulfur and fluorine to form a recess in the silicon layer.