Abstract: Ultra-low capacitance interconnect structures, preferably Through Silicon Via (TSV) interconnects and methods for fabricating said interconnects are disclosed. The fabrication method comprises the steps of providing a substrate having a first main surface, producing at least one hollow trench-like structure therein from the first main surface, said trench-like structure surrounding an inner pillar structure of substrate material, depositing a dielectric liner which pinches off said hollow trench-like structure at the first main surface such that an airgap is created in the center of hollow trench-like structure and further creating a TSV hole and filling it at least partly with conductive material.

Abstract: A process of forming a MEMS device with a device cavity underlapping an overlying dielectric layer stack having an etchable sublayer over an etch-resistant lower portion, including: etching through at least the etchable sublayer of the overlying dielectric layer stack in an access hole to expose a lateral face of the etchable sublayer, covering exposed surfaces of the etchable sublayer by protective material, and subsequently performing a cavity etch. A cavity etch mask may cover the exposed surfaces of the etchable sublayer. Alternatively, protective sidewalls may be formed by an etchback process to cover the exposed surfaces of the etchable sublayer. Alternatively, the exposed lateral face of the etchable sublayer may be recessed by an isotropic etch, than isolated by a reflow operation which causes edges of an access hole etch mask to drop and cover the exposed lateral face of the etchable sublayer.

Abstract: The present invention generally relates to a method of forming a magnetic head while ensuring residues do not negatively impact the magnetic head. In particular, when performing a RIE process to remove DLC, oxygen gas can leave residues that will negatively impact the RIE process performed on the next substrate to enter the chamber. By utilizing CO2 rather than O2, the residues will not be created and therefore will not impact processing of the next substrate that enters the chamber.

Abstract: The inventive concepts disclosed herein include, for instance, methods for etching a metal layer and methods for manufacturing a semiconductor device using the etched metal layer. A wafer including a metal layer and a mask layer on the metal layer may be loaded into a process chamber. An etching gas may be supplied into the process chamber to etch the metal layer exposed by the mask layer. After the etching process, the mask layer may be removed. The etching gas can include phosphorus (P) and fluorine (F). An RF power may be constantly or selectively supplied to the process chamber, or different levels of RF power can be selectively supplied. An etching gas can be supplied to the process chamber when the RF power is off or at a lower level. A surface activation gas can be supplied when the RF power is on or at a higher level.

Abstract: A method includes forming a cavity in a substrate, depositing a layer of conductive material in the cavity and over exposed portions of the substrate, removing portions of the conductive material to expose portions of the substrate using a planarizing process, and removing residual portions of the conductive material disposed on the substrate using a reactive ion etch (RIE) process.

Abstract: To improve processing uniformity by improving a working characteristic in an edge exclusion region. Provided is a plasma processing apparatus for processing a sample by generating plasma in a vacuum vessel to which a processing gas is supplied and that is exhausted to a predetermined pressure and by applying a radio frequency bias to a sample placed in the vacuum vessel, wherein a conductive radio frequency ring to which a radio frequency bias power is applied is arranged in a stepped part formed outside a convex part of the sample stage on which the wafer is mounted, and a dielectric cover ring is provided in the stepped part, covering the radio frequency ring, the cover ring substantially blocks penetration of the radio frequency power to the plasma from the radio frequency ring, and the radio frequency ring top surface is set higher than a wafer top surface.

Abstract: The surface morphology of an LED light emitting surface is changed by applying a reactive ion etch (RIE) process to the light emitting surface. Etched features, such as truncated pyramids, may be formed on the emitting surface, prior to the RIE process, by cutting into the surface using a saw blade or a masked etching technique. Sidewall cuts may also be made in the emitting surface prior to the RIE process. A light absorbing damaged layer of material associated with saw cutting is removed by the RIE process. The surface morphology created by the RIE process may be emulated using different, various combinations of non-RIE processes such as grit sanding and deposition of a roughened layer of material or particles followed by dry etching.

Abstract: A method of manufacturing a semiconductor device, which forms a pattern by performing pattern transformation steps multiple times, comprises setting finished pattern sizes for patterns to be formed in each consecutive two pattern transformation steps among the plurality of pattern transformation steps based on a possible total amount of in-plane size variation of the patterns to be formed in the consecutive two pattern transformation steps.

Abstract: The present invention provides an electrostatic deflector which deflects a plurality of charged particle beams, the deflector comprising a first electrode member including a plurality of first electrode pairs arranged along a first axis direction in an oblique coordinate system, and a second electrode member including a plurality of second electrode pairs arranged along a second axis direction in the oblique coordinate system, wherein each of the plurality of charged particle beams is deflected by a corresponding first electrode pair of the plurality of first electrode pairs, and a corresponding second electrode pair of the plurality of second electrode pairs.

Abstract: A method for etching on a semiconductors at the back end of line using reactive ion etching. The method comprises reduced pressure atmosphere and a mixture of gases at a specific flow rate ratio during plasma generation and etching. Plasma generation is induced by a source radio frequency and anisotropic etch performance is induced by a second bias radio frequency.

Abstract: A method and system for fabricating a substrate is disclosed. First, a plurality of process chambers are provided, at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate and at least one of the plurality of process chambers containing a plasma filtering plate library. A plasma filtering plate is selected and removed from the plasma filtering plate library. Then, the plasma filtering plate is inserted into at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate. Subsequently, an etching process is performed in the substrate.

Abstract: A method for etching a conductive layer through a mask with wider and narrower features is provided. A steady state etch gas is flowed. A steady state RF power is provided to form a plasma from the etch gas. A pulsed bias voltage is provided during the steady state etch gas flow, wherein the pulsed bias voltage has a frequency between 1 to 10,000 Hz. Wider and narrower features are etched into the conductive layer using the plasma formed from the etch gas.

Abstract: The invention provides a method of forming a concavo-convex pattern by partly removing a magnetic layer and a carbon protective layer in an intermediate product of a magnetic recording medium having at least the magnetic layer and the protective layer formed on a substrate surface, wherein the magnetic layer is partly removed to form the concavo-convex pattern by a dry etching method using a etching gas of a mixture gas of argon and a deposition gas containing one or more types of carbon compounds. Also disclosed is a method of manufacturing a patterned medium type magnetic recording medium employing the method of forming a concavo-convex pattern. As a result a concavo-convex pattern free of after-corrosion and exhibiting good productivity is provided.

Abstract: Embodiments of the invention may include first providing a stack of layers including a semiconductor substrate, a buried oxide layer on the semiconductor substrate, a semiconductor-on-insulator layer on the buried-oxide layer, a nitride layer on the semiconductor-on-insulator layer, and a silicon oxide layer on the nitride layer. A first opening and second opening with a smaller cross-sectional area than the first opening are then formed in the silicon oxide layer, the nitride layer, the semiconductor-on-insulator layer, and the buried-oxide layer. The first opening and the second opening are then etched with a first etching gas. The first opening and the second opening are then etched with a second etching gas, which includes the first etching gas and a halogenated silicon compound, for example, silicon tetrafluoride or silicon tetrachloride. In one embodiment, the first etching gas includes hydrogen bromide, nitrogen trifluoride, and oxygen.

Abstract: Methods for fabricating TMR and CPP GMR magnetic heads using a chemical mechanical polishing (CMP) process with a patterned CMP conductive protective layer for sensor stripe height patterning. The method comprises defining a stripe height of a read sensor of a magnetic head reader. The method further comprises refill depositing an insulator layer on the read sensor. The method further comprises performing a CMP process down to the conductive protective layer on the read sensor deposited while defining the read sensor to remove an overfill portion of the insulator layer above the conductive protective layer and to remove a sensor pattern masking structure on the conductive protective layer. As a result, the insulator layer is planarized and smooth with the read sensor, eliminating fencing and alumina bumps typically encountered in the insulator layer at the edge of the patterned sensor.

Abstract: The present invention introduces a new technique allowing the fabrication of high-aspect ratio nanoscale semiconductor structures and local device modifications using FIB technology. The unwanted semiconductor sputtering in the beam tail region prevented by a thin slow-sputter-rate layer which responds much slower and mostly to the high-intensity ion beam center, thus acting as a saturated absorber funnel-like mask for the semiconductor. The protective layer can be deposited locally using FIB, thus enabling this technique for local device modifications, which is impossible using existing technology. Furthermore, such protective layers allow much higher resolution and nanoscale milling can be achieved with very high aspect ratios, e.g. Ti layer results in aspect ratio higher than 10 versus bare semiconductor milling ratio of about 3.

Abstract: A method of manufacturing a semiconductor device includes forming an insulating layer over a semiconductor region; forming a multilayer resist composite including a plurality of resist layers over the insulating layer; forming an opening in the resist layers of the multilayer resist composite except in the lowermost resist layer adjacent to the insulating layer; forming a reflow opening in the lowermost resist layer; reflowing part of the lowermost resist layer exposed in the reflow opening by heating to form a slope at the surface of the lowermost resist layer; forming a first gate opening in the lowermost resist layer so as to extend from the slope; and forming a gate electrode having a shape depending on the shapes of the opening in the multilayer resist composite, the slope and the first gate opening.

Abstract: A method for silicon micromachining techniques based on high aspect ratio reactive ion etching with gas chopping has been developed capable of producing essentially scallop-free, smooth, sidewall surfaces. The method uses precisely controlled, alternated (or chopped) gas flow of the etching and deposition gas precursors to produce a controllable sidewall passivation capable of high anisotropy. The dynamic control of sidewall passivation is achieved by carefully controlling fluorine radical presence with moderator gasses, such as CH4 and controlling the passivation rate and stoichiometry using a CF2 source. In this manner, sidewall polymer deposition thicknesses are very well controlled, reducing sidewall ripples to very small levels. By combining inductively coupled plasmas with controlled fluorocarbon chemistry, good control of vertical structures with very low sidewall roughness may be produced.

Abstract: Etching equipment and methods are disclosed herein for more efficient etching of sacrificial material from between permanent MEMS structures. An etching head includes an elongate etchant inlet structure, which may be slot-shaped or an elongate distribution of inlet holes. A substrate is supported in proximity to the etching head in a manner that defines a flow path substantially parallel to the substrate face, and permits relative motion for the etching head to scan across the substrate.

Abstract: A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers.

Abstract: An aspect of the present embodiment, there is provided a method of fabricating a semiconductor device including providing a film to be processed above a semiconductor substrate, providing a negative-type resist and a photo-curable resist in order, pressing a main surface of a template onto the photo-curable resist, the main surface of the template having a concavo-convex pattern with a light shield portion provided on at least a part of a convex portion, irradiating the template with light from a back surface of the template, developing the negative-type resist and the photo-curable resist so as to print the concavo-convex pattern of the template on the negative-type resist and the photo-curable resist, and etching the film to be processed by using the concavo-convex pattern printed on the negative-type resist and the photo-curable resist as a mask.

Abstract: An ashing device and ashing method that can positively remove resist from a wafer while preventing degradation of the film material properties of exposed porous Low-K film on the wafer. The ashing device of the present invention introduces a gas to a dielectric plasma generating chamber 14, excites said gas to generate a plasma, and performs plasma processing using said gas plasma on a processing work S in use of a Low-K film. The ashing gas introduced from a gas regulator 20 is an inert gas to which H2 has been added. The configuration is formed so that plasma is generated from the gas blend, and the resist is removed by the hydrogen radicals generated.

Abstract: This etching method comprises a step for forming an organic compound gas (22) atmosphere around a copper film (101) that has a mask material (102) formed on the surface thereof and a step for using the mask material (102) as a mask on the copper film (101), irradiating with oxygen ions (6), and performing anisotropic etching of the copper film (101) in the organic compound gas (22) atmosphere.

Abstract: A method for selectively etching a substrate is described. The method includes preparing a substrate comprising a silicon nitride layer overlying a silicon-containing contact region, and patterning the silicon nitride layer to expose the silicon-containing contact region using a plasma etching process in a plasma etching system. The plasma etching process uses a process composition having as incipient ingredients a process gas containing C, H and F, and a non-oxygen-containing additive gas, wherein the non-oxygen-containing additive gas includes H, or C, or both H and C, and excludes a halogen atom.

Abstract: The invention provides a method of processing a wafer using Ion Energy (IE)-related multilayer process sequences and Ion Energy Controlled Multi-Input/Multi-Output (IEC-MIMO) models and libraries that can include one or more measurement procedures, one or more IEC-etch sequences, and one or more Ion Energy Optimized (IEO) etch procedures. The IEC-MIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple IEC etch sequences. The multiple layers and/or the multiple IEC etch sequence can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using IEO etch procedures.

Abstract: A method for etching a differential metal gate structure on a substrate is described. The differential metal gate structure includes a metal gate layer overlying a high dielectric constant (high-k) dielectric layer, wherein the metal gate layer comprises a different thickness at different regions on the substrate. The metal gate layer is patterned by using a plasma etching process, wherein at least one etch step includes forming plasma using a halogen-containing gas and at least one etch step includes forming plasma using an additive gas having as atomic constituents C, H, and F.

Abstract: An etching method of etching a periodic pattern formed by self-assembling a first polymer and a second polymer of a block copolymer that is capable of being self-assembled, the etching method includes supplying a high frequency power which is set such that a great amount of ion energy is distributed within a range smaller than ion energy distribution at which an etching yield of the first polymer is generated and larger than or equal to ion energy distribution at which an etching yield of the second polymer is generated, and supplying a predetermined gas, generating plasma from the supplied gas by the high frequency power, and etching the periodic pattern on a processing target object by using the generated plasma.

Abstract: Embodiment of the present invention provides a method of forming electronic fuse or commonly known as e-fuse. The method includes forming a polysilicon structure and a field-effect-transistor (FET) structure together on top of a common semiconductor substrate, the FET structure having a sacrificial gate electrode; implanting at least one dopant into the polysilicon structure to create a doped polysilicon layer in at least a top portion of the polysilicon structure; subjecting the polysilicon structure and the FET structure to a reactive-ion-etching (RIE) process, the RIE process selectively removing the sacrificial gate electrode of the FET structure while the doped polysilicon layer being substantially unaffected by the RIE process; and converting the polysilicon structure including the doped polysilicon layer into a silicide to form the electronic fuse.

Abstract: The described process allows trenches to be etched in a structure comprising a support substrate and a multilayer, formed on the substrate, for the definition of wave guides of an integrated optical device and comprises a selective plasma attack in the multilayer through a masking structure that leaves uncovered areas of the multilayer corresponding to the trenches to be etched. Such a masking structure is obtained by forming a mask of metallic material on the multilayer that leaves uncovered the areas corresponding to the trenches to be etched and forming a mask of non-metallic material, for example photoresist, on it that leaves uncovered regions comprising at least part of the areas and an edge portion of the mask of metallic material.

Abstract: A chemical solution that removes undesired metal hard mask yet remains selective to the device wiring metallurgy and dielectric materials. The present invention decreases aspect ratio by selective removal of the metal hard mask before the metallization of the receiving structures without adverse damage to any existing metal or dielectric materials required to define the semiconductor device, e.g. copper metallurgy or device dielectric. Thus, an improved aspect ratio for metal fill without introducing any excessive trapezoidal cross-sectional character to the defined metal receiving structures of the device will result.

Abstract: A manufacturing method of a semiconductor device includes: forming step of forming an etching mask on a second main face of a substrate, the etching mask being made of Cu or Cu alloy and having an opening, the second main face being on an opposite side of a first main face of the substrate where a nitride semiconductor layer is provided; a first etching step of applying a dry etching to the second main face of the substrate with use of the etching mask so that all of or a part of the nitride semiconductor layer is left; a removing step of removing the etching mask after the first etching step; and a second etching step of dry-etching the left nitride semiconductor layer after the removing step.

Abstract: A top plate assembly is positioned above and spaced apart from the substrate support, such that a processing region exists between the top plate assembly and the substrate support. The top plate assembly includes a central plasma generation microchamber and a plurality of annular-shaped plasma generation microchambers positioned in a concentric manner about the central plasma generation microchamber. Adjacently positioned ones of the central and annular-shaped plasma generation microchambers are spaced apart from each other so as to form a number of axial exhaust vents therebetween. Each of the central and annular-shaped plasma generation microchambers is defined to generate a corresponding plasma therein and supply reactive constituents of its plasma to the processing region between the top plate assembly and the substrate support.

Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can form a plurality of grooves extending in a first direction on a semiconductor substrate. The method can form an insulating layer on the inner face of the groove and on the top face of the semiconductor substrate. The method can deposit a first conductive layer on the insulating layer so as to fill in the groove. The method can deposit a second conductive layer on the first conductive layer. The method can form a hard mask in a region including part of a region immediately above the groove on the second conductive layer. The method can form a columnar body including the hard mask and the second conductive layer by etching the second conductive layer using the hard mask as a mask.

Abstract: A method and system for etching a substrate is described and, in particular, a method for etching large, high aspect ratio features, such as those in micro-electromechanical devices (MEMs), is also described. The method comprises disposing a substrate in a processing system, forming plasma having a substantial population of negatively-charged ions, and etching one or more features in the substrate using the negative ion population.

Abstract: In a process for forming trenches having M different widths in a substrate, a passivation step and an etching step are alternately performed. The passivation step includes depositing a passivation layer on a bottom of the trenches by converting gas introduced in a chamber into plasma. The etching step includes removing the passivation layer on the bottom of the trenches and applying reactive ion etching to the bottom to increase a depth of the trenches. The etching step further includes setting energy for the reactive ion etching to a predetermined value when the passivation layer on the bottom of the trench having the Nth smallest width is removed. The value allows the etching amount of the trench having the Nth smallest width to be equal to or greater than the etching amount of the trench having the (N+1)th smallest width.

Abstract: A method for fabricating magnetic transducer is described. The method includes providing a main pole having a bottom and a top wider than the bottom. The method further includes performing a high energy ion mill at an angle from a normal to the to of the main pole and at a first energy. The high energy ion mill removes a portion of the top of the main pole and exposes a top bevel surface for the main pole. The method also includes performing a low energy ion mill at second energy and a glancing angle from the top bevel surface. The glancing angle is not more than fifteen degrees. The second energy is less than the first energy. The method and system also include depositing a nonmagnetic gap.

Abstract: In one non-limiting exemplary embodiment, a method includes: providing a structure having at least one lithographic layer on a substrate, where the at least one lithographic layer includes a planarization layer (PL); forming a sacrificial mandrel by patterning at least a portion of the at least one lithographic layer using a photolithographic process, where the sacrificial mandrel includes at least a portion of the PL; and producing at least one microstructure by using the sacrificial mandrel in a sidewall image transfer process.

Abstract: There is provided a fin transistor structure and a method of fabricating the same. The fin transistor structure comprises a fin formed on a semiconductor substrate, wherein a bulk semiconductor material is formed between a portion of the fin serving as the channel region of the transistor structure and the substrate, and an insulation material is formed between remaining portions of the fin and the substrate. Thereby, it is possible to reduce the current leakage while maintaining the advantages of body-tied structures.

Abstract: An inspection method comprises focusing a particle beam onto a sample; operating at least one detector located close to the sample; assigning detection signals generated by the at least one detector to different intensity intervals; determining, based on the detection signals assigned to the intensity intervals, at least one first signal component related to electrons incident on the detector; and determining, based on the detection signals assigned to the intensity intervals, at least one second signal component related to X-rays incident on the detector.

Abstract: There is provided a fin transistor structure and a method of fabricating the same. The fin transistor structure comprises a fin formed on a semiconductor substrate, wherein an insulation material is formed between a portion of the fin serving as the channel region of the transistor structure and the substrate, and a bulk semiconductor material is formed between remaining portions of the fin and the substrate. Thereby, it is possible to reduce the current leakage while maintaining the advantages such as low cost and high heat transfer.

Abstract: Methods and apparatus for performing end point determination. A method includes receiving a wafer into an etch tool chamber for performing an RIE etch; beginning the RIE etch to form vias in the wafer; receiving in-situ measurements of one or more physical parameters of the etch tool chamber that are correlated to the RIE etch process; providing a virtual metrology model for the RIE etch in the chamber; inputting the received in-situ measurements to the virtual metrology model for the RIE etch in the chamber; executing the virtual metrology model to estimate the current via depth; comparing the estimated current via depth to a target depth; and when the comparing indicates the current via depth is within a predetermined threshold of the target depth; outputting a stop signal. An apparatus for use with the method embodiment is disclosed.

Abstract: A method for amorphizing a layer on a substrate is described. In one embodiment, the method includes treating the substrate with a first gas cluster ion beam (GCIB) using a first beam energy selected to yield an amorphous sub-layer within the substrate of a desired thickness, which produces a first interfacial roughness of an amorphous-crystal interface between the amorphous sub-layer and a crystalline sub-layer of the substrate. The method further includes treating the substrate with a second GCIB using a second beam energy, less than the first beam energy, to reduce the first interfacial roughness of the amorphous-crystal interface to a second interfacial roughness.

Abstract: Methods of processing substrates having metal layers are provided herein. In some embodiments, a method of processing a substrate comprising a metal layer having a patterned mask layer disposed above the metal layer, the method may include etching the metal layer through the patterned mask layer; and removing the patterned mask layer using a first plasma formed from a first process gas comprising oxygen (O2) and a carbohydrate. In some embodiments, a two step method with an additional second process gas comprising chlorine (Cl2) or a sulfur (S) containing gas, may provide an efficient way to remove patterned mask residue.

Abstract: Methods are provided for cleaning metal regions overlying semiconductor substrates. A method for removing material from a metal region comprises heating the metal region, forming a plasma from a gas comprising hydrogen and carbon dioxide, and exposing the metal region to the plasma.

Abstract: An apparatus and method are provided which allow the low cost patterned deposition of material onto a workpiece. A stencil mask, having chamfered edges is applied to the surface of the workpiece. The material is then deposited onto the workpiece, such as by PECVD. Because of the chamfered edges, the material thickness is much more uniform than is possible with traditional stencil masks. Stencil masks having a variety of cross sectional patterns are disclosed which improve deposition uniformity.

Abstract: In anisotropic etching of the substrates, ultra-thin and conformable layers of materials can be used to passivate sidewalls of the etched features. Such a sidewall passivation layer may be a Self-assembled monolayer (SAM) material deposited in-situ etching process from a vapor phase. Alternatively, the sidewall passivation layer may be an inorganic-based material deposited using Atomic Layer Deposition (ALD) method. SAM or ALD s layer deposition can be carried out in a pulsing regime alternating with sputtering and/or etching processes using process gasses with or without plasma. Alternatively, SAM deposition is carried out continuously, while etch or sputtering turns on in a pulsing regime. Alternatively, SAM deposition and etch or sputtering may be carried out continuously.

Abstract: An optimum application voltage for reducing deposits on a peripheral portion of a substrate as well as improving a process result in balance is effectively found without changing a height of a focus ring. A plasma processing apparatus includes a focus ring which includes a dielectric ring provided so as to surround a substrate mounting portion of a mounting table and a conductive ring provided on the dielectric ring; a voltage sensor configured to detect a floating voltage of the conductive ring; a DC power supply configured to apply a DC voltage to the conductive ring. An optimum voltage to be applied to the conductive ring is obtained based on a floating voltage actually detected from the conductive ring, and the optimum application voltage is adjusted based on a variation in the actually detected floating voltage for each plasma process.

Abstract: A plasma ashing method is used for removing a patterned resist film in a processing chamber after etching a portion of a low-k film from an object to be processed in the processing chamber by using the patterned resist film as a mask. The method includes a first step of supplying a reaction product removal gas including at least CO2 gas into the processing chamber, generating plasma of the reaction product removal gas by applying a high frequency power for the plasma generation, and removing reaction products deposited on an inner wall of the processing chamber; and a second step of supplying an ashing gas into the processing chamber, generating plasma of the ashing gas by applying a high frequency power for the plasma generation, and removing the resist film.

Abstract: A method for fabricating integrated circuit is provided. First, a substrate having a micro electromechanical system (MEMS) region is provided. A first interconnect structure and a hard mask layer have been disposed on the MEMS region in sequence. Next, an anisotropic etching process is performed by using the hard mask layer as a photo mask to etch a portion of the first interconnect structure exposed by the hard mask layer. Accordingly, a MEMS structure is formed. A portion of the substrate in MEMS region is exposed by the MEMS structure. Then, an isotropic etching process is performed for removing the portion of the substrate in MEMS region to form a cavity with a center region and a ring-like indentation region. The center region is surrounded by the ring-like indentation region and the MEMS structure suspends above the cavity. An integrated circuit is also provided.

Abstract: A semiconductor device is accepted at a stage of its fabrication, at which stage the device includes a diffusion-barrier cap-material (DBCM) layer and an intermetal dielectric layer covering the DBCM layer. The DBCM layer is exposed and it is suitable for removal by an etching procedure in a portion of a pattern contained in the intermetal dielectric layer. A silylation treatment is performed on the semiconductor device prior to the etching procedure for removing the DBCM layer. The intermetal dielectric layer of the completed device has surfaces in contact with metal interconnects and metal vias, and it may have an excess of carbon content near at least a portion of the these surfaces.