Abstract: A substrate processing method that can selectively remove deposit produced through dry etching of silicon. A substrate has a silicon base material and a hard mask that is made of a silicon nitride film and/or a silicon oxide film and formed on the silicon base material, the hard mask having an opening to which at least part of the silicon base material is exposed. A trench corresponding to the opening is formed in the silicon base material through dry etching using plasma produced from halogenated gas. After the dry etching, the substrate is heated to a temperature of not less than 200° C., and then hydrogen fluoride gas and helium gas are supplied toward the substrate.

Abstract: A process for selectively etching a material comprising SiO2 over silicon, the method comprising the steps of: placing a silicon substrate comprising a layer of a material comprising SiO2 within a reactor chamber equipped with an energy source; creating a vacuum within the chamber; introducing into the reactor chamber a reactive gas mixture comprising a fluorine compound, a polymerizable fluorocarbon, and an inert gas, wherein the reactive gas mixture is substantially free of added oxygen; activating the energy source to form a plasma activated reactive etching gas mixture within the chamber; and selectively etching the material comprising SiO2 preferentially to the silicon substrate.

Abstract: The present application discloses a method for manufacturing a gate-all-around field effect transistor, comprising the steps of: forming a suspended fin in a semiconductor substrate; forming a gate stack around the fin; and forming source/drain regions in the fin on both sides of the gate stack, wherein an isolation dielectric layer is formed in a portion of the semiconductor substrate which is adjacent to bottom of both the fin and the gate stack. The present invention relates to a method for manufacturing a gate-all-around device on a bulk silicon substrate, which suppress a self-heating effect and a floating-body effect of the SOI substrate, and lower a manufacture cost. The inventive method is a conventional top-down process with respect to a reference plane, which can be implemented as a simple manufacture process, and is easy to be integrated into and compatible with a planar CMOS process. The inventive method suppresses a short channel effect and promotes miniaturization of MOSFETs.

Abstract: A transfer process for silicon nanomembranes (SiNM) may involve treating a recipient substrate with a polymer structural support. After treating the recipient substrate, a substrate containing the intended transferable devices may be brought in direct contact with the aforementioned polymer layer. The two substrates may then go through a Deep Reactive Ion Etch (DRIE) to remove at least a portion of the substrate containing the devices. Oxide may be selectively removed with a buffered oxide wet etch, leaving the transferred SiNM on the recipient substrate with the Underlying polymer layer.

Abstract: According to one embodiment, a semiconductor device manufacturing method comprises mounting a supporting substrate on a front surface side of a silicon substrate having an interconnection layer and function elements formed on a front surface side, polishing a back surface side of the silicon substrate, forming a mask having an opening and an opening for a dummy hole having a diameter smaller than that of the above opening on the back surface side of the silicon substrate, etching portions exposed to the openings of the mask from the back surface side of the silicon substrate to form a via hole that reaches a part of the interconnection layer and form a dummy hole to an intermediate portion of the silicon substrate, and forming an interconnection material in the via hole.

Abstract: A method for reducing line width roughness (LWR) of a feature in an etch layer below a patterned photoresist mask having mask features is provided. The method includes (a) non-etching plasma pre-etch treatment of the photoresist mask, and (b) etching of a feature in the etch layer through the pre-treated photoresist mask using an etching gas. The non-etching plasma pre-etch treatment includes (a1) providing a treatment gas containing H2 and COS, (a2) forming a plasma from the treatment gas, and (a3) stopping the treatment gas.

Abstract: A scanning probe where the micromachined pyramid tip is extended by the growth of an epitaxial nanowire from the top portion of the tip is disclosed. A metallic particle, such as gold, may terminate the nanowire to realize an apertureless near-field optical microscope probe.

Abstract: A process for fabricating AlGaInN-based photonic devices, such as lasers, capable of emitting blue light employs etching to form device waveguides and mirrors, preferably using a temperature of over 500° C. and an ion beam in excess of 500 V in CAIBE.

Abstract: A method for capping lines includes forming a metal film layer on a copper line by a selective deposition process, the copper line disposed in a dielectric substrate, wherein the depositing also results in the deposition of stray metal material on the surface of the dielectric substrate, and etching with an isotropic etching process to remove a portion of the metal film layer and the stray metal material on the surface of the dielectric substrate, wherein the metal film layer is deposited at an initial thickness sufficient to leave a metal film layer cap remaining on the copper line following the removal of the stray metal material.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The method includes the following steps. Firstly, a semiconductor substrate having an active surface and a back surface is provided. The active surface is opposite to the back surface, and the semiconductor substrate includes at least one grounding pad disposed on the active surface. Secondly, at least one through silicon via is formed through the semiconductor substrate from the back surface to the active surface thus exposing the grounding pad. Then, a conductive layer is formed on the back surface of the semiconductor substrate and filled into the through silicon via to electrically connect to the grounding pad and the semiconductor substrate.

Abstract: MEMS devices (40) using etched cavities (42) are desirably formed using multiple etching steps. Preliminary cavities (20) formed by locally anisotropic etching to nearly the final depth have irregular (46) sidewalls (44) and steep and/or inconsistent sidewall (44) to bottom (54) intersection angles (48). This leads to less than desired cavity diaphragm (26) burst strengths. Final cavities (42) with smooth sidewalls (50), smaller and consistent sidewall (50) to bottom (54) intersection angles (58), and having more than doubled cavity diaphragm (26) burst strengths are obtained by treating the preliminary cavities (20) with TMAH etchant, preferably relatively dilute TMAH etchant. In a preferred embodiment, a cleaning step is performed between the etching step and the TMAH treatment step to remove any anisotropic etching by-products present on the preliminary cavities' (20) initial sidewalls (44).

Abstract: A field effect transistor device includes a gate stack portion disposed on a substrate, and a channel region in the substrate having a depth partially defined by the gate stack portion and a silicon region of the substrate, the silicon region having a sloped profile such that a distal regions of the channel region have greater depth than a medial region of the channel region.

Abstract: A manufacturing process technology creates a pattern on a first layer using a focused ion beam process. The pattern is transferred to a second layer, which may act as a traditional etch stop layer. The pattern can be formed on the second layer without irradiation by light through a reticle and without wet chemical developing, thereby enabling conformal coverage and very fine critical feature control. Both dark field patterns and light field patterns are disclosed, which may enable reduced or minimal exposure by the focused ion beam.

Abstract: A method for manufacturing a magnetoresistive sensor having improved pinned layer stability at small track widths. The method includes providing a substrate, and depositing a plurality of sensor layers. A layer of material that is resistant to removal by chemical mechanical polishing (CMP stop layer) and an antireflective coating layer are deposited. A photoresist mask is formed on the antireflective layer, and a reactive ion etch (RIE) is performed to remove portions of the ion mill resistant mask that are not covered by the photoresist mask, the RIE being performed in a plasma chamber having a platen, the performing the RIE further comprising applying a platen power of at least 70 W. An ion milling is performed to remove a portion of the sensor layers, the ion milling being terminating before all of the sensor materials have been removed.

Abstract: Methods of forming a write pole are disclosed. A first photomask having a first opening over one of a yoke region and a pole tip region of the write pole is formed over an insulation layer having an insulator material. A first etch process is performed on the insulation layer via the first opening, the first etch process removing the insulator material from a corresponding one of the yoke region and the pole tip region. A second photomask having a second opening over the other one of the yoke region and the pole tip region is formed over the insulation layer. A second etch process is performed on the insulation layer via the second opening, the second etch process removing the insulator material from a corresponding one of the yoke region and the pole tip region.

Abstract: A method of removing at least a portion of a silicon oxide material is disclosed. The silicon oxide is removed by exposing a semiconductor structure comprising a substrate and the silicon oxide to an ammonium fluoride chemical treatment and a subsequent plasma treatment, both of which may be effected in the same vacuum chamber of a processing apparatus. The ammonium fluoride chemical treatment converts the silicon oxide to a solid reaction product in a self-limiting reaction, the solid reaction product then being volatilized by the plasma treatment. The plasma treatment includes a plasma having an ion bombardment energy of less than or equal to approximately 20 eV. An ammonium fluoride chemical treatment including an alkylated ammonia derivative and hydrogen fluoride is also disclosed.

Abstract: Disclosed herein is a method for manufacturing a micro-electromechanical structure. The method includes the following steps. A circuitry layer having a release feature is formed on an upper surface of a first substrate. A passive layer is formed on the circuitry layer without covering the release feature. The release feature is removed to expose the first substrate by a wet etching process. A portion of the exposed first substrate is anisotropically etched. A second substrate is disposed above the circuitry layer. A cavity is formed in the lower surface of the first substrate. The cavity is filled with a polymeric material. A portion of the first substrate under the microstructure is removed to release the micro-electromechanical structure.

Abstract: A method for manufacturing a semiconductor structure comprising complementary bipolar transistors, wherein for manufacture of a PNP-type structure, an emitter layer having a surface oxide layer is present on top of an NPN-type structure, the emitter layer comprising lateral and vertical surfaces, and wherein for removal of the oxide layer, an ion etching step is applied, wherein for the on etching step a plasma for providing ions is generated in a vacuum chamber by RF coupling and the generated ions are accelerated by an acceleration voltage between the plasma and a wafer comprising the semiconductor structure, and wherein the plasma generation and the ion acceleration are controlled independently from each other

Abstract: There is provided a plasma processing apparatus capable of optimizing a plasma process in response to various requirements of a micro processing by effectively controlling a RF bias function. In this plasma processing apparatus, a high frequency power RFH suitable for generating plasma of a capacitively coupling type is applied to an upper electrode 48 (or lower electrode 16) from a third high frequency power supply 66, and two high frequency powers RFL1 (0.8 MHz) and RFL2 (13 MHz) suitable for attracting ions are applied to the susceptor 16 from first and second high frequency power supplies 36 and 38, respectively, in order to control energy of ions incident onto a semiconductor wafer W from the plasma. A control unit 88 controls a total power and a power ratio of the first and second high frequency powers RFL1 and RFL2 depending on specifications, conditions or recipes of an etching process.

Abstract: A process is disclosed for sectioning by etching of monolayers and multilayers using an RIE technique with fluorine-based chemistry. In one embodiment, the process uses Reactive Ion Etching (RIE) alone or in combination with Inductively Coupled Plasma (ICP) using fluorine-based chemistry alone and using sufficient power to provide high ion energy to increase the etching rate and to obtain deeper anisotropic etching. In a second embodiment, a process is provided for sectioning of WSi2/Si multilayers using RIE in combination with ICP using a combination of fluorine-based and chlorine-based chemistries and using RF power and ICP power. According to the second embodiment, a high level of vertical anisotropy is achieved by a ratio of three gases; namely, CHF3, Cl2, and O2 with RF and ICP. Additionally, in conjunction with the second embodiment, a passivation layer can be formed on the surface of the multilayer which aids in anisotropic profile generation.

Abstract: Many current micromachining devices are integrated with materials such as very thick layer of polyimide (10 to 100 um) to offer essential characteristics and properties for various applications; it is inherently difficult and complicated to provide reliable metal interconnections between different levels of the circuits. The present invention is generally related to a novel micromachining process and structure to form metal interconnections in integrated circuits or micromachining devices which are incorporated with thick polyimide films. More particularly, the embodiments of the current invention relates to formation of multi-step staircase structure with tapered angle on polyimide layer, which is therefore capable of offering superb and reliable step coverage for metallization among different levels of integrated circuits, and especially for very thick polyimide layer applications.

Abstract: A method of pattern etching a Si-containing anti-reflective coating (ARC) layer is described. The method comprises etching a feature pattern into the silicon-containing ARC layer using plasma formed from a process gas containing SF6 and a hydrocarbon gas. The method further comprises adjusting a flow rate of the hydrocarbon gas relative to a flow rate of the SF6 to reduce a CD bias between a final CD for nested structures in the feature pattern and a final CD for isolated structures in the feature pattern.

Abstract: A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.

Abstract: Methods for producing self-aligned, self-assembled sub-ground-rule features without the need to use additional lithographic patterning. Specifically, the present disclosure allows for the creation of assist features that are localized and self-aligned to a given structure. These assist features can either have the same tone or different tone to the given feature.

Abstract: In a substrate processing method of processing a substrate that includes an oxide layer as a mask layer and a silicon layer as a target layer to be processed, the silicon layer is etched while depositing a deposit on a surface of the oxide layer by a plasma generated from a mixed gas of a fluorine-based gas, a bromine-based gas, O2 gas, and SiCl4 gas to secure a thickness of the mask layer.

Abstract: A method for producing an electrically conductive connection between a first surface of a semiconductor substrate and a second surface of the semiconductor substrate includes producing a hole, forming an electrically conductive layer that includes tungsten, removing the electrically conductive layer from the first surface of the semiconductor substrate, filling the hole with copper and thinning the semiconductor substrate. The hole is produced from the first surface of the semiconductor substrate into the semiconductor substrate. The electrically conductive layer is removed from the first surface of the semiconductor substrate, wherein the electrically conductive layer remains at least with reduced thickness in the hole. The semiconductor substrate is thinned starting from a surface, which is an opposite surface of the first surface of the semiconductor substrate, to obtain the second surface of the semiconductor substrate with the hole being uncovered at the second surface of the semiconductor substrate.

Abstract: A micromachined sensor for measuring vascular parameters, such as fluid shear stress, includes a substrate having a front-side surface, and a backside surface opposite the front-side surface. The sensor includes a diaphragm overlying a cavity etched within the substrate, and a heat sensing element disposed on the front-side surface of the substrate and on top of the cavity and the diaphragm. The heat sensing element is electrically couplable to electrode leads formed on the backside surface of the substrate. The sensor includes an electronic system connected to the backside surface and configured to measure a change in heat convection from the sensing element to surrounding fluid when the sensing element is heated by applying an electric current thereto, and further configured to derive from the change in heat convection vascular parameters such as the shear stress of fluid flowing past the sensing element.

Abstract: A method for manufacturing a magnetoresistive read sensor that allows the sensor to be constructed with clean well defined side junctions, even at very narrow track widths. The method involves using first and second etch mask layers, that are constructed of materials such that the second mask (formed over the first mask) can act as a mask during the patterning of the first mask (bottom mask). The first mask has a well defined thickness that is defined by deposition and which is not affected by the etching processes used to define the mask. This allows the total ion milling etch mask thickness to be well controlled before the ion milling process used to define the sensor side walls.

Abstract: The invention provides a method for forming a via. A first dielectric layer is formed on a substrate. A conductive structure is formed in the first dielectric layer. A second dielectric layer is formed on the first dielectric layer and conductive structure. A first etching step is performed by using a first etching mixture to form a first via in the second dielectric layer. A second etching step is performed by using a second etching mixture to form a second via under the first via. The second via exposes at least a top surface of the conductive structure. An etching rate of the second etching step is slower than the first etching step.

Abstract: A method of patterning a metal layer includes forming a first mask on a surface of the metal layer, the first mask having an opening through the first mask that exposes the metal layer, and forming a nanogap in the exposed metal layer using an ion beam directed through the opening. The first mask limits a lateral extent of the ion beam, and the nanogap has a width that is less than a width of the opening.

Abstract: The present application discloses provides a method for planarizing an interlayer dielectric layer, comprising the steps of: providing a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack, performing a first RIE on the multilayer structure, in which a reaction chamber pressure is controlled in such a manner that an etching rate of the portion of the at least one sacrificial layer at a center of a wafer is higher than that at an edge of the wafer, so as to obtain a concave etching profile; performing a second RIE on the multilayer structure to completely remove the sacrificial layer and a part of the insulating layer, so as to obtain the insulating layer having a planar surface which serves as an interlayer dielectric layer.

Abstract: Methods of forming p-channel MOSFETs use halo-implant steps that are performed relatively early in the fabrication process. These methods include forming a gate electrode having first sidewall spacers thereon, on a semiconductor substrate, and then forming a sacrificial sidewall spacer layer on the gate electrode. A mask layer then patterned on the gate electrode. The sacrificial sidewall spacer layer is selectively etched to define sacrificial sidewall spacers on the first sidewall spacers, using the patterned mask layer as an etching mask. A PFET halo-implant of dopants is then performed into portions of the semiconductor substrate that extend adjacent the gate electrode, using the sacrificial sidewall spacers as an implant mask. Following this implant step, source and drain region trenches are etched into the semiconductor substrate, on opposite sides of the gate electrode. These source and drain region trenches are then filled by epitaxially growing SiGe source and drain regions therein.

Abstract: Systems and methods for improving surface reflectance of silicon wafers are disclosed. The systems and methods improve surface reflectance by forming a textured surface on the silicon wafer by performing surface oxidation and dry etching processes. The surface oxidation maybe performed using a dry oxygen plasma process. A dry etch process is performed to remove the oxide layer formed by the surface oxidation step and etch the Silicon layer with oxide masking. Dry etching enables black silicon formation, which minimizes or eliminates light reflection or scattering, eventually leading to higher energy conversion efficiency.

Abstract: Methods of manufacturing semiconductor devices and methods of optical proximity correction methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device, and adjusting a size of at least one pattern for a feature of the material layer by an adjustment amount to partially compensate for the amount of RIE lag determined.

Abstract: Apparatus, devices, and methods for increasing the ion energy in a plasma processing devices are provided. In various embodiments, the surface area of a showerhead facing the work piece includes a plurality of features. The plurality of features increases the surface area of the showerhead relative to a flat surface. Increasing the surface area of the showerhead increases the ion energy without increasing the power used to generate the plasma. Increasing the ion energy using such a showerhead allows for the broader application of plasma processes in integrated circuit manufacturing.

Abstract: A method for etching high-aspect-ratio features is disclosed. The method is applicable in forming a nanoscale deep trench having a smooth and angle-adjustable sidewall. The method includes: forming a patterned photoresist layer on a surface of a silicon substrate for exposing a part of the silicon substrate; and supplying a process gas simultaneously containing sulfur hexafluoride (SF6) and fluorinated carbon composition into a chamber in which the substrate in positioned for carrying out a deep reactive ion etching operation to etch the part of the silicon substrate for forming the deep trench. The method forms a nanoscale deep trench with a high silicon-to-photoresist etching selectivity.

Abstract: A method of processing semiconductor wafers includes applying reactive gas through a plurality of inlets to the semiconductor wafers. The method further includes removing exhaust gas resulting from the step of applying reactive gas. The removing of the exhaust gas is through a plurality of outlets coupled to a manifold. The manifold combines the exhaust gas from the plurality of outlets. The method further includes measuring a pressure in each outlet of the plurality of outlets during the step of removing.

Abstract: Patterning-induced damage of sensitive low-k dielectric materials in semiconductors devices may be restored to a certain degree on the basis of a surface treatment that is performed prior to exposing the device to ambient atmosphere. To this end, the dangling silicon bonds of the silicon oxide-based low-k dielectric material may be saturated in a confined process environment, thereby providing superior surface conditions for the subsequent application of an appropriate repair chemistry.

Abstract: A process including forming a silicon layer over a semiconductor wafer having features thereon and then selectively ion implanting in the silicon layer to form ion implanted regions. The step of selectively ion implanting is repeated as many times as necessary to obtain a predetermined number and density of features. Thereafter, the silicon layer is etched to form openings in the silicon layer that were formerly occupied by the ion implanted regions. The opened areas in the silicon layer form a mask for further processing of the semiconductor wafer.

Abstract: A method for manufacturing an LD is disclosed. The LD has a striped structure including an optical active region. The striped structure is buried with resin, typically benzo-cyclo-butene (BCB). The method to form an opening in the BCB layer has tri-steps etching of the RIE. First step etches the BCB layer partially by a mixed gas of CF4 and O2, where CF4 has a first partial pressure, second step etches the photo-resist patterned on the top of the BCB layer by a mixed gas of CF4 and O2, where CF4 in this step has the second partial pressure less than the first partial pressure, and third step etches the BCB left in the first step by mixed gas of CF4 and O2, where CF4 in this step has the third partial pressure greater than the second partial pressure.

Abstract: A method for manufacturing an ion implantation mask is disclosed which includes the steps of: forming an oxide film as a protective film over the entire surface of a semiconductor substrate; forming a thin metal film over the oxide film; and forming an ion-inhibiting layer composed of an ion-inhibiting metal over the thin metal film. The obtained ion implantation mask is used to form a deeper selectively electroconductive region.

Abstract: The patterns (or layout), and pattern densities of TSVs described above provide layout of TSVs that could be etched with reduced etch microloading effect(s) and with good within-die uniformity. The patterns and pattern densities of TSVs for different groups of TSVs (or physically separated groups, or groups with different functions) should be fairly close amongst different groups. Different groups of TSVs (or TSVs with different functions, or physically separated TSV groups) should have relatively close shapes, sizes, and depths to allow the aspect ratio of all TSVs to be within a controlled (and optimal) range. The size(s) and depths of TSVs should be carefully selected to optimize the etching time and the metal gap-fill time.

Abstract: A method for controlling striations and CD loss in a plasma etching method is disclosed. During the etching process, the substrate of semiconductor material to be etched is exposed first to plasma under a low power strike and subsequently to a conventional high power strike. CD loss has been found to be reduced by about 400 Angstroms and striations formed in the contact holes are reduced.

Abstract: There is provided a substrate processing method capable of preventing the decrease in etching efficiency by positive ions and increasing the overall etching efficiency by using negative ions. The substrate processing method includes applying a plasma RF and a bias RF in the pattern of a pulse wave, respectively. The substrate processing method repeatedly performs the steps of: (3b) etching a substrate by positive ions in plasma by applying both the plasma RF and the bias RF; (3c) generating negative ions in a processing chamber by stopping the application of both the plasma RF and the bias RF; and (3a) attracting the negative ions to the substrate by applying the bias RF and stopping the application of the plasma RF. A duty ratio of the bias RF is set to be greater than a duty ratio of the plasma RF.

Abstract: A layer stack of different materials is deposited on a substrate in a single plasma enhanced chemical vapor deposition processing chamber while maintaining a vacuum. A substrate is placed in the processing chamber and a first processing gas is used to form a first layer of a first material on the substrate. A plasma purge and gas purge are performed before a second processing gas is used to form a second layer of a second material on the substrate. The plasma purge and gas purge are repeated and the additional layers of first and second materials are deposited on the layer stack.

Abstract: Methods for creating at least one micro-electromechanical (MEMS) structure in a silicon-on-insulator (SOI) wafer. The SOI wafer with an extra layer of oxide is etched according to a predefined pattern. A layer of oxide is deposited over exposed surfaces. An etchant selectively removes the oxide to expose the SOI wafer substrate. A portion of the SOI substrate under at least one MEMS structure is removed, thereby releasing the MEMS structure to be used in the formation of an accelerometer.

Abstract: [Problem to be Solved] In a plasma processing apparatus for executing a process using plasma, promoting the sharing of an apparatus in executing a plurality of different processes and plasma states amongst apparatuses in executing same processes in a plurality of apparatuses are provided. [Solution] A ring member formed of an insulating material is disposed to surround a to-be-treated substrate in a processing vessel and an electrode is installed in the ring member for adjusting a plasma sheath region. For example, a first DC voltage is applied to the electrode when a first process is performed on the to-be-treated substrate and a second DC voltage is applied to the electrode when a second process is performed on the to-be-treated substrate. In this case, the plasma state can be matched by applying an appropriate DC voltage according to each process or each apparatus executing the same process. Therefore, the sharing of an apparatus can be promoted and the plasma state can be readily adjusted.

Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes depositing a gate material over a semiconductor substrate, and depositing a first resist layer over the gate material. A first mask is used to pattern the first resist layer to form first and second resist features. The first resist features include pattern for gate lines of the semiconductor device and the second resist features include printing assist features. A second mask is used to form a resist template; the second mask removes the second resist features.

Abstract: Disclosed herein is a method for manufacturing a micro-electromechanical structure. The method includes the following steps. A circuitry layer having a release feature is formed on an upper surface of a first substrate. A passive layer is formed on the circuitry layer without covering the release feature. The release feature is removed to expose the first substrate by a wet etching process. A portion of the exposed first substrate is anisotropically etched. A second substrate is disposed above the circuitry layer. A cavity is formed in the lower surface of the first substrate. The cavity is filled with a polymeric material. A portion of the first substrate under the microstructure is removed to release the micro-electromechanical structure.

Abstract: To fabricate high aspect ratio metal structures, a two-layer structure is provided on a conductive layer. The two-layer structure includes a first layer adjacent the conductive layer and a second layer adjacent the first layer where the second layer is etchable by a Deep Reactive Ion Etching (DRIE) process. Using the DRIE process, at least one selected region of the second layer is completely etched away with the selected region being at least partially aligned with a region of the conductive layer such that the first layer is then exposed thereover. The first layer so-exposed is then removed to expose the region of the conductive layer thereunder. Metal is electroplated onto the exposed conductive layer and any remaining portions of the two-layer structure are then removed.