Abstract: A method for utilizing interference fringe patterns generated when milling a trench through a semiconductor substrate by a method such as FIB milling, to determine and optimize the thickness uniformity of the trench bottom. The interference fringes may be mapped and the mapping used to direct the FIB milling to those regions which are thicker to correct observed non-uniformities in the trench floor thickness by varying the pixel dwell time across the milled area. The interference fringe mapping may be used to develop computerized contour lines to automate the pixel dwell time variations as described above, for correcting non-uniformities in the trench floor thickness. The method may be applied to applications other than trench formation for backside editing, such as monitoring progress in forming a milled object.

Abstract: Methods are provided for delineating different layers and interfaces for inspection of a semiconductor wafer, wherein a sectioned portion of a wafer is subjected to a reactive ion etch process before inspection using a scanning electron microscope.

Abstract: Disclosed a method for dry etching a semiconductor wafer by a plasma generated between a power-supplied first electrode and a grounded second electrode. After the bottom surface of the edge of the wafer is in contact with the first electrode, and the top surface of the edge and the side surface of the wafer are etched by ionized plasma species generated by the plasma discharge of reactive ion etching. Then, after the upper surface of the edge of the wafer is in contact with the second electrode, and the bottom surface of the edge and the side surface of the wafer are etched by radicalized plasma species generated by the plasma discharge of plasma etching.

Abstract: A method of etching high dielectric constant materials using a halogen gas, a reducing gas and an etch rate control gas chemistry.

Abstract: The present invention relates to a semiconductor device in which an electrode of a device formed on a substrate such as a semiconductor wafer and an electrode of a wiring structure such as an interposer are connected to each other through a connecting electrode extending through the substrate, and a method of manufacturing the same. A semiconductor device according to the present invention includes a first substrate including a front surface and a back surface, a first device having a first electrode being formed on the front surface; and a wiring structure formed with a second electrode, the wiring structure having a principal surface. The first electrode of the first device and the second electrode of the wiring structure are connected to each other by a connecting electrode extending through the first substrate from the front surface to the back surface thereof. Substantially all the back surface of the first substrate is bonded to the principal surface of the wiring structure.

Abstract: A method of dry plasma etching a semiconductor structure (20), having at least one semiconductor material layer (21), on a semiconductor wafer (200), involving a dry plasma reaction gas mixture (30i) being chemically selected for, and having an etch rate corresponding to, each semiconductor material layer (21); dividing the semiconductor structure (20) into a masked portion (23a) and an unmasked portion (23b); and sequentially exposing the unmasked portion (23b) of the semiconductor structure (20) to the dry plasma reaction gas mixture (30i).

Abstract: A method of producing a device for simultaneously carrying out an electrochemical and a topographical near field microscopy is disclosed, which is characterized in that a probe suitable for topographic near field microscopy is covered by a conductive material, the conductive material is covered by an insulating layer, and the conductive material and the insulating layer are removed in the region of the immediate tip of the probe.

Abstract: A method of reducing fluorine contamination on a integrated circuit wafer surface is achieved. The method comprises placing an integrated circuit wafer on a cathode stage. The integrated circuit wafer comprises a surface contaminated with fluorine. The integrated circuit wafer is plasma treated with a plasma comprising a reducing gas that forms HF from the fluorine and a bombardment gas that removes the fluorine from the surface. The cathode stage is heated to thereby increase the rate of the fluorine removal.

Abstract: A new methodology of monitoring process drift and chamber seasoning is presented based on the discovery of the strong correlation between chamber surface condition and free radical density in a plasma. Lower free radical density indicates either there is a significant process drift in the case of production wafer etching or that the chamber needs more seasoning before resuming production wafer etching. Free radical density in the plasma is monitored through measuring the emission intensities of free radicals in the plasma by an optical spectrometer. A timely detection of the extent of process drift and chamber seasoning can help to minimize the chamber downtime and improve its throughput significantly. Such method can also be implemented in existing production wafer etching or chamber seasoning practices in an in-situ, real-time, and non-intrusive manner.

Abstract: Apparatus and processes are disclosed for milling copper adjacent to organic low-k dielectric on a substrate by directing a charged-particle beam at a portion of the copper and exposing the copper to a precursor sufficient to enhance removal of the copper relative to removal of the dielectric, wherein the precursor contains an oxidizing agent, has a high sticking coefficient and a long residence time on the copper, contains atoms of at least one of carbon and silicon in amount sufficient to stop oxidation of the dielectric, and contains no atoms of chlorine, bromine or iodine. In one embodiment, the precursor comprises at least one of the group consisting of NitroEthanol, NitroEthane, NitroPropane, NitroMethane, compounds based on silazane such as HexaMethylCycloTriSilazane, and compounds based on siloxane such as Octa-Methyl-Cyclo-Tetra-Siloxane. Products of the processes are also disclosed.

Abstract: A semiconductor device capable of compatibly suppressing a microloading effect (irregular etching) and over-etching also in formation of a fine contact hole requiring a high aspect ratio is obtained. This semiconductor device comprises a first conductive part, an insulator film having an opening formed on the first conductive part and a second conductive part electrically connected with the first conductive part through the opening. The insulator film includes an upper insulator film and a lower insulator film, stacked/formed at least around a connection part between the first conductive part and the second conductive part, consisting of different materials.

Abstract: Multi-level structures are formed in a semiconductor substrate by first forming a pattern of lines or structures of different widths. Width information on the pattern is decoded by processing steps into level information to form a MEMS structure. The pattern is etched to form structures having a first floor. The structures are oxidized until structures of thinner width are substantially fully oxidized. A portion of the oxide is then etched to expose the first floor. The first floor is then etched to form a second floor. The oxide is then optionally removed, leaving a multi-level structure. In one embodiment, high aspect ratio comb actuators are formed using the multi-level structure process.

Abstract: The fabrication of the read head sensor components where chemical mechanical polishing (CMP) stop layer is deposited above the sensor layers, a first reactive ion etch (RIE) layer and a second RIE layer are deposited, where the second RIE layer is etchable with a different ion species than the first RIE layer. A stencil layer is then deposited and patterned to create an etching stencil having the desired magnetic read track width of the sensor. An RIE step is then conducted in which the second RIE layer is etched. An RIE step for the first RIE layer is then conducted with a different ion species. Thereafter, the sensor layers are milled where the remaining portions of the first and second RIE layers act as a milling mask. A CMP assisted liftoff step is then conducted in which the remaining portions of the ion milling mask are removed.

Abstract: In one aspect, the invention encompasses a method of etching insulative materials which comprise complexes of metal and oxygen. The insulative materials are exposed to physical etching conditions within a reaction chamber and in the presence of at least one oxygen-containing gas. In another aspect, the invention encompasses a method of forming a capacitor. An electrically conductive first layer is formed over a substrate, and a second layer is formed over the first layer. The second layer is a dielectric layer and comprises a complex of metal and oxygen. A conductive third layer is formed over the second layer. The first, second and third layers are patterned into a capacitor construction. The patterning of the second layer comprises exposing the second layer to at least one oxygen-containing gas while also exposing the second layer to physical etching conditions.

Abstract: Method and device for cutting a wire with a small number of processing operations. The method includes forming a cut portion by scanning the semiconductor substrate with a focused ion beam to cut the wire. The method further includes forming a clear region continuously from the cut portion by scanning the semiconductor substrate with the focused ion beam. The clear region is free of stray material of the wire.

Abstract: Chemical generator and method for generating a chemical species at a point of use such as the chamber of a reactor in which a workpiece such as a semiconductor wafer is to be processed. The species is generated by creating free radicals, and combining the free radicals to form the chemical species at the point of use.

Abstract: A method is for manufacturing a microstructure having a thin-walled portion with use of a material substrate. The material substrate has a laminated structure which includes a first conductor layer 101, a second conductor layer 102, a third conductor layer 103, a first insulating layer 104 interposed between the first conductor layer and the second conductor layer, and a second insulating layer 105 interposed between the second conductor layer and the third conductor layer. The first insulating layer is patterned to have a first masking part for covering a thin-wall forming region of the second conductor layer. The second insulating layer is patterned to have a second masking part for covering the thin-wall forming region of the second conductor layer.

Abstract: A system and method for exposing and/or milling a copper metallization layer disposed in dielectric that may have an overlying polyimide layer preferably by use of a FIB machine system used for exposing/milling aluminum metallization layers is disclosed. The method includes using a gas assisted (GAS) system for exposing a portion of a copper metal trace disposed in a dielectric and includes the step of removing a portion of the dielectric overlying the portion of the metal trace using the GAS system activated with a dielectric selective chemical that does not have a significant spontaneous (non ion-beam induced) reaction with the metal trace. The system includes a focused ion beam (FIB) machine for exposing/milling a portion of a metal trace disposed in a dielectric substrate wherein the metal trace is copper.

Abstract: A method for forming a copper damascene feature including providing a semiconductor process wafer including at least one via opening formed to extend through a thickness of at least one dielectric insulating layer and an overlying trench line opening encompassing the at least one via opening to form a dual damascene opening; etching through an etch stop layer at the at least one via opening bottom portion to expose an underlying copper area; carrying out a sub-atmospheric DEGAS process with simultaneous heating of the process wafer in a hydrogen containing ambient; carrying out an in-situ sputter-clean process; and, forming a barrier layer in-situ to line the dual damascene opening.

Abstract: A dual damascene structure with a lesser degree of shoulder loss is achieved. In a method for forming a dual damascene structure having a shoulder in an organic low k film layer by dry-etching the organic low k film layer 208 and a mask layer 210 formed over the organic low k film 208 using at least two different mixed gases, a first step in which the mask layer is etched using a first process gas and then the organic low k film layer is etched into a predetermined depth by continuously using the first process gas and a second step following the first step, in which the organic low k film layer is etched using a second process gas are executed. Since a protective wall is formed at a side wall of a via during the first step, the extent of the shoulder loss occurring in the junction region where a trench and a via form a junction can be reduced.

Abstract: A method for reducing wafer damage during an etching process is provided. In one of the many embodiments, the method includes assigning a bias voltage to each of at least one etching process, and generating the assigned bias voltage before initiation of one of the at least one etching process. The method further includes applying the assigned bias voltage to an electrostatic chuck before initiation of one of the at least one etching processes. The assigned bias voltage level reduces wafer arcing.

Abstract: A method for in-situ reduction of volatile residual contamination on a semiconductor process wafer following a plasma etching process including providing an ambient controlled chamber for accepting transfer of a semiconductor process wafer under controlled ambient conditions following a plasma etching process; providing a heat exchange surface disposed with the ambient controlled chamber in heat exchange relationship with means for heating the heat exchange surface; transferring a semiconductor process wafer having volatile residual contamination under controlled ambient conditions to the ambient controlled chamber; mounting the semiconductor process wafer in heat exchange relationship with the heat exchange surface; and, heating in-situ the heat exchange surface for a time period to thereby heat the semiconductor process wafer to vaporize the volatile residual contamination on the semiconductor process wafer while simultaneously removing a resulting vapor from the ambient controlled chamber.

Abstract: A method and system for backside unlayering a semiconductor device to expose FEOL semiconductor features of the device for subsequent electrical and/or physical probing. A window is formed within a backside substrate layer of the semiconductor. A collimated ion plasma is generated and directed so as to contact the semiconductor only within the backside window via an opening in a focusing shield. This focused collimated ion plasma contacts the semiconductor, only within the window, while the semiconductor is simultaneously being rotated and tilted by a temperature controlled stage, for uniform removal of semiconductor layering such that the semiconductor features, in a location on the semiconductor corresponding to the backside window, are exposed. Backside unlayering of the invention may be enhanced by CAIBE processing.

Abstract: To resolve a problem that an etching rate profile is changed by a position of a nozzle relative to a semiconductor wafer and accordingly, at a vicinity of an outer edge of the semiconductor wafer, an accurate machining result is difficult to achieve, gas including activated species produced by plasma is blown from a nozzle locally to a surface of the semiconductor wafer W supported on a wafer table concentrically therewith to thereby remove unevenness on the surface of the semiconductor wafer. In this case, the wafer table is provided with a radius larger than a radius of the semiconductor wafer supported thereby by an outstretched portion to thereby prevent an outer edge from being removed excessively by reflected gas.

Abstract: A method for manufacturing semiconductor-integrated electronic circuits includes: depositing an auxiliary layer on a substrate; depositing a layer of screening material on the auxiliary layer; selectively removing the layer of screening material to provide a first opening in the layer of screening material and expose an area of the auxiliary layer; and removing this area of the auxiliary layer to form a second opening in the auxiliary layer, whose cross-section narrows toward the substrate to expose an area of the substrate being smaller than the area exposed by the first opening.

Abstract: Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g., plasma etching apparatus), (b) for removing residual corrosive compounds formed by the sample treatment, (c) for wet-processing of the samples and (d) for dry-processing the samples. A plurality of wet-processing treatments of a sample can be performed. The wet-processing apparatus can include a plurality of wet-processing stations. The samples can either be passed in series through the plurality of wet-processing stations, or can be passed in parallel through the wet-processing stations.

Abstract: A method of repairing a semiconductor chip containing copper is taught, whereby copper is selectively removed from the chip. The method involves processing the chip inside a chamber in which the chip is exposed to various gases and an energy source, such as a focused ion beam. To the extent the chip may have non-copper materials, such as nitride and oxide layers, on top of the copper that is to be removed, those non-copper materials will first be selectively removed. Such removal typically results in a hole (a so-called “elevator shaft”) leading to the copper that is to be removed. Next, the method teaches the introduction of a combination of nitrogen and oxygen into the chamber and the directing of the ion beam at the spot where the copper is to be removed. In this manner, the copper on the chip is cleanly and reliably removed, without causing damage to the processing chamber.

Abstract: An electron-emitting device including a protective layer that is formed on a catalyst layer to protect the catalyst layer from the deleterious environmental conditions before or during a cathode process. The present invention further includes a half etching process that is adapted to partially remove portions of the protective layer from the catalyst layer to etch the catalyst layer except carbon nano-tube growing portions. Portions of the protective layer still remain on the catalyst layer to protect the catalyst layer from the deleterious conditions from next cathode formation process.

Abstract: A method for selectively etching a semiconductor feature opening to controllably achieve a critical dimension accuracy including providing a semiconductor wafer including a first opening formed extending through a thickness of at least one dielectric insulating layer and having an uppermost inorganic BARC layer; depositing a photoresist layer over the uppermost BARC layer and patterning the photoresist layer to form an etching pattern for etching a second opening overlying and encompassing the first opening; carrying out a first plasma assisted etching process to etch through a thickness of the BARC layer including a predetermined amount of CO in a plasma etching chemistry to increase an etching resistance of the photoresist layer; and, carrying out a second plasma assisted etching process to etch through a thickness portion of the at least one dielectric insulating layer to form the second opening.

Abstract: The invention relates to the etching of a dielectric layer in an integrated circuit (IC) structure having a patterned metal hard mask layer. The method comprises feeding a gas mixture that includes a carbon monoxide (CO) and at least one fluorocarbon gas mixture into a reactor. The gas mixture has no oxygen (O2) gas. The gas mixture is then converted into a plasma. The plasma selectively etches the dielectric layer. Typically, the dielectric layer comprises silicon.

Abstract: A method and apparatus are provided for the repair of an amplitude defect in a multilayer coating. A significant number of layers underneath the amplitude defect are undamaged. The repair technique restores the local reflectivity of the coating by physically removing the defect and leaving a wide, shallow crater that exposes the underlying intact layers. The particle, pit or scratch is first removed the remaining damaged region is etched away without disturbing the intact underlying layers.

Abstract: A method for forming a patterned amorphous carbon layer in a semiconductor stack, including forming an amorphous carbon layer on a substrate and forming a silicon containing photoresist layer on top of the amorphous carbon layer. Thereafter, the method includes developing a pattern transferred into the resist layer with a photolithographic process and etching through the amorphous carbon layer in at least one region defined by the pattern in the resist layer, wherein a resist layer hard mask is formed in an outer portion of the photoresist layer during etching.

Abstract: Key to the present invention is the subsequent use of two layers of different positive photoresists, possessing different exposure wavelength sensitivities. It is a general object of the present invention to provide a new and improved method of forming semiconductor integrated circuit devices, and more specifically, in the formation of self-aligned dual damascene interconnects and vias, which incorporates two positive photoresist systems, which have different wavelength sensitivities, to form trench/via openings with only a two-step etching process. In addition, the two layers of photoresist exhibit different etch resistant properties, for subsequent selective reactive ion etching steps. The use of a “high contrast” positive photoresist system has been developed wherein the resist system exposure sensitivity is optimized for wavelengths, deep-UV (248 nm) for the top layer of resist, the trench pattern, and I-line (365 nm) for the bottom layer of resist, the via pattern.

Abstract: A surface processing apparatus is provided. In the apparatus, an etching rate ratio of an organic material such as a BARC of anti-reflective film to a resist of mask forming a pattern, that is, a selective ratio is high, the anti-reflective film being a means for forming the pattern with a high accuracy in surface processing of a semiconductor. In the surface processing apparatus, which uses a plasma, a deposition gas is added to a light element of hydrogen as the etching gas. Ions accelerated by a bias electric power supply accelerate etching reaction. Sputtering at edges of the mask can be reduced by using the light element of hydrogen as the etching gas, and the selective ratio of the anti-reflective film to the masking material can be increased by mixing the deposition gas with the hydrogen.

Abstract: A method of rapid etching of an insulating film including an organic-based dielectric film without forming a damage layer or causing decline of the throughput, including the steps of forming an insulating film including an organic-based dielectric film such as a stacked film comprised of a polyarylether film or other organic-based dielectric film and a silicon oxide-based dielectric film or other insulating film, forming a mask layer by patterning above the insulating film, and when etching the organic-based dielectric film portion, using ions or radicals containing NH group generated by gaseous discharge in a mixed gas of hydrogen gas and nitrogen gas or a mixed gas of ammonia gas for etching using the mask layer as an etching mask, to etch the insulating layer and form openings etc. while generating reaction products containing CN group.

Abstract: New methods for fabrication of silicon microstructures have been developed. In these methods, an etching delay layer is deposited and patterned so as to provide differential control on the depth of features being etched into a substrate material. Structures having features with different depth can be formed thereby in a single etching step.

Abstract: Because of environmental pollution prevention laws, PFC (perfluorocarbon) and HFC (hydrofluorocarbon), both etching gases for silicon oxide and silicon nitride films, are expected to be subjected to limited use or become difficult to obtain in the future. An etching gas containing fluorine atoms is introduced into a plasma chamber. In a region where plasma etching takes place, the fluorine-containing gas plasma is made to react with solid-state carbon in order to produce molecular chemical species such as CF4, CF2, CF3 and C2F4 for etching. This method assures a high etch rate and high selectivity while keeping a process window wide.

Abstract: A method for preparing a sample includes separating a portion of substrate from a sample, performing focused ion beam milling, and removing additional sample material using an etchant.

Abstract: A method for tuning an electro-mechanical device such as a MEMS device is disclosed. The method comprises operating a MEMS device in a depressurized system and using FIB micromachining to remove a portion of the MEMS device. Additionally, a method for tuning a plurality of MEMS devices by depositing an active layer and then removing a portion of the active layer using FIB micromachining. Also, a method for tuning a MEMS device and vacuum packaging the MEMS device in situ are provided.

Abstract: There is provided a method of performing a surface treatment, such as coating, denaturation, modification and etching, on a surface of a substrate. The method comprises the steps of bringing a surface treatment gas into contact with a surface of a substrate, and irradiating the surface of the substrate with a fast particle beam to enhance an activity of the surface and/or the surface treatment gas, thereby facilitating a reaction between the surface and the gas. The fast particle beam may be selected from a group consisting of an electron beam, a charged particle beam, an atomic beam and molecular beam. For example, during a coating operation, chemical deposition of predetermined component elements of the gas onto the surface is effected and a predetermined portion of the surface of the substrate is irradiated with a particle beam to form a coating layer on the predetermined portion.

Abstract: A method for preparing a semiconductor wafer for whole wafer backside inspection is disclosed. The frontside of the wafer is covered with a protective frontside substrate and the backside portion of the wafer is thinned using conventional techniques. The whole wafer backside is then polished and a backside substrate, preferably of transparent material is juxtaposed to the backside of the wafer, such as with an adhesive or with a frame. The frontside substrate is then removed, exposing electronic devices for device inspection. The backside of the wafer is maintained open or available to backside inspection such as emission microscopy techniques used to detect defects which emit light.

Abstract: A method of patterning a metal layer in a semiconductor die comprises forming a mask on the metal layer to define an open region and a dense region. The method further comprises etching the metal layer at a first etch rate to form a number of metal segments in the open region and etching the metal layer at a second etch rate to form a number of metal segments in the dense region, where the first etch rate is approximately equal to the second etch rate. The method further comprises performing a number of strip/passivate cycles to remove a polymer formed on sidewalls of the metal segments in the dense region. The sidewalls of the metal segments in the dense region undergo substantially no undercutting and residue is removed from the sidewalls of the metal segments in the dense region.

Abstract: During manufacture, a magnetoresistive sensor having a ferromagnetic free layer is commonly provided with a tantalum cap layer. The tantalum cap layer provides protection to the sensor during manufacture and then is typically removed after performing annealing. The removal of the tantalum cap with a fluorine reactive ion etch leaves low volatility tantalum/fluorine byproducts. The present invention provides a method of using an argon/hydrogen reactive ion etch to remove the tantalum/fluorine byproducts. The resulting sensor has far less damage resulting from the presence of the fluorine byproducts.

Abstract: A method of forming emitter tips on a field emission display. A conductive layer is formed on a substrate, and then a photoresist layer is formed on the conductive layer wherein the photoresist layer has at least a pattern for defining predetermined areas of the emitter tips. Next, using plasma etching with the pattern of the photoresist layer as a mask, the conductive layer is etched to become a plurality of emitter stages. The etching rate of the conductive layer is greater than the etching rate of the photoresist layer. Finally, continuous use of plasma etching with an increased vertical-etching rate etches the lateral sidewalls of the emitter stages, thus shaping them as emitter tips.

Abstract: A method for etching a layer over a substrate is provided. A gas-modulated cyclic process is performed for more than three cycles. Each cycle comprises performing a protective layer forming phase using first gas chemistry with a deposition gas chemistry, which is performed in about 0.0055 to 7 seconds for each cycle and performing an etching phase for the feature through the etch mask using a second gas chemistry using a reactive etching gas chemistry, which is performed in about 0.005 to 14 seconds for each cycle. The protective layer forming phase comprises providing the deposition gas and forming a plasma from the deposition gas. Each etching phase comprises providing a reactive etching gas and forming a plasma from the reactive etching gas.

Abstract: A method for making a thin film device on integrated circuits including the steps of applying a first photoresist layer to a first surface, and patterning the first photoresist layer to have at least a first opening that exposes the first surface. A film is deposited onto the first photoresist layer, wherein a portion of the deposited film is deposited onto the exposed first surface. A second photoresist layer is applied onto the deposited layer, wherein the second photoresist layer is applied to the portion of the deposited film within the first opening and covers a second portion of the deposited layer, wherein the first photoresist layer and the second photoresist layer assist in the defining of the deposited layer. The deposited layer, first photoresist layer, and second photoresist layer are selectively removed, therein exposing the first surface and the second portion of the deposited layer.

Abstract: A method of making a semiconductor device, comprises preparing a plurality of lots each including semiconductor substrates to be processed, the plurality of lots including at least first and second lots, processing the plurality of lots for every one lot, using a semiconductor manufacturing apparatus, judging whether or not the semiconductor manufacturing apparatus is subjected to cleaning before the second lot is processed, depending upon both a first processing type of the first lot to be processed and a second processing type of the second lot to be processed after the first lot, and processing the second lot without the cleaning in the case where the second lot does not require the cleaning.

Abstract: Generally, a method for pre-cleaning native oxides and other contaminants from apertures on a substrate is provided. In one embodiment, a method for pre-cleaning apertures on a substrate includes disposing the substrate on a support member in a process chamber, cooling the substrate at least to a temperature of 100 degrees Celsius, and exposing the substrate to a pre-clean process. In another embodiment, a method for pre-cleaning apertures on a substrate includes cooling the substrate at least to a temperature of 100 degrees Celsius in a first chamber, transferring the substrate to a second chamber and pre-cleaning the substrate in the second chamber while maintaining a substrate temperature of 100 degrees Celsius.

Abstract: A method of forming an electrode for a surface acoustic wave (SAW) device comprises the steps of forming an alloy film (32) made of aluminum (Al) and magnesium (Mg) on a substrate (31) and selectively etching the alloy film (32) by using a gaseous mixture composed of BCl3, Cl2, and N2 to form the electrode such that the electrode has at least one sidewall polymer film (33). The method controls the production of hillocks and voids to provide high withstand voltage.

Abstract: A plasma etch reactor 20 includes a upper electrode 24, a lower electrode 24, a peripheral ring electrode 26 disposed therebetween. The upper electrode 24 is grounded, the peripheral electrode 26 is powered by a high frequency AC power supply, while the lower electrode 28 is powered by a low frequency AC power supply, as well as a DC power supply. The reactor chamber 22 is configured with a solid source 50 of gaseous species and a protruding baffle 40. A nozzle 36 provides a jet stream of process gases in order to ensure uniformity of the process gases at the surface of a semiconductor wafer 48. The configuration of the plasma etch reactor 20 enhances the range of densities for the plasma in the reactor 20, which range can be selected by adjusting more of the power supplies 30, 32.