Abstract: A method for manufacturing a photodiode array includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has a first layer of a first conductivity proximate the first main surface and a second layer of a second conductivity proximate the second main surface. A via is formed in the substrate which extends to a first depth position relative to the first main surface. The via has a first aspect ratio. Generally simultaneously with forming the via, an isolation trench is formed in the substrate spaced apart from the via which extends to a second depth position relative to the first main surface. The isolation trench has a second aspect ratio different from the first aspect ratio.

Abstract: A dual damascene process. A first photoresist layer with a first opening corresponding to a trench pattern is formed on a dielectric layer. A second photoresist layer with a second opening corresponding to a via pattern smaller then the trench pattern is formed on the first photoresist layer and extends to a portion of the dielectric layer. The second photoresist layer has a material character different from the first photoresist layer. A via etching process using the second photoresist as a mask is performed to form a via hole passing through the dielectric layer. A photoresist ashing process is performed to remove the second photoresist layer. A trench etching process using the first photoresist layer as a mask is performed to form a trench in the upper portion of the dielectric layer. The via etching process, the photoresist ashing process and the trench etching process are performed as a continuous process in one chamber.

Abstract: A wafer for use in a MEMS device having two doped layers surrounding an undoped layer of silicon is described. By providing two doped layers around an undoped core, the stress in the lattice structure of the silicon is reduced as compared to a solidly doped layer. Thus, problems associated with warping and bowing are reduced. The wafer may have a pattered oxide layer to pattern the deep reactive ion etch. A first deep reactive ion etch creates trenches in the layers. The walls of the trenches are doped with boron atoms. A second deep reactive ion etch removes the bottom walls of the trenches. The wafer is separated from the silicon substrate and bonded to at least one glass wafer.

Abstract: A method for manufacturing a floating gate includes: forming a tunnel oxide film on a semiconductor substrate; forming a polysilicon layer on a surface of the tunnel oxide film; forming a photosensitive film pattern on a surface of the polysilicon layer; depositing a by-product on the photosensitive film to generate a by-product mask; and using the by-product mask as an etching mask to etch the polysilicon layer, completing fabrication of the floating gate. The polysilicon layer may be etched by a simplified process using a by-product mask so as to fabricate the floating gate, the etch rate of the polysilicon layer may be increased to improve productivity, poly bridge problems may be eliminated, and total amount of a gas used in etching the polysilicon layer may be reduced, resulting in an increase in hardware margin and a decrease in the amount of the gas used in this method.

Abstract: Disclosed herein is a method of fabricating nano-components using nanoplates, including the steps of: printing a grid on a substrate using photolithography and Electron Beam Lithography; spraying an aqueous solution dispersed with nanoplates onto the grid portion to position the nanoplates on the substrate; depositing a protective film of a predetermined thickness on the substrate and the nanoplates positioned on the substrate; ion-etching the nanoplates deposited with the protective film by using a Focused Ion Beam (FIB) or Electron Beam Lithography; and eliminating the protective film remaining on the substrate using a protective film remover after the ion-etching of the nanoplates, and a method of manufacturing nanomachines or nanostructures by transporting such nano-components using a nano probe and assembling with other nano-components.

Abstract: Flash memory devices and methods for fabricating the same. In one example embodiment, a method of fabricating a flash memory includes various acts. First, a tunnel oxide layer is formed on an active region of a semiconductor substrate. Next, a gate region is formed by sequentially forming a floating gate, a gate insulating layer, and a control gate over the tunnel oxide layer. Then, a sidewall oxide layer is formed on a gate region. Next, a fluorine plasma ion implantation process is performed on the sidewall oxide layer. Then, a nitride layer is deposited on the sidewall oxide layer. Next, an etch process is performed to form spacer insulating layers.

Abstract: Plasma parameters such as plasma ion density, wafer voltage, etch rate and wafer current in the chamber are determined from external measurements on the applied RF bias electrical parameters such as voltage and current. The method includes sensing RF parameters corresponding to an input impedance, an input current and an input voltage at the input of the impedance match element to a transmission line coupled between the bias generator and the wafer pedestal. The method continues by computing a junction admittance of a junction between the transmission line and the electrode within the wafer pedestal from the input impedance, input current and input voltage and from parameters of the transmission line. The method further includes providing shunt electrical quantities of a shunt capacitance between the electrode and a ground plane, and providing load electrical quantities of a load capacitance between the electrode and a wafer on the pedestal.

Abstract: In one embodiment, a controller coupled to a focused ion beam tool can execute instructions to acquire parameters for a feature of a semiconductor device, determine a data array using the parameters, and cause the focused ion beam tool to perform tool iterations to form the feature on the semiconductor device using the data array. Other embodiments are described and claimed.

Abstract: The surface morphology of an LED light emitting surface is changed by applying a reactive ion etch (RIE) process to the light emitting surface. Etched features, such as truncated pyramids, may be formed on the emitting surface, prior to the RIE process, by cutting into the surface using a saw blade or a masked etching technique. Sidewall cuts may also be made in the emitting surface prior to the RIE process. A light absorbing damaged layer of material associated with saw cutting is removed by the RIE process. The surface morphology created by the RIE process may be emulated using different, various combinations of non-RIE processes such as grit sanding and deposition of a roughened layer of material or particles followed by dry etching.

Abstract: A method for circuit modification of an microelectronic chip having at least one conductor in an organic dielectric, includes applying a protective inorganic surface layer on top of the organic dielectric, forming at least one window in the protective inorganic surface layer to selectively expose the underlying organic dielectric, etching the organic dielectric in the window area to selectively remove the organic dielectric adjacent to the conductor, and performing at least one process that modifies the conductor.

Abstract: Embodiments relate to a flash memory device and a method of manufacturing a flash memory device, which may increase a coupling coefficient between a control gate and a floating gate by increasing a surface area of floating gate. In embodiments, a flash memory device may be formed by forming a photoresist pattern for forming a floating gate on a semiconductor substrate including an oxide film, a floating gate poly film, and a BARC (Bottom AntiReflect Coating), performing a first etching process using the photoresist pattern as a mask, to etch the floating gate poly film to a predetermined depth, depositing and forming a polymer to cover the photoresist pattern, forming spacers of the polymer at both sidewalls of the photoresist pattern, forming a second etching process using the spacers as a mask, to expose the oxide film, and removing the BARC, the photoresist pattern and the spacers by ashing and stripping.

Abstract: High aspect ratio contact openings are etched while preventing bowing or bending of the etch profile by forming a highly conductive thin film on the side wall of each contact opening. The conductivity of the thin film on the side wall is enhanced by ion bombardment carried out periodically during the etch process.

Abstract: A system and method is disclosed for providing contact etch selectivity for the etching of a plurality of contact etch holes through a dielectric layer of an integrated circuit. The method comprises the steps of obtaining a value of the reactive ion etch (RIE) lag for the dielectric layer, and selecting different values for the diameters of the contact etch holes based upon the desired depths of the contact etch holes and on the value of the RIE lag for the dielectric layer. The invention also comprises a contact diameter application processor that is capable of using RIE lag data to calculate contact diameters for contact etch holes for a mask design layout of an integrated circuit.

Abstract: Disclosed is a method for the formation of features in a damascene process. According to the method, vias are formed in a dielectric layer and then covered by a layer of high molecular weight polymer. The high molecular weight polymer covers the vias but does not enter the vias. A trench is then etched through the high molecular weight polymer and the dielectric layer. Any remaining high molecular weight polymer is then removed.

Abstract: The present invention is directed to improving defect performance in semiconductor processing systems. In specific embodiments, an apparatus for processing semiconductor substrates comprises a chamber defining a processing region therein, and a substrate support disposed in the chamber to support a semiconductor substrate. At least one nozzle extends into the chamber to introduce a process gas into the chamber through a nozzle opening. The apparatus comprises at least one heat shield, each of which is disposed around at least a portion of one of the at least one nozzle. The heat shield has an extension which projects distally of the nozzle opening of the nozzle and which includes a heat shield opening for the process gas to flow therethrough from the nozzle opening. The heat shield decreases the temperature of nozzle in the processing chamber for introducing process gases therein to reduce particles.

Abstract: A method of etching a carbon-containing layer on a semiconductor substrate using a Si-containing gas and a related method of fabricating a semiconductor device in which a plurality of contact holes having excellent sidewall profiles are formed by etching an interlayer insulating layer using a carbon-containing layer pattern formed in accordance with the invention and having a width of several tens of nm as an etch mask are provided. To etch a carbon-containing layer to be used as a second etch mask, a first mask pattern is formed on the carbon-containing layer to partially expose a top surface of the carbon-containing layer. The carbon-containing layer is then anisotropically etched with a plasma of a carbon-etching mixture gas formed of O2 and a Si-containing gas using the first mask pattern as a first etch mask to form the carbon-containing layer pattern.

Abstract: In performing an anisotropic etching process after a taper etching process of a gate conductive layer of a two-layer or three-layer laminated structure, a portion that is not etched is left at an edge of a second conductive film to shorten an LDD region. It is an object to make the LDD region longer by reducing or removing the left portion that is not etched. After a taper etching process of a gate conductive layer of a two-layer or three-layer laminated structure, an argon plasma treatment is performed. With this argon plasma treatment, a reactive organism in the taper etching process is removed, and it becomes possible to reduce or remove the left portion that is not etched in the anisotropic etching to be performed next.

Abstract: A new method of depositing PE-oxide or PE-TEOS. An HDP-oxide is provided over a pattern of polysilicon. An etch back is performed to the deposited HDP-oxide, a layer of plasma-enhanced SiN is deposited. This PE-SiN is etched back leaving SiN spacers on the sidewalls of the poly pattern, further leaving a deposition of HDP-oxide on the top surface of the poly pattern. The profile of the holes within the poly pattern in such that the final layer of PE-oxide or PE-TEOS is deposited without resulting in the formation of keyholes in this latter layer.

Abstract: A method of forming a dual segment liner covering a first and a second set of semiconductor devices is provided. The method includes forming a first liner and a first protective layer on top thereof, the first liner covering the first set of semiconductor devices; forming a second liner, the second liner having a first section covering the first protective layer, a transitional section, and a second section covering the second set of semiconductor devices, the second section being self-aligned to the first liner via the transitional section; forming a second protective layer on top of the second section of the second liner; removing the first section and at least part of the transitional section of the second liner; and obtaining the dual segment liner including the first liner, the transitional section and the second section of the second liner. A semiconductor structure with a self-aligned dual segment liner formed in accordance with one embodiment of the invention is also provided.

Abstract: A method suitable for etching hydrophilic trenches into a substrate, such as silicon, is provided. The method comprises etching and sidewall passivation processes for achieving anisotropy. Sidewalls of the etched trench are made hydrophilic during the etch by virtue of a hydrophilizing dopant in a passivating gas plasma. The method is useful for etching ink supply channels in inkjet printheads.

Abstract: A MEMS device having a proof mass resiliently mounted above a substrate has projections formed on adjacent surfaces of the mass and substrate. The device is formed by creating a plurality of holes in the upper layer. A substance suitable for removing the intermediate layer without substantially removing the upper layer and substrate is introduced through the holes. A substance removing the upper layer, the substrate, or both, is then introduced through the holes to remove a small amount of the substrate and upper layer. Portions of the intermediate layer between the projections are then removed. The dimple structure fabricated from this process will prevent MEMS device stiction both in its final release and device operation.

Abstract: A method for etching on a semiconductors at the back end of line using reactive ion etching. The method comprises reduced pressure atmosphere and a mixture of gases at a specific flow rate ratio during plasma generation and etching. Plasma generation is induced by a source radio frequency and anisotropic etch performance is induced by a second bias radio frequency.

Abstract: A polymer-based, self-aligned wafer-level heterogeneous integration system, SA WLIT, for integrating semiconductor integrated circuit (IC) chips to a substrate is presented. The system includes a method including preparing a substrate, flipping the substrate onto a polymer-based flat surface and securing the substrate to the flat surface, mounting semiconductor chips into the prepared substrate, integrating the chips to the substrate with another polymer-based material, and removing the resulting multi-chip module from the flat surface. The chips may then be connected with each other and regions off the multi-chip module with metal interconnect processing technology. A multi-chip module prepared by the polymer-based, self-aligned heterogeneous integration system including semiconductor chips mounted in a prepared substrate. The chips may be connected to the substrate by a polymer-based integrating material.

Abstract: Provision of a process capable of preferably etching particularly PtMn used for a pin layer of an MRAM is an object: a dry etching method for performing dry etching on a layer including platinum and/or manganese by using pulse plasma and a production method of an MRAM, wherein the dry etching method is applied to processing of the pin layer. The MRAM is configured to have a memory portion comprising a magnetic memory element composed of tunnel magnetoresistive effect element formed by stacking a magnetic fixed layer having a fixed magnetization direction, a tunnel barrier layer and a magnetic layer capable of changing the magnetization direction.

Abstract: A plasma processing method includes a step of preparing a process subject having an organic layer on a surface thereof, and a step of irradiating the process subject with H2 plasma to improve plasma resistance of the organic layer.

Abstract: A method for fabricating a non-electroplated shield using combination patterning and devices formed thereby are disclosed. The method includes depositing a metal layer, such as CZT, removing substantially 75% of the metal layer during a first phase using at least a first removal process and removing a remaining portion of the metal layer during a second phase using at least a second removal process. The first removal process may include depositing a first patterning layer, removing substantially 75% of the metal layer by ion-mill or similar technology and stripping the first patterning layer away. The second removal process may include depositing a second patterning layer and removing the remaining portion of the metal layer using a wet-etch or other etch process and removing the second patterning layer. The deposited metal layer may have a thickness up to several ?m and the edges of the shield exhibit a unique step pattern that is visible in a cross-section view of the shield.

Abstract: Fabrication method of semiconductor device to reduce leak current at junction interface of p-type well and n-type well. The method includes forming a first trench portion by selective dry etching of a silicon substrate using a first etching gas and forming a second trench portion including an enlarged width portion downward from a bottom of the first trench portion by additional dry etching of a silicon substrate at the bottom of the first trench portion using a second etching gas. A mixture gas of a chlorine gas and a fluorocarbon gas is used as the second etching gas and also a bias voltage lower than that in the process to form the first trench portion are used in the process to form the second trench portion.

Abstract: A method of anisotropic plasma etching of a silicon wafer, maintained at a temperature from ?40° C. to ?120° C., comprising alternated and repeated steps of: etching with injection of a fluorinated gas, into the plasma reactor, and passivation with injection of silicon tetrafluoride, SiF4, and of oxygen into the plasma reactor, the flow rate of the gases in the plasma reactor being on the order of from 10% to 25% of the gas flow rate during the etch step.

Abstract: Methods for fabricating TMR and CPP GMR magnetic heads using a chemical mechanical polishing (CMP) process with a patterned CMP conductive protective layer for sensor stripe height patterning. The method comprises defining a stripe height of a read sensor of a magnetic head reader. The method further comprises refill depositing an insulator layer on the read sensor. The method further comprises performing a CMP process down to the conductive protective layer on the read sensor deposited while defining the read sensor to remove an overfill portion of the insulator layer above the conductive protective layer and to remove a sensor pattern masking structure on the conductive protective layer. As a result, the insulator layer is planarized and smooth with the read sensor, eliminating fencing and alumina bumps typically encountered in the insulator layer at the edge of the patterned sensor.

Abstract: A method for improving a polysilicon gate electrode profile to avoid preferential RIE etching in a polysilicon gate electrode etching process including carrying out a multi-step etching process wherein at least one of a lower RF source power and RF bias power are reduced to complete a polysilicon etching process and an in-situ plasma treatment with an inert gas plasma is carried out prior to neutralize an electrical charge imbalance prior to carrying out an overetch step.

Abstract: A photoresist trimming process is described. An etcher equipped with an etching chamber, a wafer holder, a TCP source and a TCP window is provided. After plasma is generated in the etching chamber, the etching chamber is heated without a wafer therein, and the temperature at the TCP window is monitored simultaneously. It is started, at any time after the temperature at the TCP window reaches a predetermined one, to treat wafers with photoresist layers to be trimmed thereon through the etching chamber.

Abstract: A method of forming alignment marks on edge chips in a kerf region of a semiconductor workpiece. The alignment marks are formed in at least one material layer of the semiconductor device. The alignment marks are formed using a separate lithography mask, and may extend into lower layers, including the workpiece, of the semiconductor device. An opaque material layer is deposited, and depressions are formed in the opaque layer over the deep alignment mark trenches. The depressions in the opaque material layer are used to align a lithography process to open the opaque material layer over alignment marks in an underlying metallization layer. The alignment marks in the metallization layer are then used to align the lithography process used to pattern the opaque material layer.

Abstract: A method for etching on a semiconductors at the back end of line using reactive ion etching. The method comprises reduced pressure atmosphere and a mixture of gases at a specific flow rate ratio during plasma generation and etching. Plasma generation is induced by a source radio frequency and anisotropic etch performance is induced by a second bias radio frequency.

Abstract: A manufacturing method of a semiconductor memory device for manufacturing a first semiconductor device and a second semiconductor device wherein a cell array ratio is smaller than that of the first semiconductor device, said manufacturing method has forming the height of first element-isolating insulating films of first memory cell array region of said first semiconductor device so as to be a predetermined height, by performing etching treatment under predetermined conditions using a first etching mask having a first opening for exposing the entirety of said first memory cell array region, and forming the height of second element-isolating insulating films of second memory cell array region and part of peripheral circuit region of said second semiconductor device so as to be the predetermined height, by performing etching treatment under said predetermined conditions using a second etching mask having a second opening for exposing the entirety of said second memory cell array region and a third opening for ex

Abstract: A method of making an etch structure in a substrate involves the steps of providing a mask on a substrate with a pattern that leaves at least one opening leaving the substrate in direct contact with the ambient, performing an isotropic or quasi-isotropic etch through a mask to create a cavity under the mask, which mask is left behind as a suspended membrane above the cavity; and performing a subsequent anisotropic etch that etches anisotropically the pattern of the mask in the bottom of the cavity.

Abstract: A method of manufacturing a semiconductor device. In the method, a thin film is formed on an Si substrate having face orientation (100), that part of the thin film, which lies on an element-isolating region, is removed. Then, the Si substrate is subjected to selective etching, making a trench in the substrate to isolate an element, by using the thin film as mask and a mixture solution of hydrofluoric acid and ozone water.

Abstract: A method is provided. The method includes forming a conductive layer on an inner surface of a substrate and providing a sacrificial layer over the conductive layer. The method includes forming a plurality of channels in the sacrificial layer and plating the sacrificial layer to substantially fill the plurality of channels with a plating material comprising conducting material. The method also includes etching the sacrificial layer to form a conducting structure having fins where conducting material remains separated by microchannels where the sacrificial layer is etched.

Abstract: Micromechanical devices having complex multilayer structures and techniques for forming the devices are described.

Abstract: A method for simultaneously forming multiple line-widths, one of which is less than that achievable employing conventional lithographic techniques. The method includes providing a structure which includes a memory layer and a sidewall image transfer (SIT) layer on top of the memory layer. Then, the SIT layer is patterned resulting in a SIT region. Then, the SIT region is used as a blocking mask during directional etching of the memory layer resulting in a first memory region. Then, a side wall of the SIT region is retreated a retreating distance D in a reference direction resulting in a SIT portion. Said patterning comprises a lithographic process. The retreating distance D is less than a critical dimension CD associated with the lithographic process. The SIT region includes a first dimension W2 and a second dimension W3 in the reference direction, wherein CD<W2<2D<W3.

Abstract: Methods of micro-machining a semiconductor substrate to form through fluid feed slots therein. One method includes providing a semiconductor substrate wafer having a thickness greater than about 500 microns and having a device side and a back side opposite the device side. The back side of the wafer is mechanically ground to provide a wafer having a thickness ranging from about 100 up to about 500 microns. Dry etching is conducted on the wafer from a device side thereof to form a plurality of reentrant fluid feed slots in the wafer from the device side to the back side of the wafer.

Abstract: A method for fabricating substrate material to include trenches and unreleased beams with submicron dimensions includes etching a first oxide layer on the substrate to define a first set of voids in the first oxide layer to expose the substrate. A second oxide layer is accreted to the first oxide layer to narrow the first set of voids to become a second set of voids on the substrate. A polysilicon layer is deposited over the second oxide layer, the first oxide layer and the substrate. A third set of voids is etched into the polysilicon layer. Further etching widens the third set of voids to define a fourth set of voids to expose the first oxide layer and the substrate. The first oxide layer and the substrate is deeply etched to define beams and trenches in the substrate.

Abstract: A method for etching an ultra high aspect ratio feature in a dielectric layer through a carbon based mask is provided. The dielectric layer is selectively etched with respect to the carbon based mask, wherein the selective etching provides a net deposition of a fluorocarbon based polymer on the carbon based mask. The selective etch is stopped. The fluorocarbon polymer is selectively removed with respect to the carbon based mask, so that the carbon based mask remains, using a trimming. The selectively removing the fluorocarbon polymer is stopped. The dielectric layer is again selectively etched with respect to the carbon based mask, wherein the second selectively etching provides a net deposition of a fluorocarbon based polymer on the carbon based mask.

Abstract: A method for ensuring the structural integrity of III-nitride opto-electronic or opto-mechanical air-gap nano-structured devices, comprising (a) performing ion beam implantation in a region of the III-nitride opto-electronic and opto-mechanical air-gap nano-structured device, wherein the milling significantly locally modifies a material property in the region to provide the structural integrity; and (b) performing a band-gap selective photo-electro-chemical (PEC) etch on the III-nitride opto-electronic and opto-mechanical air-gap nano-structured device. The method can be used to fabricate distributed Bragg reflectors or photonic crystals, for example.

Abstract: A damascene process incorporating a GCIB step is provided. The GCIB step can replace one or more CMP steps in the traditional damascene process. The GCIB step allows for selectable removal of unwanted material and thus, reduces unwanted erosion of certain nearby structures during damascene process. A GCIB step may also be incorporated in the damascene process as a final polish step to clean up surfaces that have been planarized using a CMP step.

Abstract: A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate so that the semiconductor substrate is exposed at the portion, a mounting substrate on which the semiconductor element is mounted, and a resin layer which seals at least a surface side of the semiconductor element with resin.

Abstract: A method for etching on a semiconductors at the back end of line using reactive ion etching. The method comprises reduced pressure atmosphere and a mixture of gases at a specific flow rate ratio during plasma generation and etching. Plasma generation is induced by a source radio frequency and anisotropic etch performance is induced by a second bias radio frequency.

Abstract: A manufacturing process technology creates a pattern on a first layer using a focused ion beam process. The pattern is transferred to a second layer, which may act as a traditional etch stop layer. The pattern can be formed on the second layer without irradiation by light through a reticle and without wet chemical developing, thereby enabling conformal coverage and very fine critical feature control. Both dark field patterns and light field patterns are disclosed, which may enable reduced or minimal exposure by the focused ion beam.

Abstract: A method to passivate a freshly etched metal structure comprises providing a metal surface on a substrate that has been etched by a first particle beam, exposing the metal surface to a passivation gas, and exposing the freshly etched metal structures to a second particle beam in the presence of the passivation gas. The second particle beam may comprise an ion beam or a laser beam. The passivation gas may comprise water vapor, oxygen gas, or hydrocarbon gas.

Abstract: A process for stripping photoresist from a substrate is provided. A processing system for implanting a dopant into a layer of a film stack, annealing the stripped film stack, and stripping the implanted film stack is also provided. When high dopant concentrations are implanted into a photoresist layer, a crust layer may form on the surface of the photoresist layer that may not be easily removed. The methods described herein are effective for removing a photoresist layer having such a crust on its surface.

Abstract: Techniques for magnetic device fabrication are provided. In one aspect, a method of patterning at least one, e.g., nonvolatile, material comprises the following steps. A hard mask structure is formed on at least one surface of the material to be patterned. The hard mask structure is configured to have a base, proximate to the material, and a top opposite the base. The base has one or more lateral dimensions that are greater than one or more lateral dimensions of the top of the hard mask structure, such that at least one portion of the base extends out laterally a substantial distance beyond the top. The top of the hard mask structure is at a greater vertical distance from the material being etched than the base. The material is etched.