Utilizing Multilayered Mask Patents (Class 438/717)
  • Patent number: 7932183
    Abstract: A method of manufacturing a multilayer thin film pattern includes forming a metal film over a substrate, forming a second thin film over the metal film, forming a resist pattern over the second thin film, etching the second thin film using the resist pattern as a mask, transforming the resist pattern using an organic solvent or a RELACS agent to cover an edge face of the etched second thin film and etching the metal film while the edge face of the second thin film is covered with the resist pattern.
    Type: Grant
    Filed: November 2, 2007
    Date of Patent: April 26, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yasuyoshi Itoh, Masami Hayashi
  • Patent number: 7923375
    Abstract: A method for manufacturing a semiconductor device includes forming a photo-resist pattern above a first film, implanting a predetermined dopant that increases an etching rate of the first film into the first film using the photo-resist pattern as a mask, thereby forming an implantation layer in the first film, and etching a first portion of the first film, which is at least a part of the implantation layer, using the photo-resist pattern as a mask.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: April 12, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keisuke Kikutani
  • Patent number: 7923372
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of etch mask patterns over an etch target layer, each of the etch mask patterns including a first hard mask, a first pad layer, and a second pad layer, forming spacers on both sidewalls of the etch mask patterns, the spacers including a material substantially the same as that of the first pad layer, forming a second hard mask over the resulting substrate structure until gaps between the etch mask patterns are filled, the second hard mask including a material different from that of the first hard mask but substantially the same as that of the second pad layer, planarizing the second hard mask until the first pad layer is exposed, removing the first pad layer and the spacers, and etching the etch target layer using the remaining first and second hard masks as an etch barrier layer.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: April 12, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Young-Jun Kim, Sang-Wook Park
  • Patent number: 7919414
    Abstract: A method for forming fine patterns in a semiconductor device includes forming an etch stop layer and a sacrificial layer over an etch target layer, forming photoresist patterns over the sacrificial layer, etching the sacrificial layer by using the photoresist patterns as an etch barrier to form sacrificial patterns, forming spacers on both sidewalls of the sacrificial patterns, removing the sacrificial patterns, and etching the etch stop layer and the etch target layer by using the spacer as an etch barrier.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: April 5, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Won-Kyu Kim, Jun-Hyeub Sun
  • Patent number: 7910489
    Abstract: A method for etching features into an etch layer disposed below a photoresist mask without an intermediate hardmask is provided. A plurality of etch cycles are provided. Each etch cycle comprises providing a deposition etch phase that etches features into the etch layer and deposits polymer on sidewalls of the features and over the photoresist and providing a cleaning phase that removes polymer deposited on the sidewalls.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: March 22, 2011
    Assignee: Lam Research Corporation
    Inventors: Ji Soo Kim, Peter Cirigliano, Sangheon Lee, Dongho Heo, Daehan Choi, S. M. Reza Sadjadi
  • Patent number: 7911034
    Abstract: A method for patterning CNTs on a wafer wherein a CNT layer is provided on a substrate, a hard mask film is deposited on the CNT layer, a BARC layer (optional) is coated on the hard mask film, and a resist is patterned on the BARC layer (or directly on the hard mask film if the BARC layer is not included). Then, the resist pattern is effectively transferred to the hard mask film by etching the BARC layer (if provided) and etching partly into, but not entirely through, the hard mask film (i.e., etching is stopped before reaching the CNT layer). Then, the resist and the BARC layer (if provided) is stripped, and the hard mask pattern is effectively transferred to the CNTs by etching away (preferably by using C1, F plasma) the portions of the hard mask which have been already partially etched away.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: March 22, 2011
    Assignee: Nantero, Inc.
    Inventors: Shiqun Gu, Peter G. McGrath, James Elmer, Richard J. Carter, Thomas Rueckes
  • Patent number: 7906435
    Abstract: A semiconductor device includes at least two adjacent memory cell blocks, each of the memory cell blocks having a plurality of memory cell units, each of memory cell units having a plurality of electrically reprogrammable and erasable memory cells connected in series, a plurality of cell gates for selecting the plurality of memory cells within the two adjacent memory cell blocks, each of the plurality of cell gates being formed with roughly rectangular closed loops or roughly U shaped open loops, each of the loops being connected to a corresponding cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within one of the two adjacent memory cell blocks and being connected to a corresponding memory cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within the other memory cell block of the two adjacent memory cell blocks and a plurality of pairs of first and second selection gates for selecting the memory cell block, the
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: March 15, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Nobuyasu Nishiyama
  • Patent number: 7902071
    Abstract: A method for forming a trench-gated field effect transistor (FET) includes the following steps. Using a first mask, defining and simultaneously forming a plurality of active gate trenches and at least one gate runner trench extending to a first depth within a silicon region such that (i) the at least one gate runner trench has a width greater than a width of each of the plurality of active gate trenches, and (ii) the plurality of active gate trenches are contiguous with the at least one gate runner trench; and using the first mask and a second mask for protecting the at least one gate runner trench, further extending only the plurality of active gate trenches to a second and final depth within the silicon region.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: March 8, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Bruce Douglas Marchant
  • Patent number: 7902079
    Abstract: A method for fabricating a recess pattern in a semiconductor device includes defining an active region on a substrate, forming a first mask pattern over the active region in a line type structure, forming a second mask pattern comprising an open region over the active region, the open region exposing a portion where the active region and the first mask pattern intersect, and etching the active region of the substrate exposed by the first and second mask patterns to form recess patterns.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: March 8, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yong-Soon Jung
  • Patent number: 7902078
    Abstract: A processing method includes a silicon oxide etching process of performing a plasma etching on a target layer mainly made up of silicon, a silicon oxide layer formed on the target layer and a target object having a previously patterned resist layer formed on the silicon oxide layer, the plasma etching of the silicon oxide layer being performed by using the resist layer as a mask; a deposits removing process of removing deposits generated in the silicon oxide etching process and stuck to the target object; and a silicon etching process of performing a plasma etching on the target layer by a plasma generated from a processing gas containing SF6, O2 and SiF4 while using the silicon oxide layer as a mask.
    Type: Grant
    Filed: February 14, 2007
    Date of Patent: March 8, 2011
    Assignee: Tokyo Electron Limited
    Inventor: Michiko Nakaya
  • Patent number: 7892982
    Abstract: A method for forming fine patterns of a semiconductor device includes forming an etching film on a substrate having first and second areas, forming first mask patterns on the substrate to have a first pattern density in the first area and a second pattern density in the second area, forming first capping patterns between the first mask patterns, forming second capping patterns between the first mask patterns, such that recess areas are formed between second capping patterns, and such that a first etching pattern is defined to include the first and second capping patterns, forming second mask patterns in the recess areas to include the first and second mask patterns, removing one of the first and second etching patterns, such that a single etching pattern is remaining on the substrate, and etching the etching film using the remaining etching pattern as an etch mask to form etching film patterns.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: February 22, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Doo-youl Lee, Pan-suk Kwak, Sung-gon Jung, Jung-hyeon Lee, Suk-joo Lee, Cha-won Koh, Ji-young Lee
  • Patent number: 7892977
    Abstract: In a method for forming hard mask patterns of a semiconductor device first hard mask patterns are formed on a semiconductor substrate. Second hard mask patterns are formed and include first patterns which are substantially perpendicular to the first hard mask patterns and second patterns which are positioned between the first hard mask patterns. Third hard mask patterns are formed between the first patterns.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: February 22, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Woo Yung Jung
  • Patent number: 7892981
    Abstract: A method of forming a micro pattern of a semiconductor device includes forming an etch target layer, a hard mask layer, a Bottom Anti-Reflective Coating (BARC) layer and a first photoresist pattern over a semiconductor substrate. An organic layer is formed on a surface of the first photoresist pattern. A second photoresist layer is formed over the BARC layer and the organic layer. An etch process is performed so that the second photoresist layer remains on the BARC layer between the first photoresist patterns and becomes a second photoresist pattern. The organic layer on the first photoresist pattern and between the first and second photoresist patterns is removed. The BARC layer formed below the organic layer is removed. The hard mask layer is etched using the first and second photoresist patterns as an etch mask. The etch target layer is etched using a hard mask pattern as an etch mask.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: February 22, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Woo-Yung Jung
  • Patent number: 7892979
    Abstract: A method of manufacturing a dot pattern includes the steps of preparing a structured material composed of a plurality of columnar members containing a first component and a region containing a second component different from the first component surrounding the columnar members, with the structured material being formed by depositing the first component and the second component on a substrate, and removing the columnar members from the structured material to form a porous material having a columnar hole. In addition, a material is introduced into the columnar hole portions of the porous material to form a dot pattern, and the porous material is removed.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: February 22, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventors: Miki Ogawa, Hirokatsu Miyata, Albrecht Otto, Akira Kuriyama, Hiroshi Okura, Tohru Den, Kazuhiko Fukutani
  • Publication number: 20110039416
    Abstract: A method of pattern etching a Si-containing anti-reflective coating (ARC) layer is described. The method comprises etching a feature pattern into the silicon-containing ARC layer using plasma formed from a process gas containing SF6 and a hydrocarbon gas. The method further comprises adjusting a flow rate of the hydrocarbon gas relative to a flow rate of the SF6 to reduce a CD bias between a final CD for nested structures in the feature pattern and a final CD for isolated structures in the feature pattern.
    Type: Application
    Filed: August 17, 2009
    Publication date: February 17, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Christopher COLE, Akiteru KO
  • Patent number: 7888269
    Abstract: A method includes forming a layer of silicon oxynitride (SiON), silicon rich nitride (SiRN) or silicon nitride (Si3N4) over a layer of semiconducting material. The method further includes forming a first layer of anti-reflective material over the layer of SiON, SiRN or Si3N4 and forming a second layer of anti-reflective material over the first layer. The method also includes using the first layer, second layer and layer of SiON, SiRN or Si3N4 as a mask when etching a pattern in the layer of semiconducting material.
    Type: Grant
    Filed: October 24, 2005
    Date of Patent: February 15, 2011
    Assignees: Spansion LLC, GlobalFoundries, Inc.
    Inventors: Kouros Ghandehari, Hirokazu Tokuno, David Matsumoto, Christopher H. Raeder, Christopher Foster, Weidong Qian, Minh Van Ngo
  • Patent number: 7884026
    Abstract: A semiconductor wafer includes a substrate, a conductive layer, a dielectric layer having a via, a hard mask defined a trench pattern, and a sacrificial layer. Then a sequential of etching processes is performed upon the semiconductor wafer in a chamber to form a trench and expose the conductive layer. By operating all procedures within one chamber, manufacturing time is efficiently shortened and yield is thus increased.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: February 8, 2011
    Assignee: United Microelectronics Corp.
    Inventor: An-Chi Liu
  • Patent number: 7883972
    Abstract: A semiconductor device may include a fin structure having source/drain regions and channel fins connected between source/drain patterns. A gate insulation layer may be provided on the channel fins. A gate electrode may include lower gate patterns and an upper gate pattern. The lower gate patterns may extend in a vertical direction and contact the gate insulation layer. The upper gate pattern may extend in a second horizontal direction substantially perpendicular to the first horizontal direction. The upper gate pattern may be connected to upper portions of the lower gate patterns.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: February 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Man Yoon, Choong-Ho Lee, Chul Lee, Dong-Gun Park
  • Patent number: 7879728
    Abstract: A method to form sub-lithographic trench structures in a substrate and an integrated circuit comprising sub-lithographic trench structures in a substrate. The method includes forming sets of trenches with a lithographic mask and filling the sets of trenches with sets of step spacer blocks comprising two alternating spacer materials which are separately removable from each other. In one embodiment, the trench structures formed are one-nth the thickness of the lithographic mask's feature size. The size of the trench structures being dependent on the thickness and number of spacer material layers used to form the set of step spacer blocks. The number of spacer material layers being n/2 and the thickness of each spacer material layer being one-nth of the lithographic mask's feature size.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: February 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Chung H. Lam, Hemantha K. Wickramasinghe
  • Patent number: 7867912
    Abstract: A method of manufacturing semiconductor structures is disclosed. In one embodiment, a first mask is provided above a substrate. The first mask includes first mask lines extending along a first axis. A second mask is provided above the first mask. The second mask includes second mask lines extending along a second axis that intersects the first axis. At least one of the first and second masks is formed by a pitch fragmentation method. Structures may be formed in the substrate, wherein the first and the second mask are effective as a combined mask. The structures may be equally spaced at a pitch in the range of a minimum lithographic feature size for repetitive line structures.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: January 11, 2011
    Assignee: Qimonda AG
    Inventors: Dirk Caspary, Arnd Scholz, Stefano Parascandola, Christoph Nölscher
  • Patent number: 7867908
    Abstract: A method of fabricating a substrate includes following steps. First, a metallic panel having a first surface and a second surface is provided. A first half-etching process is carried out to etch the first surface of the metallic panel to a first depth so that a first patterned metallic layer is formed on the first surface. Next, a first insulating material is deposited into gaps in the first patterned metallic layer to form a first insulator. Thereafter, a second half-etching process is carried out to etch the second surface of the metallic panel to a second depth and expose at least a portion of the first insulator so that a second patterned metallic layer is formed on the second surface. The first depth and the second depth together equal the thickness of the metallic panel.
    Type: Grant
    Filed: April 13, 2009
    Date of Patent: January 11, 2011
    Assignee: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Chih-Ming Chang, Cheng-Po Yu, Chung W. Ho
  • Patent number: 7862735
    Abstract: A method of forming a relatively fine contact hole using two masks. The two masks may have only their edge portions open, which may overlap each other.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: January 4, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Haeng Leem Jeon
  • Patent number: 7857982
    Abstract: The invention includes methods of etching features into substrates. A plurality of hard mask layers is formed over material of a substrate to be etched. A feature pattern is formed in such layers. A feature is etched only partially into the substrate material using the hard mask layers with the feature pattern therein as a mask. After the partial etching, at least one of the hard mask layers is etched selectively relative to the substrate material and remaining of the hard mask layers. After etching at least one of the hard mask layers, the feature is further etched into the substrate material using at least an innermost of the hard mask layers as a mask. After the further etching, the innermost hard mask layer and any hard mask layers remaining thereover are removed from the substrate, and at least a portion of the feature is incorporated into an integrated circuit.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: December 28, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Mirzafer Abatchev, Gurtej S. Sandhu, Aaron R. Wilson, Tony Schrock
  • Patent number: 7858458
    Abstract: A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second gate is defined in the pMOS region. Disposable spacers are simultaneously defined about the first and second gates. The nMOS and pMOS regions are selectively masked, one at a time, and LDD and Halo implants performed using the same masks as the source/drain implants for each region, by etching back spacers between source/drain implant and LDD/Halo implants. All transistor doping steps, including enhancement, gate and well doping, can be performed using a single mask for each of the nMOS and pMOS regions. Channel length can also be tailored by trimming spacers in one of the regions prior to source/drain doping.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: December 28, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Suraj Mathew
  • Patent number: 7851371
    Abstract: A method for manufacturing a semiconductor device of the present invention includes: forming a first film, a second film and a third film in sequence on a silicon substrate; patterning a resist film formed on the third film by conducting an exposure and developing process for the resist film employing an exposure mask including a phase shifter; selectively dry-etching the third film through a mask of the resist film employing the second film as an etch stop to process the third film into a first pattern; further dry-etching the third film employing the second film as an etch stop to partially remove the third film, thereby processing the third film into a second pattern; patterning the second film employing the third film having the second pattern as a mask; and patterning the first film employing the patterned second film as a mask.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: December 14, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihisa Koretsune, Masato Fujita
  • Patent number: 7851369
    Abstract: A method for forming features in a polysilicon layer is provided. A hardmask layer is formed over the polysilicon layer. A photoresist mask is formed over the hardmask layer. The hardmask layer is etched through the photoresist mask to form a patterned hardmask. The patterned hardmask is trimmed by providing a non-carbon containing trim gas comprising oxygen and a fluorine containing compound, forming a plasma from the trim gas, and trimming the hardmask. Features are etched into the polysilicon layer through the hardmask.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: December 14, 2010
    Assignee: Lam Research Corporation
    Inventor: Tom A. Kamp
  • Patent number: 7846843
    Abstract: A process for manufacturing a semiconductor device using a spacer as an etch mask for forming a fine pattern is described. The process includes forming a hard mask layer over a target layer that is desired to be etched. A sacrificial layer pattern is subsequently formed over the hard mask layer. Spacers are formed on the sidewalls of the sacrificial layer pattern. The protective layer is formed on the hard mask layer portions between the sacrificial patterns formed with the spacer. The sacrificial layer pattern and the protective layer are then later removed, respectively. The hard mask layer is etched using the spacer as an etching mask. After etching, the spacer is removed. Finally, the target layer is etched using the etched hard mask as an etching mask.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: December 7, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Chai O Chung, Jong Min Lee, Chan Bae Kim, Hyeon Ju An, Hyo Seok Lee, Sung Kyu Min
  • Patent number: 7846825
    Abstract: In a method of forming a contact hole and a method of manufacturing a semiconductor device having the same, a first insulation interlayer is formed on a substrate. A dummy pattern is formed on the first insulation interlayer. A second insulation interlayer is formed to cover the dummy pattern. A photoresist pattern is formed on the second insulation interlayer. The photoresist pattern has an exposed portion. The dummy pattern under the photoresist pattern is arranged to cross over the exposed portion of the photoresist pattern. The first and second insulation interlayers are etched using the photoresist pattern and the dummy pattern as an etching mask, to form a plurality of contact holes on both sides of the dummy pattern. Accordingly, the contact holes may be formed to have a smaller width.
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: December 7, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Nam-Jung Kang, Jae-Hoon Song, So-Hyun Ryu, Dong-Kwan Yang
  • Patent number: 7846812
    Abstract: A method of forming trench isolation includes etching first trench lines into semiconductive material of a semiconductor substrate. First isolation material is formed within the first trench lines within the semiconductive material. After forming the first isolation material within the first trench lines, second trench lines are etched into semiconductive material of the substrate between the first trench lines such that the first trench lines and second trench lines alternate. Second isolation material is formed within the second trench lines within the semiconductive material. Alternate and additional aspects are contemplated.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: December 7, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Christopher W. Hill
  • Publication number: 20100297850
    Abstract: A selective self-aligned dual patterning method. The method includes performing a single lithography operation to form a patterned mask having a narrow feature in a region of a substrate that is to a have pitch-reduced feature and a wide feature in a region of the substrate that is to have a non-pitch-reduced feature. Using the patterned mask, a template mask is formed with a first etch and the patterned mask is then removed from the narrow feature while being retained over the wide feature. The template mask is then thinned with a second etch to introduce a thickness delta in the template mask between the narrow and wide features. A spacer mask is then formed and the thinned narrow template mask is removed to leave a pitch double spacer mask while the thick wide template mask feature is retained to leave a non-pitch reduced mask.
    Type: Application
    Filed: July 17, 2009
    Publication date: November 25, 2010
    Inventors: Hun Sang Kim, Hyungje Woo, Shinichi Koseki, Eda Tuncel, Chung Liu
  • Patent number: 7838433
    Abstract: A method and apparatus for process integration in manufacture of a photomask are disclosed. In one embodiment, a cluster tool suitable for process integration in manufacture of a photomask including a vacuum transfer chamber having coupled thereto at least one hard mask deposition chamber and at least one plasma chamber configured for etching chromium. In another embodiment, a method for process integration in manufacture of a photomask includes depositing a hard mask on a substrate in a first processing chamber, depositing a resist layer on the substrate, patterning the resist layer, etching the hard mask through apertures formed in the patterned resist layer in a second chamber; and etching a chromium layer through apertures formed in the hard mask in a third chamber.
    Type: Grant
    Filed: September 12, 2006
    Date of Patent: November 23, 2010
    Assignee: Applied Materials, Inc.
    Inventor: Ajay Kumar
  • Patent number: 7833911
    Abstract: A method of manufacturing a semiconductor device includes: etching a first film provided on a wafer in a chamber; removing at least part of reaction products deposited on a component in the chamber facing the wafer by the etching to cause a distribution state of the deposited reaction products to get closer to a uniform state; and then etching a second film provided on the wafer in the chamber.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: November 16, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Katsumata, Katsuaki Aoki
  • Patent number: 7829471
    Abstract: A method and apparatus for process integration in manufacture of a photomask are disclosed. In one embodiment, a cluster tool suitable for process integration in manufacture of a photomask including a vacuum transfer chamber having coupled thereto at least one hard mask deposition chamber and at least one plasma chamber configured for etching chromium. In another embodiment, a method for process integration in manufacture of a photomask includes depositing a hard mask on a substrate in a first processing chamber, depositing a resist layer on the substrate, patterning the resist layer, etching the hard mask through apertures formed in the patterned resist layer in a second chamber; and etching a chromium layer through apertures formed in the hard mask in a third chamber.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: November 9, 2010
    Assignee: Applied Materials, Inc.
    Inventor: Ajay Kumar
  • Patent number: 7824996
    Abstract: A resist pattern (5) is formed in a dimension of a limitation of an exposure resolution over a hard mask material film (4) over a work film (3). The material film (4) is processed using the resist pattern (5) as a mask. A hard mask pattern (6) is thereby formed. Thereby a resist pattern (7), over a non-selected region (6b), having an opening (7a) through which a selection region (6a) in the mask pattern is exposed is formed. Only the mask pattern (6a) exposed through the opening (7a) is slimmed by performing a selection etching, the work film (3) is etched by using the mask pattern (6). A work film pattern (8) is thereby formed, which include a wide pattern section (8a) of a dimension width of the limitation of the exposure resolution and a slimmed pattern section (8a) of a dimension that is not more than the limitation of the exposure resolution.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: November 2, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Hashimoto, Soichi Inoue, Kazuhiro Takahata, Kei Yoshikawa
  • Patent number: 7816270
    Abstract: A method of forming minute patterns in a semiconductor device, and more particularly, a method of forming minute patterns in a semiconductor device having an even number of insert patterns between basic patterns by double patterning including insert patterns between a first basic pattern and a second basic pattern which are transversely separated from each other on a semiconductor substrate, wherein a first insert pattern and a second insert pattern are alternately repeated to form the insert patterns, the method includes the operation of performing a partial etching toward the second insert pattern adjacent to the second basic pattern, or the operation of forming a shielding layer pattern, thereby forming the even number of insert patterns.
    Type: Grant
    Filed: May 6, 2009
    Date of Patent: October 19, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-yong Park, Jae-kwan Park, Yong-sik Yim, Jae-hwang Sim
  • Patent number: 7816162
    Abstract: After a p-type cladding layer, an etching rate reducing layer and a p-type contact layer are formed in order on an n-type substrate, an etching mask is formed. Then, by using the etching mask, the p-type contact layer, the etching rate reducing layer and the p-type cladding layer are partially etched in the region outside the etching mask with an etchant. At this time, the etching rate of the layers by the etchant is slower in the etching rate reducing layer than in the p-type cladding layer and the p-type contact layer. Then, a metal thin film is formed such that the film continuously coats an upper surface and side surfaces of a ridge consisting of the above layers left after the etching step. A normal vector at a surface coated with the thin film has an upward component.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: October 19, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shuichi Hirukawa, Katsuhiko Kishimoto
  • Patent number: 7816253
    Abstract: When an interconnect structure is built on porous ultra low k (ULK) material, the bottom of the trench and/or via is usually damaged by a following metallization process which may be suitable for dense higher dielectric materials. Embodiment of the present invention may provide a method of forming an interconnect structure on an inter-layer dielectric (ILD) material. The method includes steps of treating an exposed area of said ILD material to create a densified area, and metallizing said densified area.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: October 19, 2010
    Assignee: International Business Machines Corporation
    Inventors: Shyng-Tsong Chen, Qinghuang Lin, Kelly Malone, Sanjay Mehta, Terry A. Spooner, Chih-Chao Yang
  • Patent number: 7811940
    Abstract: A pattern having exceptionally small features is formed on a partially fabricated integrated circuit during integrated circuit fabrication. The pattern comprises features formed by self-organizing material, such as diblock copolymers. The organization of the copolymers is directed by spacers which have been formed by a pitch multiplication process in which spacers are formed at the sides of sacrificial mandrels, which are later removed to leave spaced-apart, free-standing spacers. Diblock copolymers, composed of two immiscible block species, are deposited over and in the space between the spacers. The copolymers are made to self-organize, with each block species aggregating with other block species of the same type.
    Type: Grant
    Filed: May 3, 2007
    Date of Patent: October 12, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S Sandhu
  • Patent number: 7807582
    Abstract: The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a layer of insulating material above an active area of a dual bit memory cell, forming a hard mask layer above the layer of insulating material, the hard mask layer having an original thickness, performing at least two partial etching processes on the hard mask layer to thereby define a patterned hard mask layer above the layer of insulating material, wherein each of the partial etching processes is designed to etch through less than the original thickness of the hard mask layer, the hard mask layer having openings formed therein that correspond to a digitline contact and a plurality of storage node contacts for the dual bit memory cell, and performing at least one etching process to form openings in the layer of insulating material for the digitline contact and the plurality of storage node contacts using the patterned hard mask layer as an etch mask.
    Type: Grant
    Filed: March 6, 2006
    Date of Patent: October 5, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Jonathan Doebler
  • Patent number: 7805820
    Abstract: A thin-film resonator and a method for producing a thin-film component includes, for the purpose of structuring an upper first dielectric layer, a mask that comprises a second dielectric layer facing the upper dielectric layer and a photoresist layer. Initially, the photoresist layer that serves as photomask during the structuring of the second dielectric layer is structured. The structures of the second dielectric layer, together with the structures of the photoresist layer located thereabove, form a mask that is used for structuring the first dielectric layer.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: October 5, 2010
    Assignee: Epcos AG
    Inventors: Christoph Eggs, Ansgar Schäufele, Martin Woelky
  • Patent number: 7807583
    Abstract: A method for patterning high aspect ratio vias is provided. More specifically a dry etching method is provided for patterning deep vias or vias with high aspects ratios thereby eliminating the hard mask undercut. A method is provided to create (pattern) deep vias in a substrate for use in three dimensional stacked semiconductor devices and/or structures. More specifically, a method is provided for patterning deep vias with an aspect ratio up to 10 into a Si substrate with smooth via sidewalls and sufficient slope to enable metallization.
    Type: Grant
    Filed: July 24, 2007
    Date of Patent: October 5, 2010
    Assignee: IMEC
    Inventors: Joke Van Aelst, Herbert Struyf, Serge Vanhaelemeersch
  • Publication number: 20100248491
    Abstract: A method for performing a double pattering process of a semiconductor device is provided. The method includes forming a hard mask layer having a stack structure of a first layer, a second layer and a third layer in sequence, forming a first photoresist pattern over the hard mask layer, etching the third layer to form third layer patterns by using the first photoresist pattern as an etch barrier, forming a second photoresist pattern over the third layer patterns, etching the second layer to form second layer patterns by using the second photoresist pattern and the third layer patterns as an etch barrier, removing the second photoresist pattern, and etching the first layer to form first layer patterns by using the second layer patterns as an etch barrier.
    Type: Application
    Filed: June 30, 2009
    Publication date: September 30, 2010
    Inventors: Jun-Hyeub Sun, Shi-Young Lee, Jong-Sik Bang, Sang-Min Ju
  • Patent number: 7803709
    Abstract: A method of fabricating patterns of a semiconductor device includes the steps of forming first sacrificial layer patterns over a pattern target layer; forming first spacers on sidewalls of the first sacrificial layer patterns; forming a second sacrificial layer pattern over the first sacrificial layer patterns and the first spacers such that at least one of the first spacers is exposed by the second sacrificial layer pattern; forming a dual spacer by forming a second spacer on the exposed first spacer; removing the second sacrificial layer pattern and the first sacrificial layer patterns; and forming a first pattern having a first pitch defined by the first spacers and a second pattern having a second pitch defined by the dual spacer by etching an exposed portion of the pattern target layer using the first spacers and the dual spacer as etching masks.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: September 28, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyoung Soon Yune
  • Patent number: 7799695
    Abstract: A device for liquid treatment of a defined area of a wafer-shaped article, especially of a wafer, in which a mask is kept at a defined short distance to the wafer-shaped article such that liquid can be retained between the mask and the defined area of the wafer-shaped article by capillary forces.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: September 21, 2010
    Assignee: Lam Research AG
    Inventor: Philipp Engesser
  • Patent number: 7790619
    Abstract: A method for fabricating a semiconductor device including forming a gate insulation layer, a conductive layer for a gate electrode, and an insulation layer for a gate hard mask over a substrate, selectively etching the insulation layer for a gate hard mask and the conductive layer for a gate electrode to expose a first region of the substrate, thereby forming an initial gate line, forming a first insulation layer for an insulation over a resultant structure where the initial gate line is formed, performing a planarization process until the insulation layer for a gate hard mask is exposed, and selectively etching the insulation layer for a gate hard mask and the conductive layer for a gate electrode to expose a second region of the substrate, the second region being not overlapped with the first region, thereby forming a final gate line having a line width smaller than the initial gate line.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: September 7, 2010
    Assignee: Hynix Semiconductor Inc
    Inventor: Weon-Chul Jeon
  • Publication number: 20100216310
    Abstract: A method of dry developing an anti-reflective coating (ARC) layer on a substrate is described. The method comprises disposing a substrate comprising a multi-layer mask in a plasma processing system, wherein the multi-layer mask comprises a lithographic layer overlying a silicon-containing ARC layer and wherein the lithographic layer comprises a feature pattern formed therein using a lithographic process. The method further comprises: introducing a process gas to the plasma processing system according to a process recipe, the process gas comprising a nitrogen-containing gas, a hydrogen-containing gas, and a CxHyFz-containing gas, wherein x, y, and z are integers greater than or equal to unity; forming plasma from the process gas in the plasma processing system according to the process recipe; and exposing the substrate to the plasma in order to transfer the feature pattern in the lithographic layer to the underlying silicon-containing ARC layer.
    Type: Application
    Filed: February 20, 2009
    Publication date: August 26, 2010
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Andrew W. METZ, Shuhei OGAWA, Vaidyanathan BALASUBRAMANIAM, Masaru NISHINO
  • Patent number: 7781347
    Abstract: A semiconductor device includes a hard mask including a first layer and a second layer in contact with each other and having opposite stress types, wherein a difference between initial stresses of the first layer and the second layer is increased so that after a thermal process, the difference between the final stresses of the first and second layer becomes smaller, to reduce the likelihood of peeling of the first or second layer. The initial stress of the first layer includes a compressive stress and the initial stress of the second layer includes a tensile stress.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: August 24, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jung-Seock Lee, Ki-Won Nam
  • Patent number: 7776747
    Abstract: A method for forming a fine pattern of a semiconductor device includes forming a first hard mask layer over a semiconductor substrate, forming a second hard mask layer pattern over the first hard mask layer, forming a spacer on a sidewall of the second hard mask layer pattern, selectively etching the first hard mask layer by using the spacer and the second hard mask layer pattern as an etching mask to form a first hard mask layer pattern, forming a first insulating film filling the second hard mask layer pattern and the first hard mask layer pattern, selectively etching the second hard mask layer pattern and the underlying first hard mask layer pattern to form a third hard mask layer pattern, removing the first insulating film and the spacer, and patterning the semiconductor substrate by using the third hard mask layer pattern as an etching mask to form a fine pattern.
    Type: Grant
    Filed: June 6, 2007
    Date of Patent: August 17, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Keun Do Ban, Cheol Kyu Bok, Jun Hyeub Sun
  • Patent number: 7767100
    Abstract: A patterning method with a filling material with a T-shaped cross section is used as a mask during patterning to produce structures having sublithographic dimensions, such as a double-fin field effect transistor.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: August 3, 2010
    Assignee: Infineon Technologies AG
    Inventors: Rodger Fehlhaber, Helmut Tews
  • Publication number: 20100184300
    Abstract: A method of forming a pattern includes forming a first layer on a substrate, forming a second layer on the first layer, depositing a multi-temperature phase-change material on the second layer, patterning the second layer using the multi-temperature phase-change material as a mask, reflowing the multi-temperature phase-change material, and patterning the first layer using the reflowed multi-temperature phase-change material as a mask.
    Type: Application
    Filed: February 26, 2010
    Publication date: July 22, 2010
    Applicant: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventor: Scott Jong Ho Limb