Abstract: A method of etching silicon nitride substantially selectively relative to an oxide of aluminum includes providing a substrate comprising silicon nitride and an oxide of aluminum. The silicon nitride and the oxide is exposed to an etching solution comprising HF and an organic HF solvent under conditions effective to etch the silicon nitride substantially selectively relative to the oxide. Other aspects and implementations are contemplated.

Abstract: An exemplary method for making a memory structure having different-sized memory cell layers comprises forming at least two layers of ferromagnetic materials, forming at least one mask layer above the ferromagnetic materials, patterning the at least one mask layer, etching the ferromagnetic materials using the at least one mask layer as a first etch transfer mask, laterally reducing a planar dimension of the at least one mask layer to be narrower than the ferromagnetic materials, and etching a layer of the ferromagnetic materials using the reduced at least one mask layer as a second etch transfer mask, such that the ferromagnetic layer being etched becomes a different lateral size than another ferromagnetic layer of the ferromagnetic materials.

Abstract: Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow trenches at additional locations. Etching of the shallow and deep trenches then proceeds simultaneously.

Abstract: A high reverse voltage diode includes a hetero junction made up from a silicon carbide base layer, which constitutes a first semiconductor base layer, and a polycrystalline silicon layer, which constitutes a second semiconductor layer, and whose band gap is different from that of the silicon carbide base layer. A low concentration N type polycrystalline silicon layer is deposited on a first main surface side of the silicon carbide base layer, and a metal electrode is formed on a second main surface side of the silicon carbide base layer which is opposite to the first main surface side thereof.

Abstract: A method for use in manufacturing a semiconductor device includes forming a photoresist pattern on a substrate, performing first etching process in which an initial trench is formed using the photoresist pattern as a mask, and performing second distinct etching process to enlarge the initial trench. Thus, the initial trench can be formed using the photoresist pattern having a stable structure. Thereafter, the trench is enlarged using an etching solution having a composition based on the material in which the initial trench is formed, e.g., a silicon substrate or an insulation film. Therefore, a metal wiring, an isolation film or a contact can be formed in the enlarged trench to desired dimensions.

Abstract: A process for the wet chemical treatment of semiconductor wafers, in which the semiconductor wafers are treated with treatment liquids, has the semiconductor wafers firstly treated with an aqueous HF solution, then treated with an aqueous O3 solution and finally treated with water or an aqueous HCl solution, these treatments forming a treatment sequence.

Abstract: The present invention relates to a method for fabricating a semiconductor device. In more detail of the aforementioned method, a first mask layer covering a cell region is formed on an insulation layer in the cell region. Meanwhile, a second mask layer is formed in a peripheral circuit region with a predetermined distance from the first mask layer. The insulation layer is then etched with use of the first and the second mask layers as an etch mask to form a spacer at both sidewalls of each gate line pattern in the peripheral region and simultaneously form a guard beneath the second mask layer. The first and the second mask layers are removed thereafter. Next, a third mask layer opening the cell region but covering the whole regions including a guard region in the peripheral circuit region is formed. A wet etching process is performed to the insulation layer remaining in the cell region by using the third mask layer as an etch mask.

Abstract: A method of patterning a layer of high-k dielectric material is provided, which may be used in the fabrication of a semiconductor device. A first etch is performed on the high-k dielectric layer. A portion of the high-k dielectric layer being etched with the first etch remains after the first etch. A second etch of the high-k dielectric layer is performed to remove the remaining portion of the high-k dielectric layer. The second etch differs from the first etch. Preferably, the first etch is a dry etch process, and the second etch is a wet etch process. This method further includes a process of plasma ashing the remaining portion of the high-k dielectric layer after the first etch and before the second etch.

Abstract: Disclosed is a method for producing a multicrystalline silicon substrate for solar cells comprising: a metal deposition step for depositing such metal particles as platinum and silver on the surface of the substrate by electroless-plating chloroplatinic acid or silver perchlorate; a boring step for subjecting the substrate surface to etching in a solution containing at least one of hydrofluoric acid and hydrogen peroxide; and a step for removing a stain layer by immersing the substrate into an alkaline solution. A multicrystalline silicon substrate having a lower reflectance is provided at a lower cost.

Abstract: In the manufacturing method of a GOLD structured TFT having a gate electrode of double-layered structure, in which, compared to a second layer gate electrode, the first layer gate electrode is thinner in film thickness and longer in dimension of the channel direction, by controlling the density of the photo-absorbent contained in a positive type resist such as diazonaphthoquinone (DNQ)-novolac resin series, the taper angle of the side wall is controlled to a desired angle range so that the angle thereof becomes smaller. Owing to this, it is possible to control the retreat amount of the resist when carrying out dry etching and the dimension of Lov area to a desired dimensional range so that the dimension thereof becomes larger.

Abstract: A process for treating a copper or copper alloy substrate surface with a composition and corrosion inhibitor solution to minimize defect formation and surface corrosion, the method including applying a composition including one or more chelating agents, a pH adjusting agent to produce a pH between about 3 and about 11, and deionized water, and then applying a corrosion inhibitor solution. The composition may further comprise a reducing agent and/or corrosion inhibitor. The method may further comprise applying the corrosion inhibitor solution prior to treating the substrate surface with the composition.

Abstract: A method of patterning a layer of magnetic material to form isolated magnetic regions. The method forms a mask on a film stack comprising a layer of magnetic material such that the protected and unprotected regions are defined. The unprotected regions are etched in a high temperature environment to form isolated magnetic regions.

Abstract: A composition for stripping photoresist, methods of preparing and forming the same, a method of manufacturing a semiconductor device using the composition, and a method of removing a photoresist pattern from an underlying layer using the composition, where the composition may include an ethoxy N-hydroxyalkyl alkanamide represented by the formula, CH3CH2—O—R3—CO—N—R1R2OH, an alkanolamine and a polar material. Raw materials of alkyl alkoxy alkanoate, represented by a chemical formula of R4—O—R3—COOR5, and alkanolamine, represented by a chemical formula of NHR1R2OH, may be mixed to form a mixture, which is stirred and cooled to obtain the composition. The composition may balance exfoliation and dissolution of photoresist patterns, and may potentially eliminate thread-type residues from remaining on a surface of an underlying layer after removing the photoresist patterns.

Abstract: In the manufacturing method of a GOLD structured TFT having a gate electrode of double-layered structure, in which, compared to a second layer gate electrode, the first layer gate electrode is thinner in film thickness and longer in dimension of the channel direction, by controlling the density of the photo-absorbent contained in a positive type resist, which contains a photo-absorbent of diazonaphthoquinone (DNQ)-novolac resin series, the taper angle of the side wall is controlled to a desired angle range so that the angle thereof becomes smaller. Owing to this, it is possible to control the retreat amount of the resist when carrying out dry etching and the dimension of Lov area to a desired dimensional range so that the dimension thereof becomes larger.

Abstract: A method of etching silicon nitride substantially selectively relative to an oxide of aluminum includes providing a substrate comprising silicon nitride and an oxide of aluminum. The silicon nitride and the oxide is exposed to an etching solution comprising HF and an organic HF solvent under conditions effective to etch the silicon nitride substantially selectively relative to the oxide. Other aspects and implementations are contemplated.

Abstract: A method for efficiently manufacturing a semiconductor device, the semiconductor device having an FET and a pn junction diode provided on the same semiconductor substrate, the FET having a Schottky junction for a gate electrode and a gate recess, includes the steps of forming a channel layer, a first etching stopper layer, an n-type common layer, a second etching stopper layer, a p-type layer, and a third etching stopper layer on the semiconductor substrate in that order; etching away the p-type layer and the third etching stopper layer in specific regions; simultaneously forming a source electrode, a drain electrode, a cathode; forming a mask having an opening for forming a gate recess and a gate electrode and an opening for forming an anode; forming the gate recess by etching while the third etching stopper layer prevents the p-type layer from being etched; and simultaneously forming the gate electrode and the anode.

Abstract: A method for fabrication of silicon-on-nothing (SON) MOSFET using selective etching of Si1?xGex layer, includes preparing a silicon substrate; growing an epitaxial Si1?xGex layer on the silicon substrate; growing an epitaxial thin top silicon layer on the epitaxial Si1?xGex layer; trench etching of the top silicon and Si1?xGex, into the silicon substrate to form a first trench; selectively etching the Si1?xGex layer to remove substantially all of the Si1?xGex to form an air gap; depositing a layer of SiO2 by CVD to fill the first trench; trench etching to from a second trench; selectively etching the remaining Si1?xGex layer; depositing a second layer of SiO2 by CVD to fill the second trench, thereby decoupling a source, a drain and a channel from the substrate; and completing the structure by state-of-the-art CMOS fabrication techniques.

Abstract: A method and system for providing a semiconductor device. The semiconductor device includes a first layer to be etched. The method and system include depositing an anti-reflective coating. At least a portion of the anti-reflective coating layer is on the first layer. The method and system also include patterning a resist layer. The resist layer includes a pattern having a plurality of apertures therein. The resist layer is for etching the first layer. A first portion of the first layer and a second portion of the anti-reflective coating layer are exposed by the pattern. The method and system also include etching the first portion of the first layer and the second portion of the anti-reflective coating layer and removing the resist layer utilizing a plasma etch. The anti-reflective coating layer is resistant to the plasma etch.

Abstract: In a chemical mechanical polishing method for polishing a low-k material insulating layer formed on a semiconductor wafer, aqueous abrasive slurry composed of a water component, an abrasive component, a first additive for making the low-k material insulating layer of the semiconductor wafer hydrophilic in nature, and a second additive for adding acidity to the aqueous abrasive slurry, is prepared. The aqueous abrasive slurry is feed to a rotating polishing pad having a larger diameter than that of the semiconductor wafer. The low-k material insulating layer of the semiconductor wafer is applied and pressed onto the rotating polishing pad while rotating the semiconductor wafer in the same rotational direction as that of the rotating polishing pad, whereby a polishing rate of the low-k material insulating layer of the semiconductor wafer is improved.

Abstract: A process for cleaning a silicon surface. First, a silicon surface is cleaned with an oxidant solution. Next, the silicon surface is rinsed with HF vapor or liquid and then with the silicon surface with hydrogen water or deionized water under megasonic agitation. Finally, the silicon surface is cleaned with an oxidant solution a second time. The present inventive cleaning process can be applied in thin film transistor (TFT) fabrication and the TFT obtained has higher electron mobility.

Abstract: A method for preventing to form a spacer undercut in SEG preclean process is provided. This present invention utilizes HFEG solution to etch the first spacer and the second spacer simultaneously, which can prevent from producing a spacer undercut, meanwhile; a native oxide layer upon a surface of a semiconductor substrate is removed. Hence, the clean surface on the semiconductor substrate is obtained. This method includes the steps as follows: Firstly, the native oxide layer upon the surface of the semiconductor substrate is removed by DHF (HF in deionized water) solution. Then, etching the first spacer and the second spacer at the same time by HFEG (HF diluted by ethylene glycol) solution. Also, the native oxide upon the semiconductor substrate is removed. Therefore, it obtains the clean semiconductor surface without a serious spacer undercut.

Abstract: A semiconductor substrate (1) comprising an SOI (2) formed therein. The semiconductor substrate (1) comprises first and second wafers (4,6) which are directly bonded together along a bond interface (9). Prior to bonding the wafers (4,6), a portion (15) of the second wafer (6) is ion implanted to form a p+ region for facilitating selective etching thereof to form a buried cavity (16), in which a buried insulating layer is subsequently formed under a portion (10) of the first wafer (4) for forming the SOI (2). After bonding of the first and second wafers (4,6) a communicating opening (20) is etched through the first wafer (4) to the bond interface (9), and the selectively etchable portion (15) is etched through the communicating opening (20) to form the buried cavity (16). The buried cavity (16) is then filled with deposited oxide to form the buried insulating layer (11).

Abstract: The invention concerns a method for forming nanostructures of semi-conductor material on a substrate of dielectric material by chemical vapour deposition (CVD). Said method comprises the following steps: a step of forming on the substrate (12) stable nuclei (14) of a first semi-conductor material in the form of islands, by CVD from a precursor (11) of the first semi-conductor material chosen so that the dielectric material (12) accepts the formation of said nuclei (14), a step of forming nanostructures (16A, 16B) of a second semi-conductor material from the stable nuclei (14) of the first semi-conductor material, by CVD from a precursor (21) chosen to generate a selective deposition of the second semi-conductor material only on said nuclei (14). The invention further concerns nanostructures formed according to one of said methods as well as devices comprising said nanostructures.

Abstract: Described herein is a method of forming a printhead. A silicon-on-insulator (SOI) substrate, including a first silicon layer, a second silicon layer, and an oxide layer between the first silicon layer and the second silicon layer, is provided. A plurality of thin film layers is formed on a first surface of the substrate. At least one of the layers forms a plurality of ink ejection elements. Ink feed holes are formed through the thin film layers. An opening is formed in the substrate by (a) etching the first silicon layer of the SOI substrate using a wet etch to etch a trench in the first silicon layer extending to the oxide layer; (b) etching an opening in the oxide layer; and (c) etching an opening in the second silicon layer to form an ink path between a backside of the SOI substrate and a topside of the SOI substrate.

Abstract: A process of manufacturing a semiconductor device includes the steps of forming a stacked structure of a first III-V compound semiconductor layer containing In and having a composition different from InP and a second III-V compound semiconductor layer containing In. The second III-V compound semiconductor layer is formed over the first III-V compound semiconductor layer and growing an InP layer at regions adjacent the stacked structure to form a stepped structure of InP. The process further includes the step of wet-etching the stepped structure and the second III-V compound semiconductor layer using an etchant containing hydrochloric acid and acetic acid to remove at least the second III-V compound semiconductor layer.

Abstract: Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow trenches at additional locations. Etching of the shallow and deep trenches then proceeds simultaneously.

Abstract: The present invention provides a method of preparing a surface of a silicon wafer for formation of HSG structures. The method contemplates providing a wafer having at least one HSG template comprising polysilicon formed in BPSG, the HSG template being covered by silicon dioxide. The wafer is treated with a cleaning agent to clean the surface of the wafer. Next, the wafer is treated with a conditioning agent. The conditioning agent removes native oxide from the HSG template without excessively etching structural BPSG. Preferably, the conditioning agent also removes a thin layer of polysilicon on the HSG template. The wafer is then transferred to a process chamber for HSG formation.

Abstract: A two-step via cleaning process that removes metal polymer and oxide polymer residues from a via with substantially no damage to the via or underlying structures on a semiconductor substrate. The two-step cleaning process comprises first subjecting the residue layer to a nitric acid dip that removes the metal polymer component to expose the oxide polymer component. The oxide polymer component is then subjected to a phosphoric acid dip that removes the oxide polymer component. The oxide polymer and metal polymer residues may also be removed during the fabrication of the via by removing them directly after their respective formations.

Abstract: A method is disclosed for accurately predicting the wet etch end points as a function of the temperature and concentration of the etching solution, as well as of the thickness of the film to be etched. This is accomplished by fitting an etch rate equation to the process of etching a film in terms of two constant parameters that are determined by one set of experiments performed on a given wet etch bench. Thereafter, the constants are used with the rate equation to calculate precisely the etch rate of a film, and then the etch rate is divided into a target film loss or a target film thickness to obtain etching time, or time to etch, which takes into account the variations in temperature and concentration, for example, of the acid in the solution. The resulting film either looses the specified amount of material, or acquires the specified thickness without incurring any damage, which is especially suited for sub-micron semiconductor technology where precise etching is required.

Abstract: The present invention relates to a method of manufacturing a semiconductor integrated circuit in which a via hole reaching a metal wiring and a concave groove are simultaneously formed in an interlayer film. When the interlayer film and the material of an organic film embedded in the via hole are etched, the etching rate for the material of the organic film with an etching gas is set to be higher than the etching rate for the interlayer film with an etching gas. Thus, plasma etching does not proceed in a state in which the material of the organic film projects from the bottom of the concave groove formed in the interlayer film, and the production of depositions is prevented.

Abstract: Disclosed is a method for forming a shallow trench isolation. A pad oxide layer is formed on a semiconductor substrate. First and second stopping layers are sequentially formed on the pad oxide layer. The second stopping layer, the first stopping layer, the pad oxide layer and the semiconductor substrate are etched to form a second stopping layer pattern, a first stopping layer pattern, a pad oxide layer pattern and a trench. A trench inner wall oxide layer is formed at an inner surface portion of the trench. A nitride layer liner is formed on a resulted structure. A field oxide layer is formed in the trench. By selectively removing the second stopping layer pattern, the first stopping layer pattern is exposed. Then, the first stopping layer pattern is removed. Since the chemical mechanical polishing is stopped at the second stopping layer pattern, the first stopping layer pattern is prevented from erosion when the chemical mechanical polishing process is carried out.

Abstract: Described herein is a method for delineating crystalline defects in a thin Si layer over a SiGe alloy layer. The method uses a defect etchant with a high-defect selectivity in Si. The Si is etched downed to a thickness that allows the defect pits to reach the underlying SiGe layer. A second etchant, which can be the same or different from the defect etchant, is then used which attacks the SiGe layer under the pits while leaving Si intact.

Abstract: An etching method for use in integrated circuit fabrication includes providing a metal nitride layer on a substrate assembly, providing regions of cobalt silicide on first portions of the metal nitride layer, and providing regions of cobalt on second portions of the metal nitride layer. The regions of cobalt and the second portions of the metal nitride layer are removed with at least one solution including a mineral acid and a peroxide. The mineral acid may be selected from the group including HCl, H2SO4, H3PO4, HNO3, and dilute HF (preferably the mineral acid is HCl) and the peroxide may be hydrogen peroxide. Further, the removal of the regions of cobalt and the second portions of the metal nitride layer may include a one step process or a two step process. In the one step process, the regions of cobalt and the second portions of the metal nitride layer are removed with a single solution including the mineral acid and the peroxide.

Abstract: A method for plating solder is provided. In accordance with the method, a die having a seed metallization thereon is provided. The seed metallization is microetched (85) with a solution comprising an acid and an oxidizer, thereby forming an etched seed metallization. An under bump metallization (UBM) is then electroplated (87) onto the etched seed metallization, and a lead-free solder composition, such as SnCu, is electroplated (91) onto the UBM. A method for reflowing solder is also provided, which may be used in conjunction with the method for plating solder. In accordance with this later method, the substrate is subjected to a seed metallization etch (137), followed by a microetch (141). A solder flux is then dispensed onto the substrate (147) and the solder is reflowed (149).

Abstract: A process for producing a semiconductor wafer is based upon etching the semiconductor wafer with an etching medium flowing in a laminar flow along a direction of flow toward an edge of the semiconductor wafer. There is a protective shield arranged in front of the edge of the semiconductor wafer, so that the etching medium flows onto the protective shield and not onto the edge of the semiconductor wafer. There is also a process that has the semiconductor wafer being inclined with respect to the direction of flow of the etching medium, so that there is an angle of less than 180° between the direction of flow of the etching medium and a first side of the semiconductor wafer. Also, there is an angle of greater than 180° between the direction of flow of the etching medium and a second side of the semiconductor wafer, and the second side of the semiconductor wafer is subsequently polished.

Abstract: A polishing pad conditioner cleaning method and an apparatus for effectively removing particles from a polishing pad conditioner. The polishing pad conditioner is immersed into a cleaning liquid contained in a cleaning bath. The cleaning liquid is continuously supplied into the cleaning bath. An inert gas is injected into the cleaning liquid from a bottom of the cleaning bath. The injected inert gas bubbles the cleaning liquid, so that the particles sticking to the polishing pad conditioner are removed and overflow from the cleaning bath. The polishing pad conditioner is effectively cleaned, so that formation of particles and scratches on a wafer are reduced when a polishing process is subsequently carried out using the cleaned polishing pad conditioner.

Abstract: An etching method for use in integrated circuit fabrication includes providing a metal nitride layer on a substrate assembly, providing regions of cobalt silicide on first portions of the metal nitride layer, and providing regions of cobalt on second portions of the metal nitride layer. The regions of cobalt and the second portions of the metal nitride layer are removed with at least one solution including a mineral acid and a peroxide. Further, the removal of the regions of cobalt and the second portions of the metal nitride layer may include a one-step process or a two-step process. In the one-step process, the regions of cobalt and the second portions of the metal nitride layer are removed with a single solution including the mineral acid and the peroxide. In the two-step process, the regions of cobalt are removed with a first solution containing a mineral acid and a peroxide and the second portions of the metal nitride layer are removed with a second solution containing a peroxide.

Abstract: Various methods for forming surface micromachined microstructures are disclosed. One aspect relates to executing surface micromachining operation to structurally reinforce at least one structural layer in a microstructure. Another aspect relates to executing the surface micromachining operation to form a plurality of at least generally laterally extending etch release channels within a sacrificial material to facilitate the release of the corresponding microstructure.

Abstract: A method of shallow trench isolation fill-in to create the void-free trenches is disclosed. First, a liner oxide layer is formed in the trenches. Next, the silicon substrate is pre-wetted with DI water, and the liner oxide layer is etched by a chemical solution. The chemical solution is an oxide etchant, such as HF solution or BOE (buffered oxide etchant). The etching rate close to an opening of a trench is faster than a bottom of the trench. Finally, the trenches are filled with a HDP oxide layer.

Abstract: A silicon element having macrocavities beneath its exterior surface is fabricated by electrochemical etching of a p-type silicon wafer. Etching at a high current density results in the formation of deep macrocavities overhung by a layer of crystalline silicon. The process works with both aqueous and non-aqueous electrolytes.

Abstract: In the manufacturing method of a GOLD structured TFT having a gate electrode of double-layered structure, in which, compared to a second layer gate electrode, the first layer gate electrode is thinner in film thickness and longer in dimension of the channel direction, by controlling the density of the photo-absorbent contained in a positive type resist, which contains a photo-absorbent of diazonaphthoquinone (DNQ)-novolac resin series, the taper angle of the side wall is controlled to a desired angle range so that the angle thereof becomes smaller. Owing to this, it is possible to control the retreat amount of the resist when carrying out dry etching and the dimension of Lov area to a desired dimensional range so that the dimension thereof becomes larger.

Abstract: A method for reducing the surface roughness of a metal layer is provided. In some embodiments, the method may include polishing the metal layer to a level substantially above any layers arranged directly beneath the metal layer. In some cases, the semiconductor topography comprising the metal layer may be substantially absent of any material laterally adjacent to the metal layer during polishing. In either case, a semiconductor topography having a metal layer with a mean surface roughness less than the mean surface roughness obtained during the deposition of the metal layer may be obtained. As such, the method may include reducing the mean surface roughness of a metal layer. For example, the method may include reducing the mean surface roughness of a metal layer by at least a factor of ten.

Abstract: A method for forming a shallow trench isolation using a SiON anti-reflective coating which eliminates water spot defects. The method begins by providing a substrate. A pad oxide layer is formed over the substrate. A silicon nitride layer is formed on the pad oxide layer. A silicon oxynitride layer is formed on the silicon nitride layer. A photoresist mask, having an opening, is formed over the silicon oxynitride layer. The silicon oxynitride layer, the silicon nitride layer, the pad oxide layer, and the substrate are etched through the opening, forming a trench. The photoresist mask is removed. In the key step, the silicon oxynitride layer is removed. Then, a thin silicon oxide layer is grown and a silicon oxide layer is deposited and planarized to form a shallow trench isolation.

Abstract: A method for fabricating STI for semiconductor device. The method includes the following steps. A trench is formed on the semiconductor substrate, a liner oxide is formed on the bottom and sidewall of the trench, and then a liner nitride is formed on the liner oxide. The first oxide layer is deposited in the trench by high density plasma chemical vapor deposition. The first oxide layer is spray-etched to a predetermined depth, wherein the recipe of the spray etching solution is HF/H2SO4=0.3˜0.4. A second oxide layer is deposited to fill the trench by high density plasma chemical vapor deposition to form a shallow trench isolation structure.

Abstract: An etchant and a method for fabricating a substrate for an electronic device using the etchant where the etchant contains a predetermined additive to control the etch rate of a Cu deposition layer (containing Cu, Cu/Ti, or Cu/Ta) over passage of time. Some examples of the additive may include a chelate having the —COOH group, a chemical compound containing a Cu ion, and a deoxidizer containing sulfur (S). The method includes forming a metal thin film containing copper (Cu) on a substrate, selectively exposing the metal thin film, and etching at least one of the exposed and the unexposed portions on the metal thin film with the additive-containing etchant to control the Cu etch rate over time against the number of sheets of processed substrates. The use of the additive-containing etchant results in improved yield and reduction in production costs because of less frequent etchant replacements.

Abstract: A method of manufacturing a semiconductor device is capable of preventing a dishing phenomenon from occurring without using dummy patterns. A plurality of conductive patterns are formed along the entire surface of a semiconductor substrate with an irregular pattern density. The conductive patterns have a first stopper layer at the top thereof. An interlayer insulating layer is formed on the conductive patterns. Next, a second stopper layer is formed on the interlayer insulating layer. An etching mask is formed on the second stopper layer so as to expose a first region having a conductive pattern density that is higher than that of another region(s). By using the etching mask, the second stopper layer and part of the interlayer insulating layer are etched at the first region.

Abstract: A method of forming a bottle-shaped trench in a semiconductor substrate. The method is suitable for formation of the capacitor of DRAM. First, the semiconductor substrate is selectively etched to form a trench, wherein the trench has a top portion and a bottom portion. A nitride film is then formed on the top portion of the trench. Next, the semiconductor substrate is etched through the bottom portion of the trench by a solution of hydrogen peroxide and hydrofluoric acid as the etchant to form a bottle-shaped trench followed by removal of the nitride film.

Abstract: The present invention relates to a method for fabricating semiconductor capacitors, which enables the capacitance of the capacitors to be increased.

Abstract: A method of forming a shallow trench isolation type semiconductor device comprises forming an etch protecting layer pattern to define at least one active region on a substrate, forming at least one trench by etching the substrate partially by using the etch protecting layer pattern as an etch mask, forming a thermal-oxide film on an inner wall of the trench, filling the trench having the thermal-oxide film with a CVD silicon oxide layer to form an isolation layer, removing the etch protecting layer pattern from the substrate over which the isolation layer is formed, removing the thermal-oxide film formed on a top end of the inner wall of the trench to a depth of 100 to 350 Å, preferably 200 Å from the upper surface of the substrate, and forming a gate oxide film on the substrate from which the active region and the top end are exposed.

Abstract: A method of making a semiconductor structure includes etching an anti-reflective coating layer at a pressure of 10 millitorr or less; etching a nitride layer with a first nitride etch plasma having a first F:C ratio; and etching the nitride layer with a second nitride etch plasma having a second F:C ratio. The first F:C ratio is greater than the second F:C ratio.