Abstract: A method of manufacturing an electronic device, in particular but not exclusively a semiconductor device, in which method a substrate (2) is placed inside a process chamber (1) and a surface (3) of the substrate (2) is subjected to an ozone treatment comprising the steps of: providing a liquid onto the surface (3) of the substrate (2) via first supply means, introducing a solution comprising a liquid carrier solvent and ozone gas into the process chamber (1) via second supply means, without bringing about direct contact between the solution and the surface (3) of the substrate (2).

Abstract: One aspect of the invention relates to a method of etching a high-k dielectric. The method involves removing an exposed portion of a high-k dielectric layer from a substrate by wet etching with a solution comprising water, a strong acid, an oxidizing agent, and a fluorine compound. The etching solution provides selectivity towards the high-k film against insulating materials and polysilicon and is therefore useful in manufacturing FETs.

Abstract: A thin film transistor and method of making the same is disclosed in which a contact hole is formed with a flattened interface between openings in an inorganic material passivation layer and an organic material interlayer insulating film thereabove. The method includes etching an opening in the interlayer insulating film, using that opening as a mask for subsequently etching a self-aligned opening in the passivation layer, and again etching the interlayer insulating film in a develop back process to obtain a contact hole having a flattened inner sidewall.

Abstract: When a barrier metal disposed on a thin film resistor material is wet-etched to expose the underlying thin film resistor material as a thin film resistor, the wet etching is performed at first and second steps. The first step is performed using H2O2/NH4OH solution, and is stopped before the thin film resistor material is exposed. Then, the second step is performed using H2O2/H2O solution until the thin film resistor material is exposed with a desired length, thereby forming the thin film resistor.

Abstract: A method for using a monitor substrate to determine effectiveness of a cleaning operation is provided. The method includes selecting a substrate from a lot of substrates and inspecting a surface of the substrate to determine a roughness profile of the substrate. The monitor substrate is then processed through a cleaning operation, and the monitor substrate is patterned with die regions throughout. Each of the die regions has a plurality of areas defining distinct roughness simulations. The method the proceeds to inspecting the monitor substrate at one die region and at one of the plurality of areas in the one die region that most closely resembles the roughness profile of the substrate. The inspecting of the monitor substrate is configured to yield data regarding cleaning performance of the cleaning operation.

Abstract: In one illustrative embodiment, the method comprises providing a substrate having a process layer formed thereabove, performing a wet etching process comprised of a duration parameter on the process layer to reduce a thickness of the process layer, and adjusting the duration parameter of the wet etching process if the reduced thickness of the process layer after the etching process is complete is not within acceptable limits. In another illustrative embodiment, the present invention is directed to a system that is comprised of an etch tool for performing an etching process for a duration on a process layer formed above a semiconducting substrate to reduce a thickness of the process layer, and a controller for adjusting the duration of the etching process if the reduced thickness of the process layer after the etching process is performed is not within acceptable limits.

Abstract: A method for removing contamination on a semiconductor substrate is disclosed. The contamination contains at least one element belonging to one of 3A group, 3B group and 4A group of long-period form of periodic system of elements. The method comprises first and second process steps. The first process is wet processing the semiconductor substrate by first remover liquid that contains one of acid and alkali. The second process is wet processing the semiconductor substrate by second remover liquid that contains oxidizing reagent and one of hydrofluoric acid and salt of hydrofluoric acid.

Abstract: A chemical mechanical polishing slurry comprising a film forming agent, an oxidizer, a complexing agent and an abrasive, and a method for using the chemical mechanical polishing slurry to remove copper alloy, titanium, and titanium nitride containing layers from a substrate.

Abstract: A process for polishing a semiconductor wafer includes the steps of providing a plurality of wafers, forming a first layer, such as a barrier layer, over at least a portion of each wafer, and forming at least one layer including copper over at least a portion of each first layer. The process also includes the steps of providing a first polishing pad, providing a buffing pad, providing a plurality of operatively connected wafer carriers, and disposing a wafer within each of the wafer carriers. The process further includes the steps of disposing a first slurry composition on the first polishing pad and polishing a first wafer with the first polishing pad for a first length of time, in which the first polishing pad substantially removes the copper layer of the first wafer.

Abstract: A method of removing a photoresist layer on a semiconductor wafer starts with placing the semiconductor wafer into a dry strip chamber. A dry stripping process is performed to remove the photoresist layer on the semiconductor wafer. The semiconductor wafer is then placed on a rotator of a wet clean chamber and horizontally rotated. A first cleaning process is performed to remove polymers and organic components on a surface of the semiconductor wafer. Then a second cleaning process is performed as well to remove polymers and particles on the surface of the semiconductor wafer. By performing a third cleaning process, a first cleaning solution employed in the first cleaning process and a second cleaning solution employed in the second cleaning process are removed from the surface of the semiconductor wafer. Finally, the semiconductor wafer is spun dry at the end of the method.

Abstract: A two-step via cleaning process which removes metal polymer and oxide polymer residues from a via with substantially no damage to the via or underlying structures on a semiconductor substrate. The via is formed through a dielectric layer and a barrier layer which are disposed over a metal-containing trace, pad, or other such circuitry, wherein the metal-containing trace, pad, or other circuitry is disposed on a semiconductor substrate. When such a via is formed, the sidewalls of the via are coated with a residue layer. The residue layer generally has a distinct oxide polymer component and a distinct metal polymer component. The two-step cleaning process comprises first subjecting the residue layer to a nitric acid dip which removes the metal polymer component to expose the oxide polymer component. The oxide polymer component is then subjected to a phosphoric acid dip which removes the oxide polymer component.

Abstract: The surface cleaning method of semiconductor substrate comprises, the steps of, immersing a substrate of a first conductive type having Ge or SiGe mixing Ge and Si at least in the surface layer in a solution of hydrofluoric acid, and removing foreign matters from the surface of the substrate without overetching the surface of the substrate, pouring pure water on the substrate to wash away the solution of hydrofluoric acid applied at the step (a) from the surface of the substrate, and immersing the substrate in a solution of hydrogen peroxide, and removing foreign matters from the surface of the substrate without overetching the surface of the substrate.

Abstract: An antireflection coating (ARC) polymer layer is patterned by DUV (deep ultraviolet) lithography followed by an ARC open etching step and subsequent etching of the metal layer. Low resist consumption and hence steeper resist sidewalls are achieved by virtue of the ARC polymer intermediate layer being etched with a CF4 ARC open process with high selectivity with respect to the photoresist. The gas flows are set to the following ranges: CF4 35-45 sccm, CHF3 17-23 sccm, O2 5-7 sccm and Ar 80-120 sccm.

Abstract: For removing a photoresist formed on a semiconductor wafer by using an ozone-dissolved water, until just before a low temperature ozone-dissolved water generated by an ozone-dissolved water generator is discharged from a discharge nozzle onto a semiconductor wafer placed on a stage, the semiconductor wafer is heated to a predetermined temperature which is higher than ordinary temperatures. When the low temperature ozone-dissolved water having a high concentration of ozone is discharged onto the semiconductor wafer, the temperature of the ozone-dissolved water elevates upon the instant. Thus, the photoresist formed on the semiconductor wafer can be removed by a high temperature, high ozone concentration, ozone-dissolved water.

Abstract: A method for preventing or reducing corrosion of copper containing semiconductor features during chemical mechanical polishing (CMP) including providing a semiconductor wafer polishing surface including a copper layer overlying a copper filled anisotropically etched feature; polishing the semiconductor wafer polishing surface according to a first CMP process to remove at least a portion the copper layer to reveal a portion of an underlying barrier/adhesion layer; polishing the semiconductor wafer polishing surface according to a second CMP process including applying a neutralizing solution; polishing the semiconductor wafer polishing surface according to a third CMP process including applying a copper corrosion inhibitor solution; and, polishing the semiconductor wafer polishing surface according to at least a fourth CMP process to remove a remaining portion of the underlying barrier/adhesion layer.

Abstract: The present invention generally provides a method for preventing surface corrosion in an edge bead removal process. The method includes rinsing the substrate surface with a rinsing solution containing a rinsing agent and an inhibiting agent prior to removing the edge bead. The inhibiting agent bonds to the substrate surface and operates to prevent corrosion of the substrate surface after the rinsing process.

Abstract: An etching method for use in integrated circuit fabrication includes providing a metal nitride layer on a substrate assembly, providing regions of cobalt silicide on first portions of the metal nitride layer, and providing regions of cobalt on second portions of the metal nitride layer. The regions of cobalt and the second portions of the metal nitride layer are removed with at least one solution including a mineral acid and a peroxide. The mineral acid may be selected from the group including HCl, H2SO4, H3PO4, HNO3, and dilute HF preferably the mineral acid is HCl) and the peroxide may be hydrogen peroxide. Further, the removal of the regions of cobalt and the second portions of the metal nitride layer may include a one step process or a two step process. In the one step process, the regions of cobalt and the second portions of the metal nitride layer are removed with a single solution including the mineral acid and the peroxide.

Abstract: A light-emitting and/or light-receiving semiconductor body is produced with one or more semiconductor layers composed of GaAsxP1−x, where 0≦x<1. At least a portion of the surface of the semiconductor layer is first treated with an etching solution H2SO4:H2O2:H2O in a first etching step and then with hydrofluoric acid in a second etching step. The etching results in a surface roughness on the treated portion of the surface of the semiconductor layer.

Abstract: A method of fabricating a compound semiconductor device having an ohmic electrode of a low contact potential includes a first cleaning step of heating a compound semiconductor substrate containing a first conductivity type impurity in a temperature range of not more than 250° C. and etching its surface with hydrogen chloride at the temperature of not more than 250° C., and a second cleaning step of performing a radical hydrotreatment on the compound semiconductor substrate at a temperature not more than 250° C., after the first cleaning step. The first cleaning step removes an oxide film but leaves chlorine on the surface of the substrate. The second cleaning step removes the chlorine. The temperature of not more than 250° C. avoids damaging other layers such as an active layer on the opposite surface of the substrate.

Abstract: According to a method for manufacturing a semiconductor device having a junction boundary where SiGe of a first conductivity type and Si or SiGe of a second conductivity type come in contact with each other, a portion where the junction boundary is exposed on the surface is cleaned with a first solution containing hydrofluoric acid and is then cleaned with a second solution containing sulfuric acid.

Abstract: In pre-treating a surface of a substrate in a process of forming a narrowed thin film pattern on the surface of the substrate from a solution such as a plating liquid, a mask with an opening corresponding to the thin film pattern to be formed later is formed on the surface of the substrate. Then, by micronizing a pre-treating liquid such as a water, a plating liquid, an acidic liquid ad an alkaline liquid, an atmosphere containing microparticles having diameters smaller than the minimum distance of the opening of the mask is produced. The substrate is positioned into the atmosphere, and the microparticles of the pre-treating liquid are stuck on the surface of the substrate exposing to the lower part of the opening of the mask. In using a water as the pre-treating liquid, the substrate is positioned into an atmosphere containing moisture vapor and the water particles are stuck on the surface of the substrate through their condensation.

Abstract: A method for avoiding erosion of a conductor structure during a procedure of removing etching residues is provided. The method provides a semiconductor structure and the conductor structure formed therein. A cap layer is formed on the conductor structure and the semiconductor and a dielectric layer formed thereon. The dielectric layer and the cap layer are then etched to partially expose the conductor structure. The etching residues are removed with an amine-containing solution and the amine-containing solution is removed with an intermediate solvent to avoid erosion of the exposed conductor structure. As a key step of the present invention, the intermediate solvent comprises N-methylpyrrolidone or isopropyl alcohol and can protect the conductor structure from erosion.

Abstract: A silicon substrate is cleaned under the conditions that an etching amount of the first gate insulating film 106 lying in a region 102 where the adjacent circuit is to be formed is, by the film thickness, not less than 0.01 nm but not greater than 0.2 nm. The cleaning achieves a high reliability for a thick film gate insulating film of an adjacent circuit in a semiconductor device such as a SOC, which comprises the adjacent circuit in which a MOS having the thick film gate insulating film made of layers of a first silicon oxide film (a first gate insulating film) 106 and a second silicon oxide film (a second gate insulating film) 110 is placed and an internal circuit in which a MOS having a thin film gate insulating film made of a second silicon oxide film 110 is placed.

Abstract: A method of manufacturing a semiconductor device, having a resist-removing step which is improved so as not to etch a peripheral material and damage the peripheral material is provided. A resist pattern is formed on a substrate. Using the resist pattern as a mask, the substrate is etched. A surface-deteriorated layer of the resist pattern is removed by a first chemicals treatment. A bulk portion of the resist pattern is removed by a second chemicals treatment.

Abstract: The present invention is a method for evaluating the particulate evacuating effectiveness of a wafer cleaning operation in which a cleaning liquid flows in a cleaning tank in contact with wafers. A test wafer and a seed wafer with contaminant particles on its surface are immersed into the cleaning liquid within the cleaning tank. The test wafer, contaminant particles and cleaning liquid are selected such that the zeta potentials which develop at the surface of the test wafer and contaminant particles liberated from the seed wafer into the cleaning liquid are of opposite polarity. The opposite zeta potentials enhance the deposition of the seed particles onto the surface of the test wafer. The test wafer is removed from the cleaning liquid, dried and inspected to produce a plot of the number and location of the contaminant particles deposited on the test wafer.

Abstract: A process is described for recycling test wafers used for quality control or damaged wafers used in the context of chip production by regenerative removal of the previously applied layers. The method is based on the object of developing a cost-effective, environmentally friendly and time-saving regeneration method. The object is achieved by removing the applied layers by wet blasting using a specific blast material.

Abstract: After forming a processed film onto the underlying film formed on the substrate, the processed film is dry etched using a mask pattern so as to form an etched pattern. After the reaction product deposited on a wall of the etched pattern is removed by using the first cleaning solution having relatively low power to etch the processed film and the second cleaning solution having relatively high power to etch the processed film in that order, the etched pattern or its vicinity is rinsed with water.

Abstract: A method of processing a semiconductor wafer sliced from a monocrystalline ingot comprises at least the steps of chamfering, lapping, etching, mirror-polishing, and cleaning. In the etching step, alkali etching is first performed and then acid etching, preferably reaction-controlled acid etching, is performed. The etching amount of the alkali etching is greater than the etching amount of the acid etching. Alternatively, in the etching step, reaction-controlled acid etching is first performed and then diffusion-controlled acid etching is performed. The etching amount of the reaction-controlled acid etching is greater than the etching amount of the diffusion-controlled acid etching.

Abstract: An article is disclosed having a non-planar surface with a high-resolution pattern formed thereon, particularly a distributed-feedback (DFB) ridge waveguide laser. An elastomeric member having relief patterns on its surface is used to print or mold a pattern directly onto the non-planar surface of the waveguide. A range of materials disposed on such non-planar surfaces can thus be patterned at high resolution to provide devices with sub-micron features at low cost with potential applications in optoelectronics. For example, a plastic laser based on molded organic gain materials may be made.

Abstract: The present invention provides a method of preventing the dishing phenomenon occurring atop a dual damascene structure on a semiconductor wafer. The semiconductor has a substrate, a first dielectric layer positioned on the substrate, a dual damascene hole positioned in the first dielectric layer through to the surface of the substrate, a barrier layer covering the surface of the first dielectric layer and both the surface of the walls and bottom of the dual damascene hole, and a copper layer positioned on the barrier layer and filling the dual damascene hole to form the dual damascene structure. The method first involves performing a first chemical mechanical polishing (CMP) process to remove portions of the copper layer down to the surface of the barrier layer. A photoresist layer is then formed atop the dual damascene structure to remove portions of the barrier layer uncovered by the photoresist layer.

Abstract: An etching method and an etching apparatus are provided. Silicon (Si) from surfaces semiconductor wafers W dissolves into an etching liquid E stored in a process bath 10. On detection of the concentration of silicon by a concentration sensor 50, the etching liquid E in the process bath 10 is discharged while leaving a part of the etching liquid when the Si concentration in the etching liquid E reaches a designated concentration. After that, a new etching liquid of substantially equal to an amount of the discharged etching liquid E is supplied into the process bath 10 and added to the etching liquid remaining in the bath 10. Consequently, it is possible to restrict the etching rate just after the exchange of etching liquid from rising excessively.

Abstract: A silicon etching method includes providing a substrate assembly including an exposed silicon region and an exposed oxide region. An etch composition including an ammonium fluoride component, an inorganic acid component, and an oxidizing agent is also provided. The etch composition has a pH in the range of about 7.0 to about 8.0. The substrate assembly is exposed to the etch composition. Exposing the substrate assembly to the etch composition may result in etching the exposed silicon region at an etching rate that is greater than about 3 times the etching rate of the exposed oxide region and/or etching the silicon region at an etch rate greater than about 9 Å/minute. The etching method may be used in forming isolation structures. Further, etch compositions for performing the desired etch are provided.

Abstract: A method of increasing the selectivity of silicon nitride deposition. A substrate is provided. A silicon oxide layer is formed over a portion of the substrate. Ammonia NH3 is passed over the silicon oxide layer and the substrate surface for a definite period to perform a surface treatment. Silicon nitride is subsequently deposited over the substrate and the silicon oxide layer.

Abstract: A silicon substrate is cleaned under the conditions that an etching amount of the first gate insulating film 106 lying in a region 102 where the adjacent circuit is to be formed is, by the film thickness, not less than 0.01 nm but not greater than 0.2 nm. The cleaning achieves a high reliability for a thick film gate insulating film of an adjacent circuit in a semiconductor device such as a SOC, which comprises the adjacent circuit in which a MOS having the thick film gate insulating film made of layers of a first silicon oxide film (a first gate insulating film) 106 and a second silicon oxide film (a second gate insulating film) 110 is placed and an internal circuit in which a MOS having a thin film gate insulating film made of a second silicon oxide film 110 is placed.

Abstract: The present invention relates to a method of removing a photo-resist layer from a semiconductor wafer. The semiconductor wafer comprises an inter-metal dielectric layer (IMD), and a photo-resist layer positioned on the IMD. The method comprises performing a dry cleaning process by injecting a nitrogen-containing gas into an oxygen-free environment and utilizing a plasma reaction to remove most of the photo-resist layer, and performing a wet cleaning process to completely remove the photo-resist layer.

Abstract: Semiconductor substrates are contacted with a deionized water solution containing an acidic material.

Abstract: A method of processing a semiconductor wafer sliced from a monocrystalline ingot comprises at least the steps of chamfering, lapping, etching, mirror-polishing, and cleaning. In the etching step, alkali etching is first performed and then acid etching, preferably reaction-controlled acid etching, is performed. The etching amount of the alkali etching is greater than the etching amount of the acid etching. Alternatively, in the etching step, reaction-controlled acid etching is first performed and then diffusion-controlled acid etching is performed. The etching amount of the reaction-controlled acid etching is greater than the etching amount of the diffusion-controlled acid etching.

Abstract: In order to clean a porous body in a short time without causing any change in its structure, in a cleaning method of cleaning a porous body formed by anodization, the porous body is cleaned after the anodization is completed, with a cleaning solution containing at least one of an alcohol and acetic acid.

Abstract: A method for fabricating MEMS wherein a structural member is released without using a sacrificial layer. In one embodiment, the method comprises forming a buried hydrogen-rich layer in a semiconductor substrate, defining a release structure in the semiconductor substrate above the buried hydrogen-rich layer, and separating at least a portion of the release structure from the semiconductor substrate by cleaving the semiconductor substrate at the buried hydrogen-rich layer. The method can be used to fabricate hybrid devices wherein a MEMS device and a semiconductor device are formed on the same chip.

Abstract: A method for forming shallow trench isolations includes the steps of defining a wafer substrate, forming a silicon dioxide insulating layer on the substrate, depositing a silicon nitride layer on the silicon dioxide insulating layer, and forming at least one trench in the substrate through the silicon dioxide and silicon nitride layers. The method also includes the steps of depositing a silicon dioxide layer over the silicon nitride layer and in the trench, removing the silicon dioxide layer deposited over the silicon nitride layer, anisotropically etching the silicon dioxide layer to produce silicon dioxide sidewalls in the trench contiguous with the silicon nitride layer, isotropically etching to remove the sidewalls and removing the silicon nitride layer.

Abstract: A method of manufacturing a semiconductor device in which a cobalt silicide layer is formed on a semiconductor substrate. In the method, the semiconductor substrate is prepared, and cobalt is deposited on the semiconductor substrate by sputtering while heating the semiconductor substrate at a temperature approximately equal to 200 degrees Celsius. Thereafter, cobalt is deposited on the semiconductor substrate by sputtering while heating the semiconductor substrate at a temperature between 300 degrees Celsius and 400 degrees Celsius without exposing the semiconductor substrate to the atmosphere. Preferably, the semiconductor substrate is thereafter rapid thermal annealed at a temperature equal to or higher than 500 degrees Celsius in nitrogen atmosphere for a predetermined time. Further, at least a part of cobalt portion or cobalt oxide portion on the semiconductor substrate is removed by wet etching.

Abstract: A method for removing a formation of oxide of titanium that is generated as a byproduct of a process that forms cobalt disilicide within an insulated-gate field effect transistor (FET). The method applies a chemical reagent to the FET at a predetermined temperature, and for a predetermined period of time, necessary for removing the formation, wherein the reagent does not chemically react with the cobalt disilicide. A reagent that accomplishes this task comprises water (H2O), ammonium hydroxide (NH4OH), and hydrogen peroxide (H2O2), wherein the NH4OH and the H2O2 each comprise approximately 4% of the total reagent volume. An effective temperature is 65° C. combined with a 3 minute period of application.

Abstract: There is provided a method for manufacturing a semiconductor device which can provide global planarization between a cell array region and a periphery region by a simple process. An interlevel dielectric layer is formed over the entire surface of a semiconductor substrate where a global step difference exists between a cell array region and a periphery region. A first material layer serving as a stopper is formed on the interlevel dielectric layer. A contact hole partially exposing the semiconductor substrate of the cell array region is formed by patterning the first material layer and the interlevel dielectric layer. A conductive layer is formed over the entire surface of the semiconductor substrate where the contact hole is formed. Global planarization is provided between the cell array region and the periphery region by performing a chemical mechanical polishing (CMP) process on the semiconductor substrate where the conductive layer is formed.

Abstract: A method for controlling striations and CD loss in a plasma etching method is disclosed. During the etching process, the substrate of semiconductor material to be etched is exposed first to plasma under a low power strike and subsequently to a conventional high power strike. CD loss has been found to be reduced by about 400 Angstroms and striations formed in the contact holes are reduced.

Abstract: A method of fabricating a compound semiconductor device having an ohmic electrode of a low contact potential and an apparatus for fabricating a compound semiconductor device are obtained. The method comprises a substrate cleaning step including a first cleaning step of heating a compound semiconductor substrate containing a first conductivity type impurity in a temperature range of not more than 250° C. for etching its surface with hydrogen chloride and a second cleaning step of performing a radical hydrotreatment on the compound semiconductor substrate etched with hydrogen chloride after the first cleaning step.

Abstract: A top IC die is removed from a bottom IC die in a multichip IC package while substantially preserving interconnect of the bottom IC die for proper fault isolation during testing of the multichip IC package. The top IC die is attached to the bottom IC die with a die attach material within the multichip IC package. The top IC die has a first area that is smaller than a second area of the bottom IC die, and the top IC die is disposed inward from any edge of the bottom IC die such that a perimeter area of the bottom IC die is outside the top IC die. A predetermined area of the top IC die is exposed with the predetermined area being smaller than the first area of the top IC die. The predetermined area is disposed inward from any edge of the top IC die. The first area of the top IC die outside the predetermined area remains covered, and the perimeter area of the bottom IC die remains covered.

Abstract: A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an alignment mark area of a silicon wafer in process during the formation of integrated circuits thereon. The process comprising the steps of aligning said area of said wafer, such as an alignment mark on the wafer, to an etchant dispensing apparatus, placing the surface of the wafer adjacent at least a portion of an annular portion of the etchant dispensing apparatus, dispensing at least one etchant onto said area of said wafer, such as an alignment mark, and removing the at least one etching from the wafer.

Abstract: A method of performing a nitride strip process step for a plurality of semiconductor wafers includes partially draining the chemical solution within a chemical bath after every nitride strip in which the oxide etch rate is within a specified range. If the oxide etch rate is above the specified range, the partial drain is performed. Once the etch rate falls within the range, the partial drain is performed every time a bath increment signal is received. If the etch rate falls below the specified range, then the bath is completely drained so that the solution may be replaced with fresh chemicals. While it is generally desirable to minimize the amount of field oxide that is removed during the nitride strip process step, the field oxide etch should be maintained at a specified level because, when below that level, the chemical solution silicon content is too high risking the possibility that the silicon will precipitate and cause undesirable effects including coating the wafers being stripped of nitride.

Abstract: A chemical mechanical polishing slurry precursor comprising urea, a second oxidizer, an organic acid, and an abrasive, and a method for using the chemical mechanical polishing slurry precursor to prepare a chemical mechanical polishing slurry with a first oxidizer and thereafter using the slurry to remove titanium, titanium nitride, and an aluminum alloy containing layers from a substrate.

Abstract: A process for producing a semiconductor device includes the following sequential steps: producing a semiconductor body having an AlxGa1−xAs layer with an upper surface, where x≦0.40; applying a contact metallization made of a non-noble metallic material to the AlxGa1−xAs layer; precleaning a semiconductor surface to produce a hydrophilic semiconductor surface; roughening the upper surface of the AlxGa1−xAs layer by etching with an etching mixture of hydrogen peroxide ≧30% and hydrofluoric acid ≧40% (1000:6) for a period of from 1 to 2.5 minutes; and re-etching with a dilute mineral acid. According to another embodiment, 0≦x≦1 and the upper surface of the AlxGa1−xAs layer is roughened by etching with nitric acid 65% at temperatures of between 0° C. and 30° C.