Sequential Application Of Etchant Patents (Class 438/749)
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Patent number: 8222160Abstract: According to one embodiment, a via and trench are formed in a semiconductor structure. The via and the trench are suitable for having a metal-based wire placed therein by damascene, dual damascene, plating and other suitable techniques. The via is etched into a dielectric layer of a semiconductor structure comprising a base cap layer, the dielectric layer formed over the base cap layer, and a hardmask formed over the dielectric layer. The via is filled with a sacrifice material, where the sacrifice material contains a metal or a metal compound, where the sacrifice material additionally forms a sacrifice layer over the hardmask layer. The sacrifice material placed in the via does not contain a material or film containing a Si—O bond. The sacrifice material is used as a support for a photomask that is placed over the sacrifice layer, where the photomask is developed to have a trench pattern formed therein.Type: GrantFiled: November 30, 2010Date of Patent: July 17, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Yoshihiro Uozumi
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Patent number: 8173462Abstract: A manufacturing method of a nitride crystalline film includes following steps. First, a substrate is provided. Next, a first nitride crystalline film is formed on the substrate. A patterned mask is then formed on the first nitride crystalline film. The patterned mask covers a first part of the first nitride crystalline film and exposes a second part of the first nitride crystalline film. Afterwards, the second part is etched, and the first part is maintained. After that, the patterned mask is removed. The first part is then etched to form a plurality of nitride crystal nuclei. Next, a second nitride crystalline film is formed on the substrate, and the second nitride crystalline film is made to cover the nitride crystal nuclei. A nitride film and a substrate structure are also provided.Type: GrantFiled: March 6, 2009Date of Patent: May 8, 2012Assignee: National Central UniversityInventors: Cheng-Huang Kuo, Chi-Wen Kuo, Chun-Ju Tun
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Patent number: 8148271Abstract: A substrate processing apparatus comprises a processing chamber for storing a boat supporting multiple substrates and for processing the multiple substrates, a heater unit installed around the processing chamber for heating the substrates, and a coolant gas supply nozzle including a pipe section extending perpendicular to a main surface of the substrate supported in the boat stored in the processing chamber, and a spray hole formed on the pipe section for spraying coolant gas to at least two of the multiple substrates, wherein the coolant gas supply nozzle is formed so that the cross sectional area of the pipe section in the area where the spray hole is formed is larger than the total opening area of the spray hole.Type: GrantFiled: July 19, 2006Date of Patent: April 3, 2012Assignee: Hitachi Kokusai Electric Inc.Inventors: Masaaki Ueno, Akira Hayashida, Masakazu Shimada, Takenori Oka
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Patent number: 8142669Abstract: An electromechanical element includes a mechanically movable element through a hollow formed on a substrate, and a plurality of holes formed in the movable element. In the electromechanical element, the plurality of holes are arranged such that at least two holes are in a same line, at least one hole is in another line located adjacent to the one line with at least two holes, and a distance between one of the holes arranged in the same line and the other hole located at the closest position from the one of the two holes arranged in the same line is longer than a distance between the holes adjacently arranged in the same line.Type: GrantFiled: February 19, 2007Date of Patent: March 27, 2012Assignee: Sony CorporationInventors: Akira Akiba, Shun Mitarai
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Patent number: 8138002Abstract: A convex part formation method of forming a convex part in parallel with a <110> direction of a backing on the backing having a {100} face as the top surface thereof, includes: (a) forming a mask layer in parallel with the <110> direction on the backing; (b) etch the backing so as to form a convex-part upper layer whose sectional shape on a cutting plane corresponding to a {110} face is an isosceles trapezoid, the base of which is longer than the upper side thereof, and the side surface of which has an inclination of ?U; and (c) further etching the backing so as to form a convex-part lower layer whose sectional shape on the cutting plane corresponding to the {110} face is an isosceles trapezoid, the base of which is longer than the upper side thereof, and the side surface of which has an inclination of ?D (where ?D??U).Type: GrantFiled: August 11, 2009Date of Patent: March 20, 2012Assignee: Sony CorporationInventors: Kiyotaka Yashima, Yoshinari Kiwaki, Kamada Michiru, Sachio Karino, Hironobu Narui, Nobukata Okano
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Patent number: 8075702Abstract: In an inventive resist removing method, sulfuric acid and hydrogen peroxide water are supplied to a surface of a substrate to remove a resist from the substrate surface. Thereafter, hydrogen peroxide water is supplied to the substrate surface to remove the sulfuric acid from the substrate surface.Type: GrantFiled: August 15, 2008Date of Patent: December 13, 2011Assignee: Dainippon Screen Mfg. Co., Ltd.Inventor: Masayuki Wada
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Patent number: 8058181Abstract: The current invention provides methods for performing a cleaning process that provides greater cleaning efficiency with less damage to device structures. After etching and photoresist stripping, a first plasma clean is performed. The first plasma clean may comprise one or more steps. Following the first plasma clean, a first HO based clean is performed. The first HO based clean may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. Following the first HO based clean, a second plasma clean is performed, which may comprise one or more steps. A second HO based clean follows the second plasma clean, and may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. For plasma processes, an RF, generated plasma, a microwave generated plasma, an inductively coupled plasma, or combination may be used.Type: GrantFiled: July 13, 2009Date of Patent: November 15, 2011Assignee: Novellus Systems, Inc.Inventors: David L. Chen, Yuh-Jia Su, Eddie Ka Ho Chiu, Maria Paola Pozzoli, Senzi Li, Giuseppe Colangelo, Simone Alba, Simona Petroni
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Patent number: 7998876Abstract: A method of producing a semiconductor element includes the steps of forming a wiring portion layer on a substrate; forming an interlayer insulation layer over the substrate and the wiring portion layer, in which a third insulation film, a second insulation film, and a first insulation film are laminated in this order from the substrate; forming a mask pattern on the first insulation film; removing a contact hole forming area of the first insulation film through a wet etching process; removing a contact hole forming area of the second insulation film through an etching process; removing a contact hole forming area of the third insulation film through an etching process; and a contact hole forming step of forming a contact hole in the interlayer insulation layer so that a surface of the wiring portion layer is exposed.Type: GrantFiled: March 11, 2010Date of Patent: August 16, 2011Assignee: Oki Semiconductor Co., Ltd.Inventor: Toshiyuki Orita
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Publication number: 20110186910Abstract: There is disclosed methods of making photosensitive devices, such as flexible photovoltaic (PV) devices, through the use of epitaxial liftoff. Also described herein are methods of preparing flexible PV devices comprising a structure having a growth substrate, wherein the selective etching of protective layers yields a smooth growth substrate that us suitable for reuse.Type: ApplicationFiled: September 9, 2010Publication date: August 4, 2011Inventors: Stephen R. Forrest, Jeramy Zimmerman, Kyusang Lee, Kuen-Ting Shiu
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Patent number: 7943515Abstract: A structure and a method of manufacturing a three dimensional memory using a number of bit line masks that is less than the number of device layers. A first bit line mask is used to form a first bit line layer in a first device level. The first bit line layer comprises first bit lines. The first bit line mask is also used to form a second bit line layer in a second device level. The second bit line layer comprises second bit lines. The first bit lines and the second bit lines have different electrical connections to a bit line connection level despite employing the same mask pattern.Type: GrantFiled: September 9, 2008Date of Patent: May 17, 2011Assignee: SanDisk 3D LLCInventor: Roy E. Scheuerlein
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Patent number: 7927498Abstract: A solar cell and a method of texturing a solar cell are disclosed. The method includes coating an ink containing metal particles on a surface of a substrate, drying the ink to attach the metal particles to the surface of the substrate, and differentially etching the surface of the substrate using the metal particles as a catalyst to form an uneven portion.Type: GrantFiled: February 13, 2009Date of Patent: April 19, 2011Assignee: LG Electronics Inc.Inventors: Younggu Do, Junyong Ahn, Gyeayoung Kwag
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Patent number: 7884027Abstract: A method of manufacturing a semiconductor device includes subjecting a semiconductor substrate having an aluminum film formed thereabove to a processing to at least partially expose a surface of the aluminum film, and carrying out a surface processing to remove an after-processing residue that remains on the exposed surface of the aluminum film. The surface processing includes treating the exposed surface of the aluminum film with a first liquid chemical containing an anion component and then with an alkaline, second liquid chemical.Type: GrantFiled: October 31, 2006Date of Patent: February 8, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihiro Uozumi, Takashi Hirayama, Akira Kugita
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Cleaning solution for silicon surface and methods of fabricating semiconductor device using the same
Patent number: 7879735Abstract: A cleaning solution and methods of fabricating semiconductor devices using the same are provided. A cleaning solution used for cleaning a silicon surface and methods of fabricating a semiconductor device using the same are also provided. The cleaning solution may include 0.01 to 1 wt % of fluoric acid, 20 to 50 wt % of oxidizer and 50 to 80 wt % of water. The cleaning solution may further include 1 to 20 wt % of acetic acid. The cleaning solution may be used to clean a silicon surface exposed during fabrication processes of a semiconductor device. The cleaning solution may reduce damage of other material layers (e.g., a tungsten layer or a silicon oxide layer) and enable the silicon surface to be selectively etched.Type: GrantFiled: January 23, 2007Date of Patent: February 1, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Yong Kim, Chang-Ki Hong, Woo-Gwan Shim -
Patent number: 7851370Abstract: A patterning method is provided. In the patterning method, a film is formed on a substrate and a pre-layer information is measured. Next, an etching process is performed to etch the film. The etching process includes a main etching step, an etching endpoint detection step, an extension etching step and an over etching step. An extension etching time for performing the extension etching step is set within 10 seconds based on a predetermined correlation between an extension etching time and the pre-layer information, so as to achieve a required film profile.Type: GrantFiled: September 25, 2007Date of Patent: December 14, 2010Assignee: United Microelectronics Corp.Inventors: Lung-En Kuo, Jiunn-Hsiung Liao, Min-Chieh Yang
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Patent number: 7833905Abstract: In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light.Type: GrantFiled: May 5, 2009Date of Patent: November 16, 2010Assignee: Renesas Electronics Corp.Inventors: Hiraku Chakihara, Mitsuhiro Noguchi, Masahiro Tadokoro, Naonori Wada, Akio Nishida
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Patent number: 7790625Abstract: A method of manufacturing a semiconductor device includes preparing a semiconductor wafer, forming a semiconductor function element on the semiconductor wafer, drying the semiconductor wafer after forming the semiconductor function element by using an isopropyl alcohol vapor, heating the semiconductor wafer after drying the semiconductor wafer, and performing a cleaning on the semiconductor wafer after heating the semiconductor wafer by using a fuming nitric acid.Type: GrantFiled: March 6, 2008Date of Patent: September 7, 2010Assignee: Oki Semiconductor Co., Ltd.Inventor: Shinsuke Miki
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Patent number: 7776755Abstract: The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes applying a first etching process to the substrate to remove a polysilicon layer and a metal gate layer on the substrate; applying a diluted hydrofluoric acid (HF) to the substrate to remove polymeric residue; thereafter applying to the substrate with a cleaning solution including hydrochloride (HCl), hydrogen peroxide (H2O2) and water (H2O); applying a wet etching process diluted hydrochloride (HCl) to the substrate to remove a capping layer; and applying to the substrate with a second etching process to remove a high k dielectric material layer.Type: GrantFiled: December 18, 2008Date of Patent: August 17, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jr Jung Lin, Yih-Ann Lin, Ryan Chia-Jen Chen
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Patent number: 7776756Abstract: An etching apparatus includes a chamber containing an etching solution including first and second components and water, a concentration of the water in the etching solution is at a specified level or lower; a circulation path circulating the etching solution; a concentration controller sampling the etching liquid from the circulation path and controls concentrations of the etching solution respectively; and a refilling chemical liquid feeder feeding a refilling chemical liquid including the first component having a concentration higher than the first component in the etching solution.Type: GrantFiled: July 30, 2007Date of Patent: August 17, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hisashi Okuchi, Hiroyasu Iimori, Mami Saito, Yoshihiro Ogawa, Hiroshi Tomita, Soichi Nadahara
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Patent number: 7749910Abstract: The invention provides a method for reducing the roughness of a free surface of a semiconductor wafer that includes removing material from the free surface of the wafer to provide a treated wafer, and performing a first rapid thermal annealing on the treated wafer in a pure argon atmosphere to substantially reduce the roughness of the free surface of the treated wafer. The material removal is selected and conducted to improve the effectiveness of the subsequent rapid thermal annealing in reducing the roughness of the free surface of the treated wafer.Type: GrantFiled: July 27, 2005Date of Patent: July 6, 2010Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Eric Neyret, Ludovic Ecarnot, Christophe Maleville
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Patent number: 7731801Abstract: In the ozone water treatment process, the silicon wafer is treated with the first ultra-pure water that includes ozone. The first ultra-pure water is refined by the ultraviolet ray sterilization method. The first ultra-pure water includes total organic carbon content of more than 1 ?g/liter and not more than 20 ?g/liter, so that the silicon wafer of the predetermined degree of cleanliness is obtained. The silicon wafer is treated by using the second ultra-pure water that has a lower TOC value than the first ultra-pure water in the ultra-pure water rinsing process (including the chemical solution cleaning process as required). The second ultra-pure water is refined by the ultraviolet ray oxidization method, and includes total organic carbon content with a concentration of 1 ?g/liter or less. Thus the silicon wafer of the predetermined degree of cleanliness is obtained.Type: GrantFiled: August 30, 2005Date of Patent: June 8, 2010Assignee: Sumco CorporationInventors: Makoto Takemura, Yasuo Fukuda, Kazuaki Souda, Junichiro Iwahashi, Koichi Okuda
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Patent number: 7696098Abstract: A unipolar semiconductor laser is provided in which an active region is sandwiched in a guiding structure between an upper and lower cladding layer, the lower cladding layer being situated on a semiconducting substrate. The unipolar semiconductor laser comprises a raised ridge section running from end to end between end mirrors defining the laser cavity. The ridge section aids in optical and electrical confinement. The ridge waveguide is divided in a plurality of cavity segments (at least two). Lattice structures can be arranged on and/or adjacent to these cavity segments. Each cavity segment is in contact with upper metallic electrodes. A metallic electrode coupled to the bottom surface of the semiconducting substrate facilitates current injection through the device.Type: GrantFiled: October 12, 2007Date of Patent: April 13, 2010Assignee: Nanoplus GmbHInventors: Marc Fischer, Alfred Forchel
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Patent number: 7687376Abstract: A method of manufacturing a vertical GaN-based LED comprises preparing an n-type GaN substrate; sequentially forming an active layer and a p-type nitride semiconductor layer on the n-type GaN substrate through an epitaxial growth method; forming a p-electrode on the p-type nitride semiconductor layer; wet-etching the lower surface of the n-type GaN substrate so as to reduce the thickness of the n-type GaN substrate; forming a flat n-type bonding pad on the wet-etched lower surface of the n-type GaN substrate, the n-type bonding pad defining an n-electrode formation region; and forming an n-electrode on the n-type bonding pad.Type: GrantFiled: April 6, 2007Date of Patent: March 30, 2010Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Pun Jae Choi, Jong Ho Lee
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Patent number: 7651952Abstract: Wafer structures and associated methods of fabrication are described. The wafer structures are fabricated to have aerodynamic shapes. Even if the structures on the wafer are fragile, the aerodynamic shapes of the structures create less resistance to a fluid flow of a cleaning process, and are less likely to be damaged by the cleaning process. Also, the aerodynamic shape of the structures allows a fluid flow to be directed toward the wafer from a single angle to effectively clean the wafer.Type: GrantFiled: December 19, 2007Date of Patent: January 26, 2010Assignee: Hitachi Global Storage Technologies Netherlands, B.V.Inventors: Christopher W. Bergevin, Shawn M. Collier Hernandez
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Patent number: 7595266Abstract: In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light.Type: GrantFiled: June 26, 2008Date of Patent: September 29, 2009Assignee: Renesas Technology Corp.Inventors: Hiraku Chakihara, Mitsuhiro Noguchi, Masahiro Tadokoro, Naonori Wada, Akio Nishida
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Patent number: 7591959Abstract: An etchant for removing materials with a plurality of selectivities exhibits a first etch selectivity at a first temperature and a second etch selectivity at a second temperature. The etchant may include phosphoric acid, fluoboric acid, or sulfuric acid. The materials that the etchant is configured to remove may include dielectric materials, such as silicon nitride and silicon oxide. The first temperature may be about 175° C. and the second temperature may be about 155° C.Type: GrantFiled: January 4, 2006Date of Patent: September 22, 2009Assignee: Micron Technology, Inc.Inventors: Li Li, Don L. Yates
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Patent number: 7569492Abstract: The current invention provides methods for performing a cleaning process that provides greater cleaning efficiency with less damage to device structures. After etching and photoresist stripping, a first plasma clean is performed. The first plasma clean may comprise one or more steps. Following the first plasma clean, a first HO based clean is performed. The first HO based clean may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. Following the first HO based clean, a second plasma clean is performed, which may comprise one or more steps. A second HO based clean follows the second plasma clean, and may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. For plasma processes, an RF generated plasma, a microwave generated plasma, an inductively coupled plasma, or combination may be used.Type: GrantFiled: April 28, 2008Date of Patent: August 4, 2009Assignees: Novellus Systems, Inc., STMicroelectonics S.R.L.Inventors: David L. Chen, Yuh-Jia Su, Eddie Ka Ho Chiu, Maria Paola Pozzoli, Senzi Li, Giuseppe Colangelo, Simone Alba, Simona Petroni
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Patent number: 7557042Abstract: Floating gates are formed in two separate polysilicon depositions steps resulting in distinct portions. The first formed portions are between isolation regions. A thick insulator is formed over the isolation regions and floating gate portions. The thick insulator is patterned to leave fences over the isolation regions. A thinning process, an isotropic etch in this example, is applied to these fences to make them thinner. Polysilicon sidewall spacers are formed on the sides of these fences. These sidewall spacers become the second portion of the floating gate. These second portions have the desired shape for significantly increasing the capacitance to the subsequently formed control gates, thereby reducing the gate voltage required for programming and erasing made by a relatively robust process.Type: GrantFiled: June 28, 2004Date of Patent: July 7, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Chi Nan Brian Li, Cheong M. Hong, Rana P. Singh
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Patent number: 7550183Abstract: A method for manufacturing a liquid crystal display which employs an active matrix substrate including a plurality of pixels arranged in matrix on a substrate and reflecting electrodes formed in the pixels, respectively. The method comprises (a) a laminated conductive film formation step of sequentially forming a conductive metal film and an amorphous transparent conductive film on a substrate to form a laminated conductive film and (b) a reflecting electrode formation step of patterning the laminated conductive film into a reflecting electrode, wherein the step (b) includes a first etching step of etching the conductive metal film and the amorphous transparent conductive film simultaneously and a second etching step of etching the amorphous transparent conductive film only.Type: GrantFiled: February 18, 2005Date of Patent: June 23, 2009Assignee: Sharp Kabushiki KaishaInventors: Kazuhiro Ishizuka, Takashi Fujikawa, Takehiko Sakai
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Patent number: 7541293Abstract: According to the present invention, a process for changing the form of a processed film is performed to planarize it before the processed film which is formed on a wafer is processed in a manufacturing process of a semiconductor device. As the process for changing the form of the processed film, there may be exemplified a single wafer type wet etching process. The compatibility of the processed film with processing means is taken into consideration and, for instance, the wet etching process is applied to the processed film so as to eliminate parts incompatible with the processing means, so that a distribution in-plane of the processed film is previously improved.Type: GrantFiled: October 25, 2001Date of Patent: June 2, 2009Assignees: Sony Corporation, SEZ Japan, Inc.Inventors: Hayato Iwamoto, Kei Kinoshita
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Patent number: 7534728Abstract: In the production process of an SOI substrate using a hydrogen ion implantation method, a process is provided for cleaning the substrate which can prevent formation of voids when bonding substrates and formation of blistering after exfoliation. In the process for cleaning, cleaning of the substrate is performed before performing hydrogen ion implantation. As the cleaning method, one or more of a combination selected from the group consisting of SC-1 cleaning, SC-1 cleaning+SC-2 cleaning, HF/O3 cleaning, and HF cleaning+O3 cleaning, can be used.Type: GrantFiled: April 12, 2006Date of Patent: May 19, 2009Assignee: Sumco CorporationInventors: Hideki Nishihata, Tatsumi Kusaba, Nobuyuki Morimoto
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Patent number: 7507616Abstract: A method of manufacturing a flexible display is provided, which includes forming a gate line including a gate electrode on a substrate, sequentially depositing a gate insulating layer covering the gate line, and a semiconductor layer, firstly etching the semiconductor layer; secondly etching the semiconductor layer, forming a data line including a source electrode, and a drain electrode on the semiconductor layer and the gate insulating layer; and forming a pixel electrode connected to the drain electrode.Type: GrantFiled: January 3, 2006Date of Patent: March 24, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Hyun Seo, Tae-Young Choi
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Patent number: 7456113Abstract: The present invention is a method of use of a novel cleaning solution in a single wafer cleaning process. According to the present invention the method involves using a cleaning solution in a single wafer mode and the cleaning solution comprises at least ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), water (H2O) and a chelating agent. In an embodiment of the present invention the cleaning solution also contains a surfactant. Moreover, the present invention also teaches a method of combining an ammonia hydroxide, hydrogen peroxide, and chelating agent step with a short HF step in a fashion that minimizes process time in a way that the entire method removes aluminum and iron contamination efficiently without etching too much oxide. The single wafer cleaning processes may also be used to increase the yield of high-grade reclaimed wafers.Type: GrantFiled: June 6, 2005Date of Patent: November 25, 2008Assignee: Applied Materials, Inc.Inventors: Ronald Rayandayan, Steven Verhaverbeke, Hong Wang
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Patent number: 7431860Abstract: A method for etching a pattern in a material in precise target areas comprising depositing selectively onto the material droplets of a substance for dissolving or reacting chemically with the material. Droplets may be deposited from a print head of the type having a nozzle from which the material may be ejected as a series of droplets, such as an ink jet print head. In a preferred application, a series of ridges can be etched from an organic insulator layer overlying a photoemissive organic polymer. A conductive layer is then deposited and the ridges of organic insulator are dissolved by solvent washing to provide an array of conductive stripes which can be used as a cathode for an electroluminescent display device. In combination, both anode and cathode can be fabricated for a display device without the need for photolithography, which is particularly advantageous for the fabrication of large area display devices.Type: GrantFiled: October 15, 2001Date of Patent: October 7, 2008Assignee: Seiko Epson CorporationInventor: Takeo Kawase
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Patent number: 7419914Abstract: A method for fabricating a semiconductor device with a borderless via/wiring structure includes the steps of performing borderless via etching using a resist mask to form a contact hole in an interlevel dielectric layer over a semiconductor substrate so as to expose two different metal materials of lower layer patterns in the contact hole; and performing plasma irradiation using an H2O-containing gas prior to a wet process when removing the resist mask.Type: GrantFiled: February 21, 2006Date of Patent: September 2, 2008Assignee: Fujitsu LimitedInventor: Naoki Nishida
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Patent number: 7405165Abstract: A dual-tank etch method which is suitable for the stripping of a silicon nitride layer from a pad oxide layer provided on a substrate, and etching of the pad oxide layer to a desired target thickness, is disclosed. The method includes providing a first processing tank containing a silicon nitride-stripping chemical; stripping the silicon nitride layer from the pad oxide layer by placing the substrate in the first processing tank; providing a second processing tank containing an oxide-etching chemical; and etching the pad oxide layer to the desired target thickness by placing the substrate in the second processing tank. By carrying out the pad oxide-etching step and the silicon nitride-stripping step in separate processing tanks, accumulation of silicon oxide precipitates in the second processing tank is avoided.Type: GrantFiled: November 5, 2004Date of Patent: July 29, 2008Assignee: Taiwan Semiconductor Manufacturing Co, LtdInventors: Yang Kai Fan, Yong Rong Chang, Yi Song Chiu, Ping Yin Shin
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Patent number: 7390755Abstract: The current invention provides methods for performing a cleaning process that provides greater cleaning efficiency with less damage to device structures. After etching and photoresist stripping, a first plasma clean is performed. The first plasma clean may comprise one or more steps. Following the first plasma clean, a first HO based clean is performed. The first HO based clean may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. Following the first HO based clean, a second plasma clean is performed, which may comprise one or more steps. A second HO based clean follows the second plasma clean, and may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. For plasma processes, an RF generated plasma, a microwave generated plasma, an inductively coupled plasma, or combination may be used.Type: GrantFiled: May 1, 2002Date of Patent: June 24, 2008Assignees: Novellus Systems, Inc., STMicroelectronics S.R.L.Inventors: David L. Chen, Yuh-Jia Su, Eddie Ka Ho Chiu, Maria Paola Pozzoli, Senzi Li, Giuseppe Colangelo, Simone Alba, Simona Petroni
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Patent number: 7354869Abstract: A method for a substrate processing apparatus having a substrate holding mechanism and a chemical solution dispensing/sucking mechanism including a chemical solution dispensing port for supplying a first chemical solution and a chemical solution suction port, includes placing the target substrate on the substrate holding mechanism, laying out an auxiliary plate at a periphery of the substrate such that the two main faces are substantially flush with each other, supplying a second chemical solution onto the main faces, dispensing the first solution from the dispensing port and sucking the first and second solutions through the suction port, with the dispensing and suction ports brought into contact with the second solution, and while dispensing the first solution from the dispensing port and sucking the first solution through the suction port, scanning the dispensing/sucking mechanism such that the dispensing and suction ports are opposed to the main face of the substrate.Type: GrantFiled: April 12, 2005Date of Patent: April 8, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Hideaki Sakurai, Masamitsu Itoh
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Patent number: 7344999Abstract: A method for cleaning a substrate on which a silicon layer and a silicon germanium layer are formed and exposed, and method for fabricating a semiconductor device using the cleaning method are disclosed. The cleaning method comprises preparing a semiconductor substrate on which a silicon layer and a silicon germanium layer are formed and exposed; and performing a first cleaning sub-process that uses a first cleaning solution to remove a native oxide layer from the semiconductor substrate. The cleaning method further comprises performing a second cleaning sub-process on the semiconductor substrate after performing the first cleaning sub-process, wherein the second cleaning sub-process comprises using a second cleaning solution. In addition, the second cleaning solution comprises ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and deionized water (H2O), and the second cleaning solution comprises at least 200 times more deionized water (H2O) than ammonium hydroxide (NH4OH) by volume.Type: GrantFiled: September 27, 2006Date of Patent: March 18, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Sup Mun, Woo-Gwan Shim, Han-Ku Cho, Chang-Ki Hong, Doo-Won Kwon
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Patent number: 7323421Abstract: A process for etching silicon wafers using a caustic etchant in the form of an aqueous solution comprising water, a hydroxide ion source, and a chelating agent. The process produces silicon wafers substantially free from diffused metal ions.Type: GrantFiled: June 14, 2005Date of Patent: January 29, 2008Assignee: MEMC Electronic Materials, Inc.Inventors: Mark G. Stinson, Henry F. Erk, Guoqiang (David) Zhang, Mick Bjelopavlic, Alexis Grabbe, Jozef G. Vermeire, Judith A. Schmidt, Thomas E. Doane, James R. Capstick
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Patent number: 7319076Abstract: A method and apparatus to provide a low resistance interconnect. A void is defined in the sacrificial layer that is proximate to an active layer. An overgrowth layer is formed in the void and over portions of the sacrificial layer adjacent to the void. A ridge section is defined in the overgrowth layer and portions of the sacrificial layer are removed to define a shank section in the overgrowth layer under the ridge section. The ridge section having a greater lateral dimension than the shank section to reduce electrical resistance between the active layer and electrical interconnects to be electrically coupled to the ridge section.Type: GrantFiled: September 26, 2003Date of Patent: January 15, 2008Assignee: Intel CorporationInventor: Peter J. Hanberg
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Patent number: 7303933Abstract: A process of manufacturing a semiconductor device includes the steps of forming a stacked structure of a first III-V compound semiconductor layer containing In and having a composition different from InP and a second III-V compound semiconductor layer containing In. The second III-V compound semiconductor layer is formed over the first III-V compound semiconductor layer and growing an InP layer at regions adjacent the stacked structure to form a stepped structure of InP. The process further includes the step of wet-etching the stepped structure and the second III-V compound semiconductor layer using an etchant containing hydrochloric acid and acetic acid to remove at least the second III-V compound semiconductor layer.Type: GrantFiled: June 20, 2005Date of Patent: December 4, 2007Assignee: Fujitsu Quantum Devices LimitedInventors: Takayuki Watanabe, Tsutomu Michitsuta, Taro Hasegawa, Takuya Fujii
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Patent number: 7291283Abstract: A combined wet etching method for stacked films which is capable of performing etching processes in a collective manner while controlling an amount of side-etching on each of stacked films and of making uniform side edges. In the wet etching method, two or more types of etching methods are performed in combination, on stacked films containing first and second films being deposited sequentially on a substrate and each having a different film property. The two or more types of wet etching methods include, at least, a first wet etching method in which side-etching on the first film is facilitated more than side-etching on the second film and a second wet etching method in which side-etching on the second film is facilitated more than side-etching on the first film.Type: GrantFiled: November 12, 2003Date of Patent: November 6, 2007Assignee: NEC LCD Technologies, Ltd.Inventors: Tadanori Uesugi, Shigeru Kimura
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Patent number: 7288206Abstract: A high-purity alkali etching solution for silicon wafers results in silicon wafers with extremely low metal impurity contamination, and excellent surface flatness. The alkali etching solution contains sodium hydroxide containing 1 ppb or less of the elements Cu, Ni, Mg, and Cr, 5 ppb or less of the elements Pb and Fe, 10 ppb or less of the elements Al, Ca, and Zn, and 1 ppm or less of chloride, sulfate, phosphate, and nitrogen compounds other than nitrate and nitrite, and containing 0.01 to 10 wt % of nitrate and/or nitrite.Type: GrantFiled: December 22, 2004Date of Patent: October 30, 2007Assignee: Siltronic AGInventor: Shigeki Nishimura
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Publication number: 20070249178Abstract: A manufacturing method of a semiconductor device is provided to manufacture an increased number of semiconductor devices per single substrate such as, e.g., a wafer while obviating damages like those caused by conventional dicing method. The manufacturing method comprises steps of performing a first etching process to etch a separation area on a front surface of a substrate, arranging a supporter on a back surface of the first substrate to prevent semiconductor devices from coming apart, coating with a thin film a non-etching area including a sidewall of the etched separation area and excluding a bottom of the etched separation area on the front surface of the first substrate, and performing a second etching process to etch the first substrate from the front surface through an area not coated by the thin film to divide the substrate into multiple semiconductor devices.Type: ApplicationFiled: April 19, 2007Publication date: October 25, 2007Applicant: OKI DATA CORPORATIONInventor: Mitsuhiko OGIHARA
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Publication number: 20070218695Abstract: A method of forming a metal pattern comprising forming a metal film having a lower layer made of a metal and an upper layer made of a metal different from the metal of the lower layer, forming a resist film having a predetermined pattern on the upper layer, and patterning the metal film by etching the metal film using the resist film as a mask. Here, patterning the metal film comprises etching the upper layer, immersing the resist film and the upper layer in a pretreatment liquid containing a nonionic surfactant after the first etching process, and etching the lower layer after the immersing process.Type: ApplicationFiled: March 15, 2007Publication date: September 20, 2007Applicant: SEIKO EPSON CORPORATIONInventors: Shinya Momose, Kazushige Hakeda
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Patent number: 7267127Abstract: A method for manufacturing an electronic device comprising the steps of: dry-etching a Ti-containing metal film formed on a substrate with a gas containing fluorine; and treating the substrate with a chemical solution containing fluorine ions after the dry etching step.Type: GrantFiled: September 12, 2005Date of Patent: September 11, 2007Assignee: Matsushita Electric Inductrial Co., Ltd.Inventors: Masayuki Watanabe, Yukihisa Wada
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Publication number: 20070207623Abstract: A method for flattening a glass substrate includes the steps of preparing plural kinds of etching liquids different from one another in an etching rate, preparing the glass substrate, and etching the glass substrate at least one time with each of the etching liquids and executing the etching a plurality of times in total. When the etchings are executed the plurality of times, an etching rate of the glass substrate with one etching liquid used for one etching of plural etchings is slower than that of the glass substrate with the another etching liquid used for another etching executed after the one etching process of the plural etching processes.Type: ApplicationFiled: September 26, 2006Publication date: September 6, 2007Applicants: CASIO COMPUTER CO., LTD., SANWA FROST INDUSTRY CO., LTD., NAGASE & CO., LTD.Inventor: Kazuyuki Hiroki
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Patent number: 7256138Abstract: An etching method for use in integrated circuit fabrication includes providing a metal nitride layer on a substrate assembly, providing regions of cobalt silicide on first portions of the metal nitride layer, and providing regions of cobalt on second portions of the metal nitride layer. The regions of cobalt and the second portions of the metal nitride layer are removed with at least one solution including a mineral acid and a peroxide. The mineral acid may be selected from the group including HCl, H2SO4, H3PO4, HNO3, and dilute HF (preferably the mineral acid is HCl) and the peroxide may be hydrogen peroxide. Further, the removal of the regions of cobalt and the second portions of the metal nitride layer may include a one step process or a two step process. In the one step process, the regions of cobalt and the second portions of the metal nitride layer are removed with a single solution including the mineral acid and the peroxide.Type: GrantFiled: June 29, 2004Date of Patent: August 14, 2007Assignee: Micron Technology, Inc.Inventors: Whonchee Lee, Yongjun Jeff Hu
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Cleaning solution for silicon surface and methods of fabricating semiconductor device using the same
Publication number: 20070178706Abstract: A cleaning solution and methods of fabricating semiconductor devices using the same are provided. A cleaning solution used for cleaning a silicon surface and methods of fabricating a semiconductor device using the same are also provided. The cleaning solution may include 0.01 to 1 wt % of fluoric acid, 20 to 50 wt % of oxidizer and 50 to 80 wt % of water. The cleaning solution may further include 1 to 20 wt % of acetic acid. The cleaning solution may be used Lo clean a silicon surface exposed during fabrication processes of a semiconductor device. The cleaning solution may reduce damage of other material layers (e.g., a tungsten layer or a silicon oxide layer) and enable the silicon surface to be selectively etched.Type: ApplicationFiled: January 23, 2007Publication date: August 2, 2007Inventors: Sang-Yong Kim, Chang-Ki Hong, Woo-Gwan Shim -
Patent number: 7205184Abstract: A method of crystallizing a silicon film by which it is possible to obtain a polycrystalline silicon thin film having a uniform crystal structure and a good quality, and a method of manufacturing a thin film transistor-liquid crystal display (TFT-LCD) using the same. In the method of crystallizing the silicon film, an amorphous silicon film is formed on a substrate and a reflective film pattern is formed on the amorphous silicon film. The silicon film is crystallized by irradiating a laser onto the amorphous silicon film. The reflective film pattern is formed to expose the channel of the thin film transistor in the amorphous silicon film.Type: GrantFiled: October 14, 1998Date of Patent: April 17, 2007Assignee: Samsung Electronics Co., Ltd.Inventor: Heon-je Kim