Abstract: A method of forming contact holes. A dielectric liner is comformally formed on a substrate, parts of the dielectric liner between the second and the third conducting structure are removed, a conductive liner is conformally formed on the substrate, and parts of the metal layer are removed to leave parts thereof between the second and the third conducting structure. An ILD layer is then formed on the entire surface of the substrate, and a patterned photoresist layer is formed on the ILD layer. Finally, the ILD layer is etched using the patterned photoresist layer as a mask to form a first contact hole, a second contact hole, and a third contact hole in the ILD layer at the same time.

Abstract: A method for forming salicides with lower sheet resistance and increased sheet resistance uniformity over a semiconductor process wafer including providing a semiconductor process wafer having exposed silicon containing areas at a process surface; depositing a metal layer including at least one of cobalt and titanium over the process surface; carrying out at least one thermal annealing process to react the metal layer and silicon to form a metal silicide over the silicon containing areas; and, wet etching unsilicided areas of the metal layer with a wet etching solution including phosphoric acid (H3PO4), nitric acid (HNO3), and a carboxylic acid to leave salicides covering silicon containing areas at the process surface.

Abstract: Organic acid components are used to increase the solubility of ozone in aqueous solutions for use in removing organic materials, such as polymeric resist and/or post-etch residues, from the surface of an integrated circuit device during fabrication. Each organic acid component is preferably chosen for its metal-passivating effect. Such solutions can have significantly lower corrosion rates when compared to ozonated aqueous solutions using common inorganic acids for ozone solubility enhancement due to the passivating effect of the organic acid component.

Abstract: A method for manufacturing of a metal line contact plug of a semiconductor device by performing a two step CMP process using (1) a first slurry solution having high etching selectivity of metal/insulating film and (2) a second slurry solution having small etching selectivity of metal/insulating film, thereby minimizing dependency on CMP devices and separating easily a metal line contact plug.

Abstract: Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow trenches at additional locations. Etching of the shallow and deep trenches then proceeds simultaneously.

Abstract: Disclosed is a method of manufacturing a semiconductor device. First, a silicidation blocking layer is formed on a semiconductor substrate by a plasma enhanced chemical vapor deposition process. Next, the silicidation blocking layer in a region in which a metal silicide contact is to be formed is removed by a wet etching process. Next, after a metal layer is formed on the resultant, the silicon in the region and the metal of the metal layer are reacted to form the metal silicide. Since the silicidation blocking layer consisting of PE-SiON is formed at a low temperature of less than 400 Celsius Degrees, it is possible to prevent diffusion and redistribution of impurities in gate and source/drain regions of a transistor during the deposition of the silicidation blocking layer.

Abstract: A method for using ammonium fluoride solution in a photoelectrochemical etching process of a silicon wafer, comprising steps of: placing a wafer after the pre-etching process into an alcohol solution for activating the surface of wafer and into an ammonium fluoride solution as an etching solution; and illuminating the back of wafer with a halogen light and performing a photoelectrochemical etching process in a potentiostatic.

Abstract: The invention relates to a ball-limiting metallurgy stack for an electrical device that contains at least one copper layer disposed upon a Ti adhesion metal layer. The ball-limiting metallurgy stack resists Sn migration toward the upper metallization of the device.

Abstract: A method of spiking a mixed acid liquid in a reactor is performed under three modes of control, a based-on-charge mode control, a based-on-time mode control, and a based-on-time-and-charge mode control. In the based-on-charge mode control, spike timing and spiking amount of an acid liquid are set for each lot of product. In the based-on-time mode control, the spike timing and the spiking amount of the acid liquid are set for each timing point. In the based-on-time-and-charge mode control, the spike timing and the spiking amount of an acid liquid are set for each lot of product and each timing point. Thereby, a concentration of the mixed acid liquid is controlled at a targetlevel.

Abstract: A multilayer switching assembly for switching high frequency signals has MEMS structures on a ceramic substrate having a top surface, a bottom surface and a plurality of insulating layers. The insulating layers are separated by a first conductor and a second conductor. The first conductor is connected to a ground potential. The second conductor is separated from the first conductor by one of the insulating layers. The second conductor presents a specific impedance (50 ohms) with respect to the first conductor to high frequency signals traveling on the second conductor. 64 MEMS structures are mounted on the top surface. Each MEMS has an input, an output, and a control. The input connected to the second conductor. The output is connected to a coplanar waveguide placed on the top surface. The control is connected to the bottom surface. The input to each MEMS is electrically shielded from the output and from the control by a third conductor connected to the first (grounded) conductor.

Abstract: A silicon oxide film having a ununiform thickness is deposited inside each of trenches defined in a silicon substrate by etching within a device isolation region, in such a manner that only corner portions of trench bottoms are exposed. The silicon substrate is selectively etched from the exposed trench corner portions of the silicon substrate lying inside the trenches to thereby increase the volume of each trench.

Abstract: A two-step via cleaning process that removes metal polymer and oxide polymer residues from a via with substantially no damage to the via or underlying structures on a semiconductor substrate. The two-step cleaning process comprises first subjecting the residue layer to a nitric acid dip that removes the metal polymer component to expose the oxide polymer component. The oxide polymer component is then subjected to a phosphoric acid dip that removes the oxide polymer component. The oxide polymer and metal polymer residues may also be removed during the fabrication of the via by removing them directly after their respective formations.

Abstract: A provided method for manufacturing the semiconductor device includes the steps of: forming a trench in a silicon substrate on which a silicon oxide film and a silicon nitride film are sequentially stacked; oxidizing the silicon substrate by an oxidation method of not forming nearly at all a silicon oxide film on a surface of the silicon nitride film, to form a silicon oxide film on the surface of the trench and perform pullback etching on the silicon nitride film; and performing rounding oxidation by using radical oxidation to round an edge of the surface of the trench. Therefore, it is possible to perform pullback etching on the nitride film, even in case of performing rounding oxidation by using radical oxidation.

Abstract: In a method of fabricating a microstructure for micro-fluidics applications, a mechanically stable support layer is formed over a layer of etchable material. An anisotropic etch is preformed through a mask to form a pattern of holes extending through the support layer into said etchable material. An isotropic etch is performed through each said hole to form a corresponding cavity in the etchable material under each hole and extending under the support layer. A further layer of depositable material is formed over the support layer until portions of the depositable layer overhanging each said hole meet and thereby close the cavity formed under each hole. The invention permits the formation of micro-channels and filters of varying configuration.

Abstract: A method is disclosed for accurately predicting the wet etch end points as a function of the temperature and concentration of the etching solution, as well as of the thickness of the film to be etched. This is accomplished by fitting an etch rate equation to the process of etching a film in terms of two constant parameters that are determined by one set of experiments performed on a given wet etch bench. Thereafter, the constants are used with the rate equation to calculate precisely the etch rate of a film, and then the etch rate is divided into a target film loss or a target film thickness to obtain etching time, or time to etch, which takes into account the variations in temperature and concentration, for example, of the acid in the solution. The resulting film either looses the specified amount of material, or acquires the specified thickness without incurring any damage, which is especially suited for sub-micron semiconductor technology where precise etching is required.

Abstract: A method of reducing particulate contamination in a deposition process including providing a semiconductor wafer having a process surface for depositing a deposition layer thereover according to one of a physical vapor deposition (PVD) and a chemical vapor deposition (CVD) process; depositing at least a portion of the deposition layer over the process surface; cleaning the semiconductor wafer including the process surface according to an ex-situ cleaning process to remove particulate contamination including at least one of spraying and scrubbing; and, repeating the steps of depositing and cleaning at least once to include reducing a level of occluded particulates.

Abstract: A method for forming a metal silicide layer in a self-aligned manner on a source region and a drain region and a gate electrode of a semiconductor device formed on a semiconductor substrate, the method comprising the steps of: depositing a cobalt film over an entire surface of the semiconductor device formed on the semiconductor substrate, forming the metal silicide layer on the source region and drain region and the gate electrode by performing a heat treating thereof, and etching away an unreacted cobalt remaining on the semiconductor substrate using an admixture solution made of hydrochloric acid, hydrogen peroxide, and water, having relative concentration ratio ranging from 1:1:5 to 3:1:5, at a solution temperature of 25 to 45° C., with an etching time of 1 to 20 minutes.

Abstract: A passive integrated component (10) is formed overlying a semiconductor substrate by etching a composite conductive layer using a solution of sodium persulfate or ceric ammonium nitrate to remove a lower portion of the composite copper layer (64) exposed by an upper portion of the composite copper layer (74, 76, 78) to expose an underlying surface (62).

Abstract: A stringer block is formed on the interface between a HDP silicon oxide layer and a silicon substrate. During an etching process for defining the profile of a floating gate, the stringer block functions to expose a bottom corner stringer. Following that, a polysilicon etching process effectively removes the bottom corner stringer. As a result, a stringerless flash memory cell is formed to prevent leakage currents, resulting from the bottom corner stringer, and improve both the reliability and data retention ability of the device.

Abstract: In a method for producing a bonding wafer by the hydrogen ion delamination method comprising at least a step of bonding a base wafer and a bond wafer having a micro bubble layer formed by gas ion implantation and a step of delaminating them at the micro bubble layer as a border, a peripheral portion of a thin film formed on the base wafer is removed after the delamination step. Preferably, a region of 1-5 mm from the peripheral end of the base wafer is removed. In the production of a bonding wafer by the hydrogen ion delamination method, there can be provided a bonding wafer free from problems such as generation of particles from peripheral portion of the wafer and generation of cracks in the SOI layer.

Abstract: A thin discontinuous layer of metal such as Au, Pt, or Au/Pd is deposited on a silicon surface. The surface is then etched in a solution including HF and an oxidant for a brief period, as little as a couple seconds to one hour. A preferred oxidant is H2O2. Morphology and light emitting properties of porous silicon can be selectively controlled as a function of the type of metal deposited, Si doping type, silicon doping level, and/or etch time. Electrical assistance is unnecessary during the chemical etching of the invention, which may be conducted in the presence or absence of illumination.

Abstract: An etching method for use in integrated circuit fabrication includes providing a metal nitride layer on a substrate assembly, providing regions of cobalt silicide on first portions of the metal nitride layer, and providing regions of cobalt on second portions of the metal nitride layer. The regions of cobalt and the second portions of the metal nitride layer are removed with at least one solution including a mineral acid and a peroxide. The mineral acid may be selected from the group including HCl, H2SO4, H3PO4, HNO3, and dilute HF (preferably the mineral acid is HCl) and the peroxide may be hydrogen peroxide. Further, the removal of the regions of cobalt and the second portions of the metal nitride layer may include a one step process or a two step process. In the one step process, the regions of cobalt and the second portions of the metal nitride layer are removed with a single solution including the mineral acid and the peroxide.

Abstract: A method for removing organometallic and organosilicate residues remaining after a dry etch process from semiconductor substrates. The substrate is exposed to a conditioning solution of a fluorine source, a non-aqueous solvent, a complementary acid, and a surface passivation agent. The fluorine source is typically hydrofluoric acid. The non-aqueous solvent is typically a polyhydric alcohol such as propylene glycol. The complementary acid is typically either phosphoric acid or hydrochloric acid. The surface passivation agent is typically a carboxylic acid such as citric acid. Exposing the substrate to the conditioning solution removes the remaining dry etch residues while minimizing removal of material from desired substrate features.

Abstract: A thin discontinuous layer of metal such as Au, Pt, or Au/Pd is deposited on a Group III-V material surface. The surface is then etched in a solution including HF and an oxidant for a preferably brief period, as little as a couple seconds to one hour. A preferred oxidant is H2O2. Morphology and light emitting properties of porous Group III-V material can be selectively controlled as a function of the type of metal deposited, doping type, doping level, metal thickness, whether emission is collected on or off the metal coated areas and/or etch time. Electrical assistance is unnecessary during the chemical etching of the invention, which may be conducted in the presence or absence of illumination.

Abstract: Various methods for forming surface micromachined microstructures are disclosed. One aspect relates to executing surface micromachining operation to structurally reinforce at least one structural layer in a microstructure. Another aspect relates to executing the surface micromachining operation to form a plurality of at least generally laterally extending etch release channels within a sacrificial material to facilitate the release of the corresponding microstructure.

Abstract: A silicon element having macrocavities beneath its exterior surface is fabricated by electrochemical etching of a p-type silicon wafer. Etching at a high current density results in the formation of deep macrocavities overhung by a layer of crystalline silicon. The process works with both aqueous and non-aqueous electrolytes.

Abstract: A method and apparatus for etching a semiconductor die are disclosed whereby flowing an etchant material across an inactive thereof thins the semiconductor die. In one embodiment, the etchant includes a mixture of nitric acid, hydrofluoric acid, and acetic acid and turbulently flows from one edge of the semiconductor die, across the inactive surface of the semiconductor die, to an opposing edge of the semiconductor die.

Abstract: The present invention relates to a method for fabricating semiconductor capacitors, which enables the capacitance of the capacitors to be increased.

Abstract: A method for removing a polysilicon layer from a non-silicon layer comprising the following steps. A structure having a non-silicon layer formed thereover is provided. A first polysilicon layer is formed upon the non-silicon layer. The first polysilicon layer is removed from over the non-silicon layer to expose the non-silicon layer using a NH4OH:DIW dip solution process having a NH4OH:DIW ratio of from about 1:2 to 1:8. Whereby the non-silicon layer is substantially unaffected by the NH4OH:DIW dip solution process.

Abstract: Provided is a method for forming a self aligned contact (SAC) of a semiconductor device that can minimize the loss of gate electrodes and hard mask. The method includes the steps of: providing a semiconductor substrate on which a plurality of conductive patterns are formed; forming a first insulation layer along the profile of the conductive patterns on the substrate; forming a second insulation layer on the substrate and simultaneously forming voids between the conductive patterns; forming a third insulation layer on the first insulation layer; and forming contact holes that expose the surface of the substrate between the conductive patterns by etching the third insulation layer and the second insulation layer covering the voids.

Abstract: A semiconductor device, which uses a crystalline silicon film having high crystallinity and a flat surface with few ridges and has high characteristics, and a method of manufacturing the semiconductor device are provided. According to the manufacturing method, a first amorphous silicon film is crystallized by using a heat treatment. A second amorphous silicon film is formed on a first crystalline silicon film thus obtained as an under film, and the second amorphous silicon film is crystallized by irradiation of laser light, so that a silicon film having excellent crystallinity and a surface with few ridges is obtained. The first crystalline silicon film and the second crystalline silicon film having different crystal structures are used as an active layer of a thin film transistor.

Abstract: The present disclosure relates to a post-etch cleaning treatment for a semiconductor device such as a FeRAM. The treatment comprises providing an etchant comprising both a fluorine compound and a chlorine compound, and applying the etchant to the semiconductor device in a wet cleaning process.

Abstract: A method for removing layers or layer systems from a substrate and subsequent application onto an alternative substrate. A porous breakaway layer is formed by anodization in hydrofluoric acid. Optionally, a stabilizing layer with lower porosity is previously produced on top of the breakaway layer. The oxide of the porous breakaway layer or the stabilizing layer is removed by brief contact with HF, and an epitaxial layer is applied on the porous breakaway layer or the stabilizing layer. The epitaxial layer or the layer system is then removed from the substrate, and the epitaxial layer or the layer system is applied onto an alternative substrate. Optionally, the stabilizing layer and/or residues of the breakaway layer are removed from the epitaxial layer.

Abstract: A method 10 for making a multi-layer circuit board 70 having at least one electrically conductive interconnection portion or “via” 72 which extends within the board 70 and at least one air-bridge 74. The method 10 includes the steps of forming protuberances 13 upon a core member 12, attaching pre-circuit assemblies 32, 34 to the core member 12, thereby forming the circuit board 70 while concomitantly and selectively extending at least one of the protuberances 13 within the formed circuit board 70.

Abstract: A semiconductor device manufacturing method for manufacturing a semiconductor device of constant finished dimensions as designed even when a material which is difficult to increase etch selectivity to a silicon film in a gate electrode or wiring structure is used for an anti-reflection coating, and which is also capable of achieving finer patterning through the use of a silicon oxide film or the like as a hard mask. For example, a silicon oxy-nitride film and a silicon oxide film are used for an anti-reflection coating and a hard mask, respectively, to provide etch selectivity therebetween. In etching of the anti-reflection coating and the hard mask, the hard mask such as a silicon oxide film is not completely etched in order to leave a non-single crystalline silicon film covered, under which condition the anti-reflection coating is removed.

Abstract: The present invention relates to a method of forming a damascene gate electrode of highly integrated MOS transistor capable of easily removing a dummy polysilicon layer. The disclosed comprises the steps of forming a dummy gate insulating layer and a polysilicon layer for a dummy gate on a wafer; forming an interlayer insulating layer on the wafer; polishing the interlayer insulating layer to expose a top surface of the dummy polysilicon layer; and wet etching the exposed dummy polysilicon layer using a spin etching process.

Abstract: The present invention discloses a method for fabricating a semiconductor device. In a process for forming metal interconnection contact holes on both a gate electrode including an Si-rich SiON film as a mask insulating film in a peripheral circuit region and on a semiconductor substrate, the metal interconnection contact hole is formed according to a three-step etching process using a photoresist film pattern exposing the intended locations of a metal interconnection contacts as an etching mask. Accordingly, contact properties are improved by preventing damage to the semiconductor substrate, thereby reducing leakage current and improving yield.

Abstract: The method for forming an isolation film in a semiconductor device includes the steps of providing a semiconductor substrate having at least a first insulation film formed thereon, and forming a trench in the first insulation film and the semiconductor substrate. Next, an insulation film pattern is formed. The insulation film pattern fills the trench and extends from the trench over a portion of the first insulation film. Afterwards, the first insulation film is etched. The etching of the first insulation film also results in etching of the insulation film pattern, but the insulation film pattern at the upper side wall edges of the trench is not etched.

Abstract: An etchant for etching at least one of a titanium material and silicon oxide includes a mixed liquid of HCl, NH4F and H2O. When the etchant has a NH4F/HCl molar ratio of less than one, only the titanium material is etched. When the etchant has a NH4F/HCl molar ratio of more than one, only silicon oxide is etched. When the etchant has a NH4F/HCl molar ratio of one, the titanium material and silicon oxide are etched at the same rate.

Abstract: A method of forming sublithography gate lengths involves the steps of patterning the layer of resist above the gate stack (including a gate layer, hardmask layer and etch-control layer) to a desired gate length and etching the etch-control layer and the hardmask layer; the portion of the circuit that has the correct gate length is covered with a blocking mask and the hardmask in the remainder is wet-etched to reduce its dimension, after which the gate stack is etched using both gate lengths of hardmask to produce different gate lengths in different areas.

Abstract: A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an alignment mark area of a silicon wafer in process during the formation of integrated circuits thereon.

Abstract: A method and apparatus for analyzing a semiconductor surface obtains a sample from a localized section of a wafer. The sample is obtained by isolating a section of a wafer with a sampling apparatus, dispensing liquid onto the isolated section of the wafer, dissolving compounds of interest in the liquid, removing a portion of the liquid, and analyzing the liquid and dissolved compounds of interest. The liquid can be an etching solution, an organic solvent, or other suitable solvent. Samples and analyses can, thus, be obtained as a function of position on the wafer. Analyses as a function of depth can also be determined by sampling and analyzing an isolated portion of the wafer as a function of time.

Abstract: The present invention includes a method of providing a first substrate; forming an insulator over the first substrate; forming an opening in the insulator; forming a conductor over the insulator and in the opening; removing the conductor over the insulator with a first chemical-mechanical polish process to leave the conductor in the opening; and reducing thickness of the insulator with a second chemical-mechanical process to permit the conductor in the opening to protrude. The present invention further includes a structure having such a conductor that protrudes.

Abstract: The invention includes a method of cleaning a surface of a copper-containing material by exposing the surface to an acidic mixture comprising NO3−, F− and one or more organic acid anions having carboxylate groups. The invention also includes a semiconductor processing method of forming an opening to a copper-containing material. A mass is formed over a copper-containing material within an opening in a substrate. The mass contains at least one of an oxide barrier material and a dielectric material. A second opening is etched through the mass into the copper-containing material to form a base surface of the copper-containing material that is at least partially covered by particles comprising at least one of a copper oxide, a silicon oxide or a copper fluoride. The base surface is cleaned with a solution comprising nitric acid, hydrofluoric acid and one or more organic acids to remove at least some of the particles.

Abstract: A method of fabricating a semiconductor device causing no pattern shifting of a peripheral oxide film etc. in removal of both of an antireflection film and a mask pattern and having a fine structure not implementable solely by photolithography and the semiconductor device are obtained. The method of fabricating a semiconductor device comprises steps of forming a base film of either a silicon film or a silicon compound film on a semiconductor substrate, forming a hard film of either a metal film or a metal compound film on the base film, forming a resist pattern on the hard film, dryly etching the hard film through the resist pattern serving as a mask for forming a hard pattern, dryly etching the base film through the hard pattern serving as a mask and removing the hard pattern by wet etching with a chemical solution not etching at least the base film.

Abstract: A method of removing a photoresist layer on a semiconductor wafer starts with placing the semiconductor wafer into a dry strip chamber. A dry stripping process is performed to remove the photoresist layer on the semiconductor wafer. The semiconductor wafer is then placed on a rotator of a wet clean chamber and horizontally rotated. A first cleaning process is performed to remove polymers and organic components on a surface of the semiconductor wafer. Then a second cleaning process is performed as well to remove polymers and particles on the surface of the semiconductor wafer. By performing a third cleaning process, a first cleaning solution employed in the first cleaning process and a second cleaning solution employed in the second cleaning process are removed from the surface of the semiconductor wafer. Finally, the semiconductor wafer is spun dry at the end of the method.

Abstract: One aspect of the invention relates to a method of etching a high-k dielectric. The method involves removing an exposed portion of a high-k dielectric layer from a substrate by wet etching with a solution comprising water, a strong acid, an oxidizing agent, and a fluorine compound. The etching solution provides selectivity towards the high-k film against insulating materials and polysilicon and is therefore useful in manufacturing FETs.

Abstract: A two-step via cleaning process which removes metal polymer and oxide polymer residues from a via with substantially no damage to the via or underlying structures on a semiconductor substrate. The via is formed through a dielectric layer and a barrier layer which are disposed over a metal-containing trace, pad, or other such circuitry, wherein the metal-containing trace, pad, or other circuitry is disposed on a semiconductor substrate. When such a via is formed, the sidewalls of the via are coated with a residue layer. The residue layer generally has a distinct oxide polymer component and a distinct metal polymer component. The two-step cleaning process comprises first subjecting the residue layer to a nitric acid dip which removes the metal polymer component to expose the oxide polymer component. The oxide polymer component is then subjected to a phosphoric acid dip which removes the oxide polymer component.

Abstract: An inter-level metallization structure and the method of forming it, preferably based on copper dual damascene in which the lower-metal level is formed with a exposed metallization and an adjacent, embedded stop layer, both the metallization and embedded stop layer have exposed surfaces approximately level with each other with a lower dielectric layer. The upper-metal level includes a second stop layer deposited over the embedded stop layer and the first metallization and a second dielectric layer. An inter-level via is etched through the second dielectric layer and through the second stop layer and metal is filled into the via to contact the metallization. If the inter-level via is offset over the edge of the metallization, the metal in the via contacts the embedded stop layer and not the first dielectric layer, whereby the embedded stop layer acts as a copper diffusion barrier.

Abstract: A method of creating an undercut sidewall profile within an opening formed in a positive resist layer disposed upon a transparent substrate includes the step of forming a positive resist layer on the upper surface of the substrate, and optically patterning the resist layer by selectively directing light at the resist layer from above the upper surface of the substrate. The lower surface of the substrate is flooded with light to partially expose the lowermost region of the resist layer, and the exposed resist is dissolved to form patterned openings therein. The resulting sidewalls of the patterned resist openings have an enlarged width adjacent the upper surface of the substrate. The sidewalls of the resist layer are then flooded with light from above the substrate, the upper region of the resist layer is cured by an electron beam, and the resist layer is developed a second time to dissolve exposed portions of the resist sidewalls, thereby forming an undercut resist sidewall profile.