Abstract: A solar cell and a method of texturing a solar cell are disclosed. The method includes coating an ink containing metal particles on a surface of a substrate, drying the ink to attach the metal particles to the surface of the substrate, and differentially etching the surface of the substrate using the metal particles as a catalyst to form an uneven portion.

Abstract: An object of an embodiment of the disclosed invention is to provide a method suitable for reprocessing a semiconductor substrate which is reused to manufacture an SOI substrate.

Abstract: A process of manufacturing a semiconductor device includes the steps of forming a stacked structure of a first III-V compound semiconductor layer containing In and having a composition different from InP and a second III-V compound semiconductor layer containing In. The second III-V compound semiconductor layer is formed over the first III-V compound semiconductor layer and growing an InP layer at regions adjacent the stacked structure to form a stepped structure of InP. The process further includes the step of wet-etching the stepped structure and the second III-V compound semiconductor layer using an etchant containing hydrochloric acid and acetic acid to remove at least the second III-V compound semiconductor layer.

Abstract: A method for manufacturing surgical blades from either a crystalline or poly-crystalline material, preferably in the form of a wafer, is disclosed. The method includes preparing the crystalline or poly-crystalline wafers by mounting them and machining trenches into the wafers. The methods for machining the trenches, which form the bevel blade surfaces, include a diamond blade saw, laser system, ultrasonic machine, and a hot forge press. The wafers are then placed in an etchant solution which isotropically etches the wafers in a uniform manner, such that layers of crystalline or poly-crystalline material are removed uniformly, producing single or double bevel blades. Nearly any angle can be machined into the wafer which remains after etching. The resulting radii of the blade edges is 5-500 nm, which is the same caliber as a diamond edged blade, but manufactured at a fraction of the cost.

Abstract: A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.

Abstract: An alkali etchant for controlling surface roughness of a semiconductor wafer, which is a sodium hydroxide solution or a potassium hydroxide solution having a weight concentration of 55 wt % to 70 wt %.

Abstract: Disclosed is a method of manufacturing a semiconductor device, which includes forming an insulating film above a semiconductor substrate having a recess and stopper film formed above the semiconductor substrate excluding the recess, thereby filling the recess with the insulating film, performing a first polishing by polishing the insulating film by means of a chemical mechanical polishing method using a first polishing liquid containing cerium oxide and first anionic surfactant, thereby obtaining a flattened surface, and performing a second polishing by polishing the flattened insulating film using a second polishing liquid containing cerium oxide and a second anionic surfactant having a smaller molecular weight than that of the first anionic surfactant under a polishing condition which differs from that of the first polishing, thereby exposing the stopper film.

Abstract: Disclosed is a method for manufacturing a semiconductor device comprising forming a hydrophobic interlayer insulating film having a relative dielectric constant of 3.5 or less above a semiconductor substrate, forming a recess in the interlayer insulating film, depositing a conductive material above the interlayer insulating film having the recess to form a conductive layer, selectively removing the conductive material deposited above the interlayer insulating film by polishing to expose a surface of the interlayer insulating film while leaving the conductive material in the recess, and subjecting the surface of the interlayer insulating film having the recess filled with the conductive material to pressure washing using a resin member and an alkaline washing liquid containing an inorganic alkali and exhibiting a pH of more than 9.

Abstract: The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes applying a first etching process to the substrate to remove a polysilicon layer and a metal gate layer on the substrate; applying a diluted hydrofluoric acid (HF) to the substrate to remove polymeric residue; thereafter applying to the substrate with a cleaning solution including hydrochloride (HCl), hydrogen peroxide (H2O2) and water (H2O); applying a wet etching process diluted hydrochloride (HCl) to the substrate to remove a capping layer; and applying to the substrate with a second etching process to remove a high k dielectric material layer.

Abstract: A method and system for fabricating nano-scale structures, such as channels (i.e., nano-channels) or vias (i.e., nano-vias). An open nano-structure, is formed in a substrate. Thereafter, a conformal material film may be deposited within and over the nano-structure using an optional first deposition process condition, and then the open nano-structure is closed off to form a closed nano-scale structure using a second deposition process condition, including one or more process steps.

Abstract: A manufacturing method of semiconductor device includes: forming a nitride film above a silicon substrate including a first region and a second region which respectively correspond to an outside of a memory cell region and the memory cell region; forming trenches reaching from the nitride film to the silicon substrate; retreating the nitride film such that widths of the trenches at the nitride film become wider; forming a buried oxide film to be buried in the trenches after the retreating; polishing the buried oxide film with the nitride film being used as a stopper; removing the nitride film after the polishing; implanting impurity after the removing; forming gate electrodes after the implanting; and implanting impurity after the forming the gate electrodes.

Abstract: A wet cleaning process is provided. The wet cleaning process includes at least one first rinse process and a second rinse step. The first rinse step includes rinsing a substrate using deionized water containing CO2, and then draining the water containing CO2 to expose the substrate in an atmosphere of CO2. The second rinse step includes rinsing the substrate using deionized water containing CO2.

Abstract: A cleaning sequence usable in semiconductor manufacturing efficiently cleans semiconductor substrates while preventing chemical oxide formation thereon. The sequence includes the sequence of: 1) treating with an HF solution; 2) treating with pure H2SO4; 3) treating with an H2O2 solution; 4) a DI water rinse; and 5) treatment with an HCl solution. The pure H2SO4 solution may include an H2SO4 concentration of about ninety-eight percent (98%) or greater. After the HCl solution treatment, the cleaned surface may be a silicon surface that is free of a chemical oxide having a thickness of 5 angstroms or greater. The invention finds particular advantage in semiconductor devices that utilize multiple gate oxide thicknesses.

Abstract: A TFT array substrate has a substrate with a pixel region and a switching region. A gate line has both a gate electrode that extends into the switching region and a gate pad is formed on the substrate. A gate pad electrode is formed on the gate pad. A data line includes both a source electrode that extends from the data line into the switching region and a data pad. A data pad electrode is formed on the data pad. A drain electrode that is spaced apart from the source electrode is over the gate electrode. A gate insulation layer covers the gate electrode and the substrate. Semiconductor layers, including a pure amorphous silicon layer and a doped amorphous silicon layer, and a protection layer extends over the source electrode, over the silicon layers, and over part of the drain electrode. A pixel electrode is formed on the pixel region. The pixel electrode contacts a side portion of the drain electrode. The TFT array substrate is fabricated using a back exposure.

Abstract: A two-step via cleaning process that removes metal polymer and oxide polymer residues from a via with substantially no damage to the via or underlying structures on a semiconductor substrate. The via is formed through a dielectric layer and a barrier layer that are disposed over a metal-containing trace disposed on a semiconductor substrate. Sidewalls of the via may be coated with a residue layer including a distinct oxide polymer component and a distinct metal polymer component. The two-step via cleaning process comprises subjecting the residue layer to a nitric acid dip that removes the metal polymer component to expose the oxide polymer component. The oxide polymer component is then subjected to a phosphoric acid dip that removes the oxide polymer component. The oxide polymer and metal polymer residues may also be removed during the fabrication of the via by removing them directly after their respective formations.

Abstract: Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C4F6 and C4F8. The recessed materials may be within isolation regions, and the recessing may be utilized to form trenches for receiving gatelines. Some embodiments include structures having an island of semiconductor material laterally surrounded by electrically insulative material. Two gatelines extend across the insulative material and across the island of semiconductor material. One of the gatelines is recessed deeper into the electrically insulative material than the other.

Abstract: Disclosed is a method for cleaning a multilayer substrate at least having a silicon single crystal wafer with a SiGe layer epitaxially grown on a surface of the silicon single crystal wafer, where the SiGe layer is an outermost surface of the SiGe layer and then cleaning the multilayer substrate with a first cleaning liquid capable of etching the protective film so that the protective film remains. The protective film prevents roughening of the surface of the SiGe layer while the cleaning is performed. The cleaning is performed. The cleaning is performed so that a thickness of the remaining protective film is from 1 nm to 100 nm.

Abstract: The inventive method for processing a silicon wafer is a method comprising step 11 in which a single crystal ingot is sliced into thin disc-like wafers; step 13 in which the surface of each wafer is lapped to be planar; step 14 in which the wafer is subjected to alkaline cleaning to be removed of contaminants resulting from preceding machining; and step 16 in which the wafer is alternately transferred between two groups of etching tanks one of which contain acidic etching solutions and the other alkaline etching solutions, wherein an additional step 12 is introduced between step 11 and step 13 in which a wafer is immersed in an acidic solution containing hydrofluoric acid (HF) and nitric acid (HNO3) at a volume ratio of ? to ½ (HF/HNO3) so that degraded superficial layers occurring on the front and rear surfaces of the wafer as a result of machining can be removed and the edge surface of the wafer can be beveled.

Abstract: A method and system for fabricating nano-scale structures, such as channels (i.e., nano-channels) or vias (i.e., nano-vias. An open nano-structure, is formed in a substrate. Thereafter, an optional conformal material film may be deposited within and over the nano-structure using a first deposition process condition, and then the open nano-structure is closed off to form a closed nano-structure using a second deposition process condition, including one or more process steps.

Abstract: Methods to etch a workpiece are described. In one embodiment, a workpiece is disposed within an etchant solution having a composition comprising a dilute acid and a non-ionic surfactant. An electric field is generated within the etchant solution to cause an anisotropic etch pattern to form on a surface of the workpiece.

Abstract: A method of manufacturing a micro-structure includes dry-etching a sacrificial layer provided to a silicon substrate to form structures the sacrificial layer reacting with etching gas to generate reaction products including H2O, wherein the dry-etching includes etching the sacrificial layer and removing H2O as one of the reaction products generated through the etching step of the sacrificial layer, wherein the etching and the removing of H2O are repetitively performed.

Abstract: Method of removing damaged silicon carbide crystalline structure from the surface of a silicon carbide component. The method comprises at least two liquid chemical treatment processes, where one treatment converts silicon carbide to silicon oxide, and another treatment removes silicon oxide. The liquid chemical treatments are typically carried out at a temperature below about 100° C. The time period required to carry out the method is generally less than about 100 hours.

Abstract: According to the present invention, a process for changing the form of a processed film is performed to planarize it before the processed film which is formed on a wafer is processed in a manufacturing process of a semiconductor device. As the process for changing the form of the processed film, there may be exemplified a single wafer type wet etching process. The compatibility of the processed film with processing means is taken into consideration and, for instance, the wet etching process is applied to the processed film so as to eliminate parts incompatible with the processing means, so that a distribution in-plane of the processed film is previously improved.

Abstract: A contact hole forming method and a method of manufacturing semiconductor device using the same may include forming a layer on a substrate; anisotropically etching the layer to form a dummy contact hole exposing the substrate; isotropically etching a sidewall of the dummy contact hole to form a contact hole by alternatively and repeatedly supplying an etching solution including a fluoride salt in a low-polarity organic solvent and deionized water to the dummy contact hole. The methods increase reliability of semiconductor memory devices.

Abstract: An apparatus for removing haze in a photo mask includes sealed chamber having a bake module disposed therein to support a photo mask, a reactant gas feed line to feed a reactant gas into the chamber, and a discharge device to discharge impurities in the chamber to the outside.

Abstract: A method of manufacturing gate oxide layers with different thicknesses is disclosed. The method includes that a substrate is provided first. The substrate has a high voltage device region and a low voltage device region. Then, a high voltage gate oxide layer is formed on the substrate. Afterwards, a first wet etching process is performed to remove a portion of the high voltage gate oxide layer in the low voltage device region. Then, a second wet etching process is performed to remove the remaining high voltage gate oxide layer in the low voltage device region. The etching rate of the second wet etching process is smaller than that of the first wet etching process. Next, a low voltage gate oxide layer is formed on the substrate in the low voltage device region.

Abstract: A two-step via cleaning process that removes metal polymer and oxide polymer residues from a via with substantially no damage to the via or underlying structures on a semiconductor substrate. The via is formed through a dielectric layer and a barrier layer that are disposed over a metal-containing trace disposed on a semiconductor substrate. The sidewalls of the via may be coated with a residue layer including a distinct oxide polymer component and a distinct metal polymer component. The two-step cleaning process comprises subjecting the residue layer to a nitric acid dip that removes the metal polymer component to expose the oxide polymer component. The oxide polymer component is then subjected to a phosphoric acid dip that removes the oxide polymer component. The oxide polymer and metal polymer residues may also be removed during the fabrication of the via by removing them directly after their respective formations.

Abstract: A method for manufacturing an optical device includes the steps of: forming a first multilayer film, including forming a first mirror above a substrate, forming an active layer above the first mirror, forming a second mirror above the active layer, forming a semiconductor layer on the second mirror, and forming a sacrificial layer on the semiconductor layer; conducting a first examination step of conducting a reflectance examination on the first multilayer film; forming a second multilayer film by removing the sacrificial layer from the first multilayer film; conducting a second examination step of conducting a reflection coefficient examination on the second multilayer film; and patterning the second multilayer film to form a surface-emitting laser section having the first mirror, the active layer and the second mirror, and a diode section having the semiconductor layer, wherein the sacrificial layer is formed to have an optical film thickness of an odd multiple of ?/4, where ? is a design wavelength of ligh

Abstract: A two-step via cleaning process that removes metal polymer and oxide polymer residues from a via with substantially no damage to the via or underlying structures on a semiconductor substrate. The via is formed through a dielectric layer and a barrier layer that are disposed over a metal-containing trace, pad, or other such circuitry, wherein the metal-containing trace, pad, or other circuitry is disposed on a semiconductor substrate. When such a via is formed, the sidewalls of the via are coated with a residue layer. The residue layer generally has a distinct oxide polymer component and a distinct metal polymer component. The two-step cleaning process comprises first subjecting the residue layer to a nitric acid dip that removes the metal polymer component to expose the oxide polymer component. The oxide polymer component is then subjected to a phosphoric acid dip that removes the oxide polymer component.

Abstract: Disclosed are methods and systems of etching copper containing materials so that they have smooth and/or planar surface. In this connection, the systems and methods employ two different solutions to accomplish the etching. The first solution oxidizes the surface of the copper containing material and forms a passivating film. The second solution removes the passivating film in a controlable manner.

Abstract: There is disclosed a chemical mechanical polishing method of an organic film comprising forming the organic film above a semiconductor substrate, contacting the organic film formed above the semiconductor substrate with a polishing pad attached to a turntable, and dropping a slurry onto the polishing pad to polish the organic film, the slurry being selected from the group consisting of a first slurry and a second slurry, the first slurry comprising a resin particle having a functional group selected from the group consisting of an anionic functional group, a cationic functional group, an amphoteric functional group and a nonionic functional group, and having a primary particle diameter ranging from 0.05 to 5 ?m, the first slurry having a pH ranging from 2 to 8, and the second slurry comprising a resin particle having a primary particle diameter ranging from 0.05 to 5 ?m, and a surfactant having a hydrophilic moiety.

Abstract: Silicon (12) is etched through a mask (11) comprising a layer of organic resin material (such as novolac) through which openings (32) are formed in the areas to be etched. The layer of organic resin is first deposited over a free surface of the device to be etched. The openings (32) are then formed by depositing droplets of a caustic etchant such as sodium hydroxide (NaOH) or potassium hydroxide (KOH) with an inkjet printer. The etchant reacts with the resin to expose the silicon surface in areas to be etched. The etching of the silicon surface is performed by applying a dilute solution of hydrofluoric acid (HF) and potassium permanganate (KMnO4) to the exposed surface through the openings in the mask to etch the silicon to a desired depth (83).

Abstract: A method for removing contamination on a semiconductor substrate is disclosed. The contamination contains at least one element belonging to one of 3A group, 3B group and 4A group of long-period form of periodic system of elements. The method comprises first and second process steps. The first process is wet processing the semiconductor substrate by first remover liquid that contains one of acid and alkali. The second process is wet processing the semiconductor substrate by second remover liquid that contains oxidizing reagent and one of hydrofluoric acid and salt of hydrofluoric acid.

Abstract: A process for fabricating an electron emitting device comprises a cathode electrode and a gate electrode are laminated through an insulating layer and an electron emitting film on the cathode electrode located in a gate hole penetrating through the gate electrode and the insulating layer. Wherein, a second hole penetrating through at least the gate electrode between the insulating layer and the gate electrode is juxtaposed with a first hole as a gate hole is formed, and the insulating layer between the second hole and the first hole in which the electron emitting film is deposited to the inner wall surface is etched until the first hole and the second hole are communicated with each other. Thereby, electron emitting film material is removed form the hole to reduce a leakage current.

Abstract: A wafer and the manufacturing and reclaiming methods thereof are disclosed. The wafer includes a semiconductor substrate and a protective layer formed on the surface of the semiconductor substrate. The reclaiming method of the wafer includes providing a wafer having a semiconductor substrate, a protective layer formed on the semiconductor substrate, and a polysilicon layer formed on the protective layer; and removing the polysilicon layer. The wafer and the reclaiming method of the wafer can prevent the substrate of the wafer from being destroyed during the reclaiming process and increase the reclaiming rate of the wafer.

Abstract: An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of a wafer. The composition is formulated according to the invention to provide a desired removal rate of the low-k dielectric and/or photoresist from the surface of the wafer. By varying the fluorine ion component, and the amounts of the fluorine ion component and acid, component, and controlling the pH, a composition can be formulated in order to achieve a desired low-k dielectric removal rate that ranges from slow and controlled at about 50 to about 1000 angstroms per minute, to a relatively rapid removal of low-k dielectric material at greater than about 1000 angstroms per minute.

Abstract: A method for rinsing and drying a workpiece includes placing the workpiece into a chamber and spinning the workpiece. A rinsing fluid, such as water, is applied onto the workpiece through a first outlet in the chamber, with the rinsing fluid moving outwardly towards the edge of the workpiece via centrifugal force, to rinse the workpiece. A drying fluid, such as an alcohol vapor, is applied onto the workpiece through the first outlet, with the drying fluid moving outwardly towards the edge of the workpiece via centrifugal force, to dry the workpiece. The drying fluid advantageously follows a meniscus of the rinsing fluid across the workpiece surface. The rinsing fluid, or the drying fluid, or both fluids, may be applied near or at a central area of the workpiece.

Abstract: A semiconductor device includes an element isolation insulating film provided in a semiconductor substrate between first and second element regions, a gate electrode running over the element isolation insulating film, first and second element regions, a first stopper film formed on the gate electrode and first element region to cover the first element region and giving a tensile stress, a second stopper film formed on the gate electrode and second element region to cover the second element region and giving a compressive stress, and a contact connected to the gate electrode on the element isolation insulating film. The first and second stopper films overlap each other at least partially on the element isolation insulating film, and a total thickness of the first and second stopper films on the gate electrode on the element isolation insulating film is smaller than a total thickness outside the gate electrode.

Abstract: An accelerator solution is globally applied to a workpiece to form an accelerator film, and then a portion of the accelerator film is selectively removed from the workpiece to form an acceleration region having a higher concentration of accelerator. The higher concentration of accelerator causes metal to deposit at a faster rate in the acceleration region than in a non-accelerated region for the duration of metal deposition. To make a metal feature, a resist layer is applied to a workpiece surface and patterned to form a recessed region and a field region. Then, a metal seed layer is deposited on the workpiece surface. An accelerator solution is applied so that an accelerator film forms on the metal seed layer. A portion of the accelerator film is selectively removed from the field region, leaving another portion of the accelerator film in the recessed region.

Abstract: A dual-tank etch method which is suitable for the stripping of a silicon nitride layer from a pad oxide layer provided on a substrate, and etching of the pad oxide layer to a desired target thickness, is disclosed. The method includes providing a first processing tank containing a silicon nitride-stripping chemical; stripping the silicon nitride layer from the pad oxide layer by placing the substrate in the first processing tank; providing a second processing tank containing an oxide-etching chemical; and etching the pad oxide layer to the desired target thickness by placing the substrate in the second processing tank. By carrying out the pad oxide-etching step and the silicon nitride-stripping step in separate processing tanks, accumulation of silicon oxide precipitates in the second processing tank is avoided.

Abstract: A method of preventing the formation of cracks on the backside of a silicon (Si) semiconductor chip or wafer during the processing thereof. Also provided is a method for inhibiting the propagation of cracks, which have already formed in the backside of a silicon chip during the processing thereof and prior to the joining thereto of a substrate during the fabrication of an electronic package. The methods entail either treating the backside with a wet etch, or alternatively, applying a protective film layer thereon prior to forming an electronic package incorporating the chip or wafer.

Abstract: This invention provides a process for treating a workpiece having a front side, a back side, and an outer perimeter. In accordance with the process, a processing fluid is selectively applied or excluded from an outer peripheral margin of at least one of the front or back sides or the workpiece. Exclusion and/or application of the processing fluid occurs by applying one or more processing fluids to the workpiece as the workpiece and corresponding reactor are spinning about an axis of rotation that is generally orthogonal to the center of the face of the workpiece being processed. The flow rate of the one or more processing fluids, fluid pressure, and/or spin rate are used to control the extent to which the processing fluid is selectively applied or excluded from the outer peripheral margin.

Abstract: A method of making a semiconductor structure, comprises cleaning a gate stack with a cleaning solution. The gate stack comprises a gate layer, a metallic layer on the gate layer, and a etch-stop layer on the metallic layer. The gate layer is on a semiconductor substrate, the cleaning solution is a non-oxidizing cleaning solution, and the metallic layer comprises an easily oxidized metal.

Abstract: A method of stripping a remnant metal is disclosed. The remnant metal is formed on a transitional silicide of a silicon substrate. Firstly, a surface oxidation process is performed on the transitional silicide, so as to form a protective layer on the transitional silicide. Then, a HPM stripping process is performed on the silicon substrate in order to strip the remnant metal.

Abstract: A method for forming a MEMS device using an amorphous silicon layer as a release layer includes etching superjacent films and using the amorphous silicon layer as an etch stop layer. The amorphous silicon layer is resistant to attack during the post-etch solvent stripping operation due to the oxidation of exposed portions of the amorphous silicon layer by use of an oxygen plasma.

Abstract: An organic acid/fluoride-containing solution etchant having high selectivity for BPSG to TEOS. In an exemplary situation, a TEOS layer may be used to prevent contamination of other components in a semiconductor device by the boron and phosphorous in a layer of BPSG deposited over the TEOS layer. The etchant of the present invention may be used to etch desired areas in the BPSG layer, wherein the high selectivity for BPSG to TEOS of etchant would result in the TEOS layer acting as an etch stop. A second etch with a known etchant may be utilized to etch the TEOS layer. The known etchant for the second etch can be less aggressive and, thus, not damage the components underlying the TEOS layer.

Abstract: The invention includes an atomic layer deposition method of forming a layer of a deposited composition on a substrate. The method includes positioning a semiconductor substrate within an atomic layer deposition chamber. On the substrate, an intermediate composition monolayer is formed, followed by a desired deposited composition from reaction with the intermediate composition, collectively from flowing multiple different composition deposition precursors to the substrate within the deposition chamber. A material adheres to a chamber internal component surface from such sequentially forming. After such sequentially forming, a reactive gas flows to the chamber which is different in composition from the multiple different deposition precursors and which is effective to react with such adhering material. After the reactive gas flowing, such sequentially forming is repeated. Further implementations are contemplated.

Abstract: A method of forming a resist pattern in a semiconductor device layer includes forming a buffer layer on a semiconductor device layer and forming a resist layer on the buffer layer. A decomposing agent is released into a portion of the buffer layer by a portion of the resist layer whereupon the portion of the buffer layer and the portion of the resist layer are removed to form a process window substantially free of resist residue that can be subsequently exploited for etching of the semiconductor device layer.

Abstract: Disclosed is a method for making flexible circuits in which portions of a tie layer are removed by etching the underlying polymer. Also disclosed are flexible circuits made by this method.

Abstract: A method for a substrate processing apparatus having a substrate holding mechanism and a chemical solution dispensing/sucking mechanism including a chemical solution dispensing port for supplying a first chemical solution and a chemical solution suction port, includes placing the target substrate on the substrate holding mechanism, laying out an auxiliary plate at a periphery of the substrate such that the two main faces are substantially flush with each other, supplying a second chemical solution onto the main faces, dispensing the first solution from the dispensing port and sucking the first and second solutions through the suction port, with the dispensing and suction ports brought into contact with the second solution, and while dispensing the first solution from the dispensing port and sucking the first solution through the suction port, scanning the dispensing/sucking mechanism such that the dispensing and suction ports are opposed to the main face of the substrate.