Abstract: A process for chemically etching a stereolithography resin involves chemically etching a shaped object of the resin at a temperature in a range of from about 20° C. to about 30° C. for a time of from about 30 seconds to about 60 seconds with a saturated aqueous solution of permanganate, for example potassium permanganate. The process is faster, simpler and uses less environmentally harmful chemicals than previous etching processes for SLA parts. Etching is also more thorough and can reach hard to access places that sand blasting cannot. The etching process may be part of a process for metallization of a rapid prototyping part fabricated by stereolithography. Excellent etch coverage leads excellent coverage by the coating metal and to stronger metal layers.

Abstract: A method for cleaning a substrate on which a silicon layer and a silicon germanium layer are formed and exposed, and method for fabricating a semiconductor device using the cleaning method are disclosed. The cleaning method comprises preparing a semiconductor substrate on which a silicon layer and a silicon germanium layer are formed and exposed; and performing a first cleaning sub-process that uses a first cleaning solution to remove a native oxide layer from the semiconductor substrate. The cleaning method further comprises performing a second cleaning sub-process on the semiconductor substrate after performing the first cleaning sub-process, wherein the second cleaning sub-process comprises using a second cleaning solution. In addition, the second cleaning solution comprises ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and deionized water (H2O), and the second cleaning solution comprises at least 200 times more deionized water (H2O) than ammonium hydroxide (NH4OH) by volume.

Abstract: A method for forming a structure formed by etching which is typified by a contact hole in the semiconductor and a method for manufacturing a display device using the structure. The etching method includes at least, forming an organic mask having a first opening portion and a second opening portion by patterning an organic film which includes either one of an organic film and a film with the addition of organic solvent and is located on a constituent part to be etched, and forming a transformed organic mask by dissolving the organic mask in contact with organic solvent and reflowing.

Abstract: An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that is subsequently removed from the surface of the substrate. The exposed metal may be oxidized by using solutions containing oxidizing agents such as peroxides or by using oxidizing gases such as those containing oxygen or ozone. The metal oxide produced is then removed using suitable metal oxide etching agents such as glycine. The oxidation and etching may occur in the same solution. In other embodiments, the exposed metal is directly etched without forming a metal oxide. Suitable direct metal etching agents include any number of acidic solutions. The process allows for controlled oxidation and/or etching with reduced pitting.

Abstract: There is provided a method for processing a semiconductor wafer subjected to a chamfering process, a lapping process, an etching process, and a mirror-polishing process, wherein acid etching is performed after alkaline etching as the etching process, and the acid etching is performed with an acid etchant composed of hydrofluoric acid, nitric acid, phosphoric acid, and water, a method for processing a semiconductor wafer subjected to a chamfering process, a surface grinding process, an etching process, and a mirror-polishing process, wherein the etching process is performed as described above, and a method for processing a semiconductor wafer subjected to a flattening process, an etching process, and a mirror-polishing process, wherein the etching process is performed as described above, a back surface polishing process is performed after the acid etching as the mirror-polishing process, and then a front surface polishing process is performed.

Abstract: An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of a wafer. The composition is formulated according to the invention to provide a desired removal rate of the low-k dielectric and/or photoresist from the surface of the wafer. By varying the fluorine ion component, and the amounts of the fluorine ion component and acid, component, and controlling the pH, a composition can be formulated in order to achieve a desired low-k dielectric removal rate that ranges from slow and controlled at about 50 to about 1000 angstroms per minute, to a relatively rapid removal of low-k dielectric material at greater than about 1000 angstroms per minute.

Abstract: A process of manufacturing a semiconductor device includes the steps of forming a stacked structure of a first III-V compound semiconductor layer containing In and having a composition different from InP and a second III-V compound semiconductor layer containing In. The second III-V compound semiconductor layer is formed over the first III-V compound semiconductor layer and growing an InP layer at regions adjacent the stacked structure to form a stepped structure of InP. The process further includes the step of wet-etching the stepped structure and the second III-V compound semiconductor layer using an etchant containing hydrochloric acid and acetic acid to remove at least the second III-V compound semiconductor layer.

Abstract: The present invention provides a method of fabricating an imprint mold for molding a structure. The method includes directing a first and a second flux for forming a first material and a second material, respectively, to a substrate to form a layered structure having alternating layers of the first and the second material. The method also includes controlling a thickness of the first and the second layers by controlling the first and the second flux and cleaving the layered structure to form a cleavage face in which sections of the layers are exposed. The method further includes etching the exposed sections of the layers using a etch procedure that predominantly etches one of the first and the second materials to form the mold having an imprinting surface with at least one indentation for molding the structure. At least one of the fluxes is controlled so that at least one of the layers has a thickness that varies along a portion of a length of the at least one layer.

Abstract: A combined wet etching method for stacked films which is capable of performing etching processes in a collective manner while controlling an amount of side-etching on each of stacked films and of making uniform side edges. In the wet etching method, two or more types of etching methods are performed in combination, on stacked films containing first and second films being deposited sequentially on a substrate and each having a different film property. The two or more types of wet etching methods include, at least, a first wet etching method in which side-etching on the first film is facilitated more than side-etching on the second film and a second wet etching method in which side-etching on the second film is facilitated more than side-etching on the first film.

Abstract: A method for manufacturing a silicon wafer includes a planarizing process 13 for polishing or lapping the upperside and lowerside surfaces of a thin disk-shaped silicon wafer obtained by slicing a silicon single crystal ingot, an etching process for dipping the silicon wafer into the etching liquid wherein silica powder is dispersed uniformly in an alkali aqueous solution, thereby etching the upperside and lowerside surfaces of the silicon wafer, and a both-side simultaneous polishing process 16 for polishing the upperside and lowerside surfaces of the etched silicon wafer simultaneously or a one-side polishing process for polishing the upperside and lowerside surfaces of the etched silicon wafer one after another, in this order.

Abstract: A method for removing mottled etch in a semiconductor fabricating process, prevents mottled etch from being generated after etching, by performing ashing using an oxide plasma, prior to performing wet etching using a photoresist pattern. The method for removing the mottled etch includes the steps of forming a gate oxide film on a semiconductor substrate; forming a photoresist pattern on the substrate; performing ashing using an oxygen plasma; and removing the oxide film consequently by wet etching, the oxide film being opened by the pattern.

Abstract: A method of fabricating polycrystalline silicon thin film transistor according to the present invention includes: depositing a buffer layer on a substrate; depositing an amorphous silicon layer on the buffer layer with a predetermined thickness; crystallizing the deposited amorphous silicon layer by using a laser to form a polycrystalline silicon layer; etching the crystallized polycrystalline silicon layer to a predetermined thickness; curing the etched polycrystalline silicon layer; and patterning the cured polycrystalline silicon layer to form a semiconductor layer.

Abstract: The occurrence of a package crack in the back vicinity of a die pad is restrained by making the outward appearance of the die pad of a lead frame smaller than that of a semiconductor chip which is mounted on it, and also the occurrence of a package crack in the main surface vicinity of the semiconductor chip is restrained by forming a layer of organic material with good adhesion property with the resin that constitutes the package body on the final passivation film (final passivation film) that covers the top layer of conductive wirings of the semiconductor chip.

Abstract: The invention includes methods for precisely and accurately etching layers of wide bandgap semiconductor material. According to one aspect of the invention, the method includes providing a multi-layer laminate including at least a first and second layer of wide bandgap semiconductor material, measuring a first conductance of the first layer of semiconductor material, partially etching the first layer of semiconductor material a first amount, measuring a second conductance of the first layer of semiconductor material etched the first amount, and utilizing the first and second measured conductance to determine a time required to etch the first layer of semiconductor material a second amount.

Abstract: A method for fabricating an optical device and micromechanical device, wherein both devices are monolithically-integrated with a substrate. The optical surfaces and micromechanical devices are each formed in an etch step that is well-suited for forming that device. In addition, the embodiments of the present invention enable the optical surface and micromechanical device to be fabricated irrespective of severe topography on the surface of the substrate.

Abstract: A low-k dielectric layer having a composition of silicon, oxygen and carbon is removed from a wafer. The low-k dielectric layer is removed by exposing a surface of the low-k dielectric layer to an oxygen-containing gas to oxidized the surface. The oxidized surface is immersed in an etching solution having HF and H2SO4 to etch the low-k dielectric layer. The etched surface is exposed to at least one of (i) an etching solution having H2SO4 and H2O2, and (ii) an RF or microwave energized oxygen-containing gas, to remove the low-k dielectric layer from the wafer.

Abstract: A method of etching silicon nitride substantially selectively relative to an oxide of aluminum includes providing a substrate comprising silicon nitride and an oxide of aluminum. The silicon nitride and the oxide is exposed to an etching solution comprising HF and an organic HF solvent under conditions effective to etch the silicon nitride substantially selectively relative to the oxide. Other aspects and implementations are contemplated.

Abstract: A method of etching a semiconductor substrate is described, the method comprising the steps of applying a paste containing an etchant to the substrate, and carrying out a thermal processing step to etch a part or a layer of the substrate where the paste has been applied. The etchant paste is preferably a caustic etching paste. The etchant paste may be applied selectively to a major surface of the substrate to form a pattern of applied paste. For example, the paste may be applied by a printing method, such as screen-printing. The method may be used to produce solar cells.

Abstract: A method for the caustic etching of silicon which is of importance for the semiconductor industry and silicon wafer manufacture in particular, that includes using one or more iodate or chlorite salts as additives in the etching process to achieve improved surface conditions, such as smaller facets and lower roughness, on the resulting silicon substrate.

Abstract: Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow trenches at additional locations. Etching of the shallow and deep trenches then proceeds simultaneously.

Abstract: A high reverse voltage diode includes a hetero junction made up from a silicon carbide base layer, which constitutes a first semiconductor base layer, and a polycrystalline silicon layer, which constitutes a second semiconductor layer, and whose band gap is different from that of the silicon carbide base layer. A low concentration N type polycrystalline silicon layer is deposited on a first main surface side of the silicon carbide base layer, and a metal electrode is formed on a second main surface side of the silicon carbide base layer which is opposite to the first main surface side thereof.

Abstract: Disclosed is a method for non-destructive removal of cured epoxy from a wafer backside. A wafer back-coated with epoxy is soaked in an acetone bath for a period of time, allowing degradation of the epoxy coating adhesion strength. The epoxy coating is then peeled or scraped away, leaving the wafer backside ready for a rework or for a reapplication of a new epoxy coating.

Abstract: A process for the wet chemical treatment of semiconductor wafers, in which the semiconductor wafers are treated with treatment liquids, has the semiconductor wafers firstly treated with an aqueous HF solution, then treated with an aqueous O3 solution and finally treated with water or an aqueous HCl solution, these treatments forming a treatment sequence.

Abstract: A method for providing whisker-free aluminum metal lines or aluminum alloy lines in integrated circuits includes the following steps: providing a substrate; providing a whisker-containing layer made of aluminum metal or an aluminum alloy on the substrate; back-etching and/or resputtering the whisker-containing layer such that the whiskers are essentially removed; and structuring the whisker-free layer into the lines.

Abstract: The present invention relates to a method for selectively removing a high-k material comprising providing a high-k material on a semiconductor substrate, and contacting the high-k material with a solution comprising HF, an organic compound, and an inorganic acid.

Abstract: A method of preparing a silicon layer or substrate surface for growing an epitaxial layer of SiGe thereon. The process comprises removing native oxide from the surface of the silicon with an HF solution, and then oxidizing the exposed silicon surface to form a chemically formed layer of silicon oxide of the process damaged silicon surface. The chemically formed layer of silicon oxide is then removed by a second HF cleaning process so as to leave a smooth silicon surface suitable for growing a SiGe layer.

Abstract: A method for etching a metal layer is described. That method comprises forming a metal layer on a substrate, then exposing part of the metal layer to a wet etch chemistry that comprises an active ingredient with a diameter that exceeds the thickness of the metal layer.

Abstract: A pattern forming method of the present invention includes the steps of forming, on a substrate before droplets are ejected onto the substrate, a water repelling area, in which a contact angle between the droplet and the target surface is a first contact angle, and a water attracting line, which is adjacent to the water repelling area and in which a second contact angle is smaller than the first contact angle and which is to be the pattern to be formed; and landing droplets onto the target surface such that part of the droplet landed is in a water repelling area and part of the droplet landed is in a water attracting line, the equation (1) is satisfied, D?L×{1+2(cos ?2?cos ?1)}??(1) where D is a droplet diameter, L is a pattern width, ?1 is a first contact angle, and ?2 is a second contact angle. By decreasing the number of discharged droplets, it is possible to prevent increase of a tact time and decrease of an inkjet operating life.

Abstract: A process for treating a copper or copper alloy substrate surface with a composition and corrosion inhibitor solution to minimize defect formation and surface corrosion, the method including applying a composition including one or more chelating agents, a pH adjusting agent to produce a pH between about 3 and about 11, and deionized water, and then applying a corrosion inhibitor solution. The composition may further comprise a reducing agent and/or corrosion inhibitor. The method may further comprise applying the corrosion inhibitor solution prior to treating the substrate surface with the composition.

Abstract: An ultrasonic etching apparatus for chemically-etching a workpiece is disclosed. The apparatus includes an outer tank at least partially filled with an aqueous solution, an inner tank at least partially disposed within the outer tank and in contact with aqueous solution, the inner tank at least partially filled with an etching solution, a lid engaged with the mouth of said inner tank; and an ultrasonic transducer coupled to the outer tank to impart ultrasonic energy to the etching solution in said inner tank. Also disclosed are methods of using the apparatus to etch workpieces.

Abstract: A method and intermediate structure for improving the thinning and planarity of a wafer back side utilizing planarization material applied to the back side prior to at least one portion of the thinning operation and which is subsequently removed concurrently with the wafer material by one or more suitable thinning or planarization techniques. The planarization material may be applied as a thin layer or film of a hardenable material to the rough, bare back side of a wafer to produce a planar surface when hardened. The planarization material is selected to exhibit a material removal rate approximating the removal rate of the wafer material for a given removal technique such as etching, mechanical abrasion or chemical-mechanical planarization (CMP). This approach to wafer thinning and planarization results in improved process control in the form of uniform material removal rates, reduction in wafer warpage, final surface smoothness and planarity, and even distribution of residual stresses.

Abstract: Disclosed is a method of forming the isolation film in the semiconductor device. The method comprises the steps of sequentially forming a pad oxide film and a pad nitride film on a silicon substrate, forming a photoresist pattern through which an isolation region is opened, on the pad nitride film, etching the pad nitride film and the pad oxide film using the photoresist pattern as an etch mask, thus exposing the silicon substrate of the isolation region, implementing an electrochemical etch process to form porous silicon in the silicon substrate of the exposed isolation region, removing the photoresist pattern, and implementing a thermal oxidization process to oxidize porous silicon, thereby forming an oxide film in the isolation region.

Abstract: A process for producing multiple undercut profiles in a single material. A resist pattern is applied over a work piece and a wet etch is performed to produce an undercut in the material. This first wet etch is followed by a polymerizing dry etch that produces a polymer film in the undercut created by the first wet etch. The polymer film prevents further etching of the undercut portion during a second wet etch. Thus, an undercut profile can be obtained having a larger undercut in an underlying portion of the work piece, utilizing only a single resist application step. The work piece may be a multi-layer work piece having different layers formed of the same material, or it may be a single layer of material.

Abstract: An object of the present invention is to provide a wafer cleaning apparatus for cleaning wafers that have received various processing such as copper plating and chemical mechanical polishing. An apparatus for cleaning front and back surfaces of a wafer with solution while rotating the wafer that has been subjected to a fabrication process is disclosed. The apparatus comprises cleaning nozzles for spraying a cleaning solution, respectively, onto a front surface of the wafer that has been processed and onto a back surface thereof and also comprises an etching nozzle for spraying an etching solution onto a vicinity of the outer periphery of the wafer.

Abstract: A method of patterning a layer of high-k dielectric material is provided, which may be used in the fabrication of a semiconductor device. A first etch is performed on the high-k dielectric layer. A portion of the high-k dielectric layer being etched with the first etch remains after the first etch. A second etch of the high-k dielectric layer is performed to remove the remaining portion of the high-k dielectric layer. The second etch differs from the first etch. Preferably, the first etch is a dry etch process, and the second etch is a wet etch process. This method may further include a process of plasma ashing the remaining portion of the high-k dielectric layer after the first etch and before the second etch.

Abstract: A method of etching silicon nitride substantially selectively relative to an oxide of aluminum includes providing a substrate comprising silicon nitride and an oxide of aluminum. The silicon nitride and the oxide is exposed to an etching solution comprising HF and an organic HF solvent under conditions effective to etch the silicon nitride substantially selectively relative to the oxide. Other aspects and implementations are contemplated.

Abstract: A precursor that may be imaged by heat is made up of a substrate, for example a copper board, and a composite layer structure composed of two layers. Preferably, the first layer is composed of an aqueous developable polymer mixture containing a photothermal conversion material, which is contiguous to the substrate. The second layer of the composite is composed of one or more non-aqueous soluble polymers, which are soluble or dispersible in a solvent which does not dissolve the first layer. The precursor is exposed with an infrared laser or a thermal print head, and upon aqueous development, the exposed regions are removed, revealing regions of the substrate surface able to be etched or otherwise treated. The second layer may also contain a photothermal conversion material. Alternatively, the composite layer may be free of photothermal conversion material when thermal imaging is carried out using a thermal print head. The precursor may be used, for example, as a mask precursor or electronic part precursor.

Abstract: In a method for photo-electrochemical etching of a semiconductor sample, the semiconductor sample is brought in contact with an electrolyte liquid. The contact area formed thereby is illuminated through the electrolyte liquid with UV light. The photo-current created by UV light irradiation at the contact area is measured. To increase the etching quality, a jet of fresh electrolyte liquid is repeatedly applied to the contact area. A device for carrying out the method includes a container to be filled with an electrolyte liquid, a UV source for illuminating the semiconductor sample with UV light through the electrolyte liquid, and a measuring instrument for measuring the photo-current created during UV light irradiation of the contact area. Further provided are an inlet for supplying fresh electrolyte liquid, directed towards the semiconductor sample, and a device attached to the inlet for repeated production of electrolyte fluid jets, directed towards the semiconductor sample.

Abstract: A method for cleaning semiconductor substrates includes a DI water clean operation that uses a spin speed no greater than 350 rpm. The cleaning method may include additional cleaning operations such as an organic clean, an aqueous chemical clean or a DI water/ozone clean. The cleaning method may be used to clean substrates after the conclusion of an etching procedure which exposes a single film between a Cu-containing conductive material and the environment. The spin speed of the DI water clean operation prevents copper corrosion due to breakdown of the film that separates the Cu-containing conductive material from the environment.

Abstract: A method of masking and etching a semiconductor substrate includes forming a layer to be etched over a semiconductor substrate. An imaging layer is formed over the layer to be etched. Selected regions of the imaging layer are removed to leave a pattern of openings extending only partially into the imaging layer. After the removing, the layer to be etched is etched using the imaging layer as an etch mask. In one implementation, an ion implant lithography method of processing a semiconductor includes forming a layer to be etched over a semiconductor substrate. An imaging layer of a selected thickness is formed over the layer to be etched. Selected regions of the imaging layer are ion implanted to change solvent solubility of implanted regions versus non-implanted regions of the imaging layer, with the selected regions not extending entirely through the imaging layer thickness.

Abstract: A method is provided herein for cleaning a semiconductor device. In accordance with the method, a semiconductor device is provided (11), and a micellar solution is applied (13) to the semiconductor device. The method is particularly useful for cleaning copper and silicon surfaces and removing processing residues from the surfaces of vias or trenches.

Abstract: A method of fabricating final spacers having a target width comprises the following steps. Initial spacers, each having an initial width that is less than the target width, are formed over the opposing side walls of a gate electrode portion. The difference between the initial spacer width and the target width is determined. A second spacer layer having a thickness equal to the determined difference between the initial width of the initial spacers and the target width is formed upon the initial spacers and the structure. The second spacer layer is etched to leave second spacer layer portions extending from the initial spacers to form the final spacers.

Abstract: Shallow trench isolation structures are simultaneously fabricated such that ones in a cell region have first-type features and others in a periphery region have second-type features. The first-type features can be rounded edges or can be first depths and widths, and the second-type features can be unrounded edges or can be second depths and widths which are different from the first depths and widths. The method includes forming patterned photoresist over a hard mask over portions of a cell and a periphery region, and removing the exposed hard mask layer in the periphery region while removing a portion of the exposed hard mask layer in the cell region. A trench is then partially formed in the periphery region and more of the hard mask layer is removed in the cell region, followed by the trench in the periphery region being deepened while a trench in the cell region is formed.

Abstract: The occurrence of a package crack in the back vicinity of a die pad is restrained by making the outward appearance of the die pad of a lead frame smaller than that of a semiconductor chip which is mounted on it, and also the occurrence of a package crack in the main surface vicinity of the semiconductor chip is restrained by forming a layer of organic material with good adhesion property with the resin that constitutes the package body on the final passivation film (final passivation film) that covers the top layer of conductive wirings of the semiconductor chip.

Abstract: An electron-emitting device including a protective layer that is formed on a catalyst layer to protect the catalyst layer from the deleterious environmental conditions before or during a cathode process. The present invention further includes a half etching process that is adapted to partially remove portions of the protective layer from the catalyst layer to etch the catalyst layer except carbon nano-tube growing portions. Portions of the protective layer still remain on the catalyst layer to protect the catalyst layer from the deleterious conditions from next cathode formation process.

Abstract: A resist film and a polymer layer adhered on a semiconductor substrate can be removed by the method according to the present invention. A first processing liquid, typically including a oxidizing agent, such as hydrogen peroxide solution, is fed to the substrate, thereby the condition of the resist film and the polymer layer is changed. Next, a second processing liquid, typically including a dimethyl sulfoxide and an amine solvent, is fed to the substrate, thereby the resist film and the polymer layer is dissolved and lifted off from the substrate. A sputtered copper particles included in the polymer layer can also be removed.

Abstract: Methods and apparatus for fabricating and cleaning in-process semi-conductor wafers are provided. An in-process wafer is placed within a closed chamber. A reactant gas is incorporated in a liquid solvent to form a “reactant mixture” that is capable of reacting with photoresist material (or other material) on a wafer surface to facilitate removal of the material from the wafer surface. The reactant mixture is condensed on one or more of the in-process wafer surfaces to form a thin film on the surface(s) of the wafer. The solvent in the reactant mixture acts as a transport medium to place the reactant gas on the wafer surface. The reactant gas is then able to react with the photoresist material (or other material) on the in-process wafer surface to effect removal the material. Following reaction of the reactant gas with the photoresist, the thin film of reactant mixture is removed from the wafer surface by flash heating, rinsing, draining, or other suitable means.

Abstract: A method of forming a shallow trench isolation is disclosed. An example method of forming a shallow trench isolation performs a planarization process for a substrate on which a hard mask and an insulation layer are formed, selectively etching the insulation layer on the edge of the substrate by using wet etch equipment, and performs a main etching process in the center region of the substrate.

Abstract: A method is provided for eliminating a polish stop layer from a polishing process. In particular, a method is provided which may include polishing an upper layer of a semiconductor topography to form an upper surface at an elevation above an underlying layer, wherein the upper surface does not include a polish stop material. Preferably, the upper surface of the topography formed by polishing is spaced sufficiently above the underlying layer to avoid polishing the underlying layer. The entirety of the upper surface may be simultaneously etched to expose the underlying layer. In an embodiment, the underlying layer may comprise a lateral variation in polish characteristics. The method may include using fixed abrasive polishing of a dielectric layer for reducing a required thickness of an additional layer underlying the dielectric layer. Such a method may be useful when exposing an underlying layer is desirable by techniques other than polishing.

Abstract: A method of manufacturing a semiconductor device, including the steps of (a) rowing an InP layer on a surface of starting growth, resulting in the InP layer having a convex structure, and (b) wet etching the InP layer by an enchant including hydrochloric acid and acetic acid, and thereby flattening a surface of the InP layer.