Abstract: A method for removing organometallic and organosilicate residues remaining after a dry etch process from semiconductor substrates. The substrate is exposed to a conditioning solution of a fluorine source, a non-aqueous solvent, a complementary acid, and a surface passivation agent. The fluorine source is typically hydrofluoric acid. The non-aqueous solvent is typically a polyhydric alcohol such as propylene glycol. The complementary acid is typically either phosphoric acid or hydrochloric acid. The surface passivation agent is typically a carboxylic acid such as citric acid. Exposing the substrate to the conditioning solution removes the remaining dry etch residues while minimizing removal of material from desired substrate features.

Abstract: A method for removing fluorine-containing etching residues during dual damascene process comprises providing a dual damascene structure having a copper conductor structure therein, a cap layer formed on the copper conductor structure and the dual damascene structure, and a low dielectric constant dielectric layer on the cap layer. The low dielectric constant dielectric layer formed by spin-on polymer method has at least an opening above the copper conductor structure. The cap layer is etched by fluorine-containing plasma to expose the copper conductor structure. The dual damascene structure is cleaned with a solvent and then the fluorine-containing etching residues are removed by plasma sputtering treatment or baking, or by a combination of both. The addition of baking and plasma sputtering treatment can prevent poor adhesion between the subsequent metal diffusion barrier layer and the low dielectric constant dielectric layer.

Abstract: A ruthenium containing metal 6′ adhering to a periphery of a device forming area, an end face and a rear face in a silicon substrate 10 is removed using a first remover containing (a) at least one compound selected from the group consisting of salts containing chlorate, perchlorate, iodate, periodate, salts containing bromine oxide ion, salts containing manganese oxide ion and salts containing tetravalent cerium ion and (b) at least one acid selected from the group consisting of nitric acid, acetic acid, iodic acid and chloric acid. After the removing treatment, the substrate is washed with hydrofluoric acid to remove the residual remover.

Abstract: A method for completely removing dielectric layers formed selectively upon a substrate employed within a microelectronics fabrication from regions wherein closely spaced structures such as self-aligned metal silicide (or salicide) electrical contacts may be fabricated, with improved properties and with attenuated degradation. There is first provided a substrate with employed within a microelectronics fabrication having formed thereon patterned microelectronics layers with closely spaced features. There is then formed a salicide block layer employing silicon oxide dielectric material which may be selectively doped. There is then formed over the substrate a patterned photoresist etch mask layer. There is then etched the pattern of the patterned photoresist etch mask layer employing dry plasma reactive ion etching. An anhydrous etching environment is then employed to completely remove the silicon oxide dielectric salicide block layer with attenuated degradation of the microelectronics fabrication.

Abstract: A substrate with striped ridge patterns formed on the surface thereof is transported along a transport path. A relationship is determined between the direction of the striped ridge patterns on the substrate surface and the direction of jetting out fluid to the substrate surface. The fluid is jetted out and blown to the substrate surface along the direction satisfying the determined relationship to process the surface of the substrate. It is possible to reliably perform a surface process of each substrate irrespective of different directions of striped ridge patterns on substrate surfaces.

Abstract: According to a method for manufacturing a semiconductor device having a junction boundary where SiGe of a first conductivity type and Si or SiGe of a second conductivity type come in contact with each other, a portion where the junction boundary is exposed on the surface is cleaned with a first solution containing hydrofluoric acid and is then cleaned with a second solution containing sulfuric acid.

Abstract: A method for using an organic dielectric as a sacrificial layer for forming suspended or otherwise spaced structures. The use of an organic dielectric has a number of advantages, including allowing use of an organic solvent or etch to remove the sacrificial layer. Organic solvents only remove organic materials, and thus do not affect or otherwise damage non-organic layers such as metal layers. This may reduce or eliminate the need for the rinsing and drying steps often associated with the use of acidic etchants such as Hydrofluoric Acid.

Abstract: One embodiment of the present invention provides a process for selective etching during semiconductor manufacturing. The process starts by receiving a silicon substrate with a first layer composed of a first material, which is covered by a second layer composed of a second material. The process then performs a first etching operation that etches some but not all of the second layer, so that a portion of the second layer remains covering the first layer. Next, the system performs a second etching operation to selectively etch through the remaining portion of the second layer using a selective etchant. The etch rate of the selective etchant through the second material is faster than an etch rate of the selective etchant through the first material, so that the second etching operation etches through the remaining portion of the second layer and stops at the first layer.

Abstract: The present invention discloses a method of forming a slope lateral structure. In this invention, the silicon nitride and the silicon hydroxide with different etching rates are used. Thus, when the silicon nitride is etching, the top and laterals portion of the silicon hydroxide is suffering the slight etching. So that, when the silicon nitride is etched completely, a slope lateral silicon hydroxide is formed, because of the different etching time on the top and the bottom portion of the silicon hydroxide. Using the present invention, the conventional NROM process problem, which the wordlines are connected by the residue on the laterals of the protective layer after etching process can be solved.

Abstract: A method for cutting Group III nitride semiconductor light emitting element comprises the step of discharge-etched on a front face of a chip or cutting channel of a substrate; and breaking on a back surface of the discharge-etching face to be formed with dies. This method is different from the prior art dicing saw and point scribe. Thus, the cutting time is shortened. The consumption of the diamond knife from cutting is reduced. The yield ratio of dies is improved and the outlook is also improved.

Abstract: A method of masking and etching a semiconductor substrate includes forming a layer to be etched over a semiconductor substrate. An imaging layer is formed over the layer to be etched. Selected regions of the imaging layer are removed to leave a pattern of openings extending only partially into the imaging layer. After the removing, the layer to be etched is etched using the imaging layer as an etch mask. In one implementation, an ion implant lithography method of processing a semiconductor includes forming a layer to be etched over a semiconductor substrate. An imaging layer of a selected thickness is formed over the layer to be etched. Selected regions of the imaging layer are ion implanted to change solvent solubility of implanted regions versus non-implanted regions of the imaging layer, with the selected regions not extending entirely through the imaging layer thickness.

Abstract: An improved method of forming a semiconductor device is described. The method comprises forming a dielectric layer on a substrate, forming a photoresist layer on the dielectric layer, then patterning the photoresist layer to define a region to be etched. After forming an etched region within the dielectric layer, the photoresist layer is removed and the etched region is cleaned. The etched region is cleaned by applying a buffered oxide etch dip, followed by an amine based dip.

Abstract: A method of manufacturing a semiconductor device, having a resist-removing step which is improved so as not to etch a peripheral material and damage the peripheral material is provided. A resist pattern is formed on a substrate. Using the resist pattern as a mask, the substrate is etched. A surface-deteriorated layer of the resist pattern is removed by a first chemicals treatment. A bulk portion of the resist pattern is removed by a second chemicals treatment.

Abstract: Etching method applicable to a semiconductor device fabrication and an MEMS(Micro-Electro-Mechanical System) process, including the steps of forming an etching mask on a substrate, forming a plurality of patterns in the etching mask corresponding to depths of the plurality of trenches; and etching the substrate using the etching mask having the plurality of patterns formed therein, whereby eliminating an alignment error in respective photolithography, that permits to form a precise structure, simplify a fabrication process, and reduce a production cost.

Abstract: A process for forming a metal silicide layer on the surface of a conductive region in a semiconductor substrate, located at the bottom of a contact hole formed in an insulator layer, has been developed. The process features the removal of a photoresist shape, used to define the contact hole, via removal procedures that avoid the formation of a substoichiometric, silicon oxide, native oxide layer, on the top surface of the conductive region. The removal of the contact hole defining photoresist shape is realized via a chemical mechanical polishing procedure, which results in no native oxide formation, or removal of the photoresist shape can be accomplished via a combination of chemical mechanical polishing and wet clean procedure, which will form a native oxide layer, however only comprised of easily removable stoichiometric silicon oxide.

Abstract: A method of cleaning polycide gates after an etching step. A gate oxide layer, a polysilicon layer, a titanium nitride layer, a silicide layer, an anti-reflection layer and a patterned photoresist layer are sequentially formed over a substrate. An etching operation is next carried out to form a gate structure. The gate structure is formed by patterning the polysilicon layer, the titanium nitride layer and the silicide layer. The gate structure is subsequently cleaned in a three-step cleaning operation. In the first cleaning step, minute amount of fluoride-containing compound, hydrogen and inert gas are used as gaseous reactants in a plasma-cleaning operation. The fluoride-containing compound is capable of initiating a free radical chain reaction. In the second cleaning step, a solvent containing ammonium ions is applied to the gate structure. In the third cleaning step, a solution formed by dissolving oxidizing agent in de-ionized water is applied.

Abstract: There is described a method of manufacturing a semiconductor device for accurately and anisotropically etching desired locations on a semiconductor wafer at high selectivity. A polysilicon layer which is to act as a floating gate is embedded in the surface of an oxide film insulating layer. Control gates are formed in a direction orthogonal to the polysilicon layer. Exposed portions of the polysilicon layer are subjected to dry-etching, thereby forming a floating gate. Residues remaining in the channels formed in the oxide film insulating layer are removed by means of wet etching.

Abstract: Cu metallization is treated to reduce defects and effect passivation by removing a thin surface layer or removing corrosion stains, subsequent to CMP and barrier layer removal, employing a cleaning composition comprising deionized water, an acid and ammonium hydroxide and/or an amine. Embodiments include removing up to about 100 Å of the Cu metallization surface in a damascene opening by sequentially treating the exposed Cu surface with: an optional corrosion inhibitor; a solution having a pH of about 4 to about 11 and containing an acid, ammonium hydroxide and/or an amine, and deionized water; and a corrosion inhibitor.

Abstract: A method of manufacturing a semiconductor device, which comprises the steps of providing a substrate having a groove on the surface thereof, forming a burying film on the substrate to thereby fill the groove with the burying film, performing a first polishing step to polish the burying film by means of a CMP method, the polishing being suspended before the substrate is exposed, and performing a second polishing step to polish the burying film by means of a CMP method until part of the burying film which is disposed outside the groove is removed. The time to finish polishing of the second polishing step is determined based on a film thickness of the burying film which is left remained after finishing the first polishing step. The first polishing step may be performed under a condition which differs from that of the second polishing step.

Abstract: In the manufacture of an integrated circuit, contaminated oxide is replaced by relatively pure oxide using the following steps. First, a partially manufactured integrated circuit is bathed in an aqueous solution of hydrogen peroxide and ammonium hydroxide to oxidize organic materials and weaken bonds of metal contaminants to the integrated circuit substrate. Second, an aqueous rinse removes the oxidized organic materials and metal contaminants. Third, the integrated circuit is bathed in an aqueous solution of hydrogen fluoride and nitric acid. The hydrogen fluroide etches the contaminated oxide; the nitric acid combines with calcium and metal contaminants freed as the oxide is etched. The resulting nitride byproducts are highly soluble and easily removed in the following aqueous rinse. A drying step removes rinse water from the integrated circuit. Finally, an oxide formation step provides a relatively pure oxide layer.

Abstract: According to an example embodiment, a semiconductor device having a back side and a circuit side opposite the back side is analyzed. The semiconductor device includes bulk silicon in the back side and also includes epitaxial silicon. A wet etch solution comprising aqueous tetramethylammonium hydroxide (TMAHW) is directed at the back side. Using the wet etch solution, the back side is selectively etched and an exposed region is formed. The etching is selective to the bulk silicon. When the etching process encounters the epitaxial silicon, the etch rate slows and is used as an endpoint indicator of the selective etching process. Once the etching process is stopped, the circuitry is accessed via the exposed region.

Abstract: A method and apparatus for analyzing a semiconductor surface obtains a sample from a localized section of a wafer. The sample is obtained by isolating a section of a wafer with a sampling apparatus, dispensing liquid onto the isolated section of the wafer, dissolving compounds of interest in the liquid, removing a portion of the liquid, and analyzing the liquid and dissolved compounds of interest. The liquid can be an etching solution, an organic solvent, or other suitable solvent. Samples and analyses can, thus, be obtained as a function of position on the wafer. Analyses as a function of depth can also be determined by sampling and analyzing an isolated portion of the wafer as a function of time.

Abstract: A method for forming shallow trench isolations includes the steps of defining a wafer substrate, forming a silicon dioxide insulating layer on the substrate, depositing a silicon nitride layer on the silicon dioxide insulating layer, and forming at least one trench in the substrate through the silicon dioxide and silicon nitride layers. The method also includes the steps of depositing a silicon dioxide layer over the silicon nitride layer and in the trench, removing the silicon dioxide layer deposited over the silicon nitride layer, anisotropically etching the silicon dioxide layer to produce silicon dioxide sidewalls in the trench contiguous with the silicon nitride layer, isotropically etching to remove the sidewalls and removing the silicon nitride layer.

Abstract: A method of preparing for structural analysis a deep trench-type capacitor formed in a die employs a combination of mechanical and chemical action to expose the trench-type capacitors. The method of preparing the die includes the steps of (a) mechanically treating the die back side so as to remove a first portion of the substrate and leave intact a second portion of the substrate; (b) mounting the mechanically treated die by affixing the die by its top side to a mount; and (c) chemically treating the mounted die so as to remove the substrate second portion and provide a chemically treated die. By exposing the deep trench capacitors, the method facilitates the inspection of the device for the detection of possible structural defects such as metal shorts, capacitor holes, and particle failures. The method further overcomes the deficiencies associated with conventional methods of substrate removal, and facilitates inspection by a variety of methods.

Abstract: An etching method and an etching apparatus are provided. Silicon (Si) from surfaces semiconductor wafers W dissolves into an etching liquid E stored in a process bath 10. On detection of the concentration of silicon by a concentration sensor 50, the etching liquid E in the process bath 10 is discharged while leaving a part of the etching liquid when the Si concentration in the etching liquid E reaches a designated concentration. After that, a new etching liquid of substantially equal to an amount of the discharged etching liquid E is supplied into the process bath 10 and added to the etching liquid remaining in the bath 10. Consequently, it is possible to restrict the etching rate just after the exchange of etching liquid from rising excessively.

Abstract: The present invention relates to low dielectric constant nanoporous silica films and to processes for their manufacture. A substrate, e.g., a wafer suitable for the production of an integrated circuit, having a plurality of raised lines and/or electronic elements present on its surface, is provided with a relatively high porosity, low dielectric constant, silicon-containing polymer film composition.

Abstract: A silicon etching method includes providing a substrate assembly including an exposed silicon region and an exposed oxide region. An etch composition including an ammonium fluoride component, an inorganic acid component, and an oxidizing agent is also provided. The etch composition has a pH in the range of about 7.0 to about 8.0. The substrate assembly is exposed to the etch composition. Exposing the substrate assembly to the etch composition may result in etching the exposed silicon region at an etching rate that is greater than about 3 times the etching rate of the exposed oxide region and/or etching the silicon region at an etch rate greater than about 9 Å/minute. The etching method may be used in forming isolation structures. Further, etch compositions for performing the desired etch are provided.

Abstract: Planarizing machines and methods for selectively using abrasive slurries on fixed-abrasive planarizing pads in mechanical and/or chemical-mechanical planarization of microelectronic substrate assemblies. In one embodiment of a method in accordance with the invention, a microelectronic substrate is planarized by positioning a fixed-abrasive planarizing pad on a table of a planarizing machine, covering at least a portion of a planarizing surface on the pad with a first abrasive planarizing solution during a first stage of a planarizing cycle, and then adjusting a concentration of the abrasive particles on the planarizing surface at a second stage of the planarizing cycle after the first stage. The concentration of the second abrasive particles can be adjusted during the second stage of the planarizing cycle by coating the planarizing surface with a non-abrasive second planarizing solution without abrasive particles during the second stage.

Abstract: An aqueous thiourea-ammonia treatment is used to form a thin sulfurous film at the indium phosphide surface, having a thickness of less than one nanometer. The thiourea-ammonium hydroxide treatment can be used as is or immediately prior to deposition of cadmium sulfide for enhanced surface passivation. The thiourea-ammonium hydroxide treatment is entirely compatible with chemical bath deposition, molecular beam epitaxy, or metalorganic chemical vapor deposition of the cadmium sulfide.

Abstract: Spacers are formed on a semiconductor device by depositing a spacer layer on the semiconductor device. The semiconductor device is subjected to an anisotropic etching process to leave at least a portion of the spacer layer covering the semiconductor device. The semiconductor device is then subjected to an isotropic etching process to form the spacers on the semiconductor device.

Abstract: A nonvolatile memory system is described. The system includes ferroelectric memory cells each comprising a pair of metal plates and a ferroelectric material therebetween. Data are stored in the cells by applying an electric field corresponding to the desired data value across a given cell, thereby setting the polarity of the ferroelectric material to a given state. A datum is read from a cell by a mechanical force to the ferroelectric material and sensing charge induced on one of the cells.

Abstract: A method for controlling striations and CD loss in a plasma etching method is disclosed. During the etching process, the substrate of semiconductor material to be etched is exposed first to plasma under a low power strike and subsequently to a conventional high power strike. CD loss has been found to be reduced by about 400 Angstroms and striations formed in the contact holes are reduced.

Abstract: Methods for manufacturing a semiconductor device, in which a chamfered metal silicide layer is formed by a 2-stage continuous wet etching process using different etchants, thereby resulting in a sufficient insulation margin between a lower conductive layer including the metal silicide layer and the contact plug self-aligned with the lower conductive layer are disclosed. In the manufacture of a semiconductor device, a mask pattern is formed on a metal silicide layer to expose a portion of the metal silicide layer. The exposed portion of the metal silicide layer is isotropically etched in a first etchant to form a metal silicide layer with a shallow groove, and defects due to the silicon remaining on the surface of the metal silicide layer with the shallow groove are removed using a second etchant, to form a metal silicide layer with a smooth surface. Microelectronic structures produced by methods of the present invention are also disclosed.

Abstract: A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an alignment mark area of a silicon wafer in process during the formation of integrated circuits thereon. The process comprising the steps of aligning said area of said wafer, such as an alignment mark on the wafer, to an etchant dispensing apparatus, placing the surface of the wafer adjacent at least a portion of an annular portion of the etchant dispensing apparatus, dispensing at least one etchant onto said area of said wafer, such as an alignment mark, and removing the at least one etching from the wafer.

Abstract: A top IC die is removed from a bottom IC die in a multichip IC package while substantially preserving interconnect of the bottom IC die for proper fault isolation during testing of the multichip IC package. The top IC die is attached to the bottom IC die with a die attach material within the multichip IC package. The top IC die has a first area that is smaller than a second area of the bottom IC die, and the top IC die is disposed inward from any edge of the bottom IC die such that a perimeter area of the bottom IC die is outside the top IC die. A predetermined area of the top IC die is exposed with the predetermined area being smaller than the first area of the top IC die. The predetermined area is disposed inward from any edge of the top IC die. The first area of the top IC die outside the predetermined area remains covered, and the perimeter area of the bottom IC die remains covered.

Abstract: The high Q inductor process for reducing substrate interaction of integrated inductors includes etching away some of the silicon substrate after the inductor has been formed on the substrate. A first etch process is performed to form an opening in the center of the inductor exposing the silicon substrate. A second etch process is performed to etch the exposed silicon substrate to form a trench in the silicon substrate. A third etch process is performed to etch the trench into an inverted pyramidal cavity within the substrate and extending beneath the inductor. The pyramidal cavity is then filled with a solution, such as spin-on-glass thereby providing mechanical support for the inductor.

Abstract: A semiconductor substrate is dipped into a contaminating treatment liquid whose pH value is controlled depending on the property of metal impurities, so as to produce a sample contaminated with metal of a desired concentration. Alternatively, a semiconductor substrate is kept in a hermetic container along with desired organic matter so as to produce a sample contaminated with the organic matter in the form of vapor obtained through vapor-liquid or vapor-solid equilibrium.

Abstract: A method of purifying an alkaline solution is capable of extremely efficiently nonionizing metallic impurity ions in an alkaline solution at a low cost. A method of etching semiconductor wafers in turn is capable of etching semiconductor wafers using the purified alkaline solution without deteriorating the quality of the semiconductor wafers. A reducing agent having an oxidation potential lower than a reversible electrode potential of metallic ions existing in the alkaline solution is dissolved in the alkaline solution to thereby nonionize the metallic ions existing in the alkaline solution.

Abstract: A method of manufacturing a field emission element including the steps of: depositing an emitter electrode film on the surface of an emitter portion forming recess formed on a substrate; forming an emitter portion of an emitter electrode by removing the emitter electrode film deposited on the bottom of the emitter portion forming recess; depositing a sacrificial film on the surface of the emitter electrode and on the bottom of the emitter portion forming recess, and thereafter depositing a second gate electrode film on the surface of the sacrificial film. With this manufacture method, field emission elements having small unevenness in vertical positions of emitter and gate electrodes can be formed.

Abstract: The invention relates to an aqueous phosphoric acid etch bath composition with a readily soluble silicon containing composition. The baths are used in the etching step of composite semiconductor device manufacturing.

Abstract: A process for producing multiple undercut profiles in a single material. A resist pattern is applied over a work piece and a wet etch is performed to produce an undercut in the material. This first wet etch is followed by a polymerizing dry etch which produces a polymer film in the undercut created by the first wet etch. The polymer film prevents further etching of the undercut portion during a second wet etch. Thus, an undercut profile can be obtained having a larger undercut in an underlying portion of the work piece, utilizing only a single resist application step. The work piece may be a multi-layer work piece having different layers formed of the same material, or it may be a single layer of material.

Abstract: A porous semiconductor is created by electrochemical etching. Selected regions of a semiconductor are first treated to reduce the threshold potential at which pore formation occurs, and then an electrochemical etch is carried out on the semiconductor at a potential at least equal to the reduced threshold potential for the selected regions and less than the threshold potential for untreated regions. The selective treatment preferably involves implantation with the same ions as the semiconductor, i.e. Si ions for silicon. The treatment results in the formation of highly defined etch patterns or patterns of porous material depending on the process conditions.

Abstract: After an Si wafer is anisotropically etched through an etching mask having an opening in an anisotropically etching solution, an etching face of the Si wafer emerged by the anisotropic etching is subjected to anodic oxidation by applying a positive voltage for anodic oxidation on the Si wafer. As a result, the etching face of the Si wafer is isotropically etched due to the anodic oxidation in the anisotropic etching solution. By the isotropic etching thus performed, a sharp corner formed at an end portion of a recess portion formed in the Si wafer by the anisotropic etching, is rounded. Because the isotropic etching reaction progresses very slowly in comparison with the anisotropic etching, control of the etching can be made easy and accurately. As a result, the thickness of the diaphragm can be prevented from being dispersed.

Abstract: The inventive method provides a wet cleaning of semiconductor devices on semiconductor wafers after photoresist is stripped. Semiconductor wafers are placed into a centrifuge carriage of a processing chamber. The centrifuge carriage rotates the semiconductor wafers. N-methylpyrrolidine heated to a temperature between 65° C. and 85° C. is sprayed onto the semiconductor wafers. Next N-methylpyrrolidine at room temperature is sprayed onto the semiconductor wafers. Finally, water at room temperature is sprayed onto the semiconductor wafers. The inventive method provides high throughput cleaning without undue corrosion or damage to metal layers.

Abstract: A method for fabricating a T-gate structure is provided. A structure is provided that has a silicon layer having a gate oxide layer, a polysilicon layer over the gate oxide layer and an insulating layer over the gate oxide layer. A photoresist layer is formed over the insulating layer. An opening is the formed extending through the photoresist layer and partially into the insulating layer. The opening in the insulating layer extends from a top surface of the insulating layer to a first depth. The photoresist layer is swelled to reduce the size of the opening in the photoresist layer. The opening is then extended in the insulating layer from the first depth to a second depth. The opening is wider from the top surface of the insulating layer to the first depth than the opening is from the first depth to the second depth. The opening is then filled with a conductive material to form a T-gate structure.

Abstract: A DVS-BCB polymer film is grown by heating a divinyl siloxane bisbenzocyclobutene (DVS-BCB) monomer in a vaporization controller with continuously supplying; supplying a carrier gas and maintaining a partial pressure of the DVS-BCB monomer at a state lower than a saturated vapor pressure, thereby to vaporize the monomer; transporting the carrier gas containing the DVS-BCB monomer from the vaporization controller to an evacuated reaction chamber; and spraying the gas on the heated surface of a substrate in the reaction chamber.

Abstract: A method for forming an ink jet nozzle plate includes providing a structure having a top substrate layer, a bottom substrate layer, and a buried layer disposed between the top substrate layer and the bottom substrate layer; providing a patterned bore mask having openings which extend to the top substrate layer; anisotropically etching through the openings through the top substrate layer, the buried layer, and into a portion of the bottom substrate layer; providing a bore liner into the openings formed through the top substrate layer, the buried layer, and into the etched portion of the bottom substrate layer; removing the bore mask and providing a cavity mask having openings aligned with the bore liners; anisotropically etching the top substrate layer to expose the bore liners; and removing the cavity mask and providing an ink jet nozzle plate layer over the top substrate layer and extending to be in contact with the bore liners to form bore regions in the ink jet nozzle plate layer; attaching the ink jet noz

Abstract: A process for the wet chemical treatment of semiconductor wafers, in which the semiconductor wafers are treated with treatment liquids, has the semiconductor wafers firstly treated with an aqueous HF solution, then treated with an aqueous O3 solution and finally treated with water or an aqueous HCl solution, these treatments forming a treatment sequence.

Abstract: A method of processing a semiconductor wafer sliced from a monocrystalline ingot comprises at least the steps of chamfering, lapping, etching, mirror-polishing, and cleaning. In the etching step, alkali etching is first performed and then acid etching, preferably reaction-controlled acid etching, is performed. The etching amount of the alkali etching is greater than the etching amount of the acid etching. Alternatively, in the etching step, reaction-controlled acid etching is first performed and then diffusion-controlled acid etching is performed. The etching amount of the reaction-controlled acid etching is greater than the etching amount of the diffusion-controlled acid etching.

Abstract: A process for producing multiple undercut profiles in a single material. A resist pattern is applied over a work piece and a wet etch is performed to produce an undercut in the material. This first wet etch is followed by a polymerizing dry etch which produces a polymer film in the undercut created by the first wet etch. The polymer film prevents further etching of the undercut portion during a second wet etch. Thus, an undercut profile can be obtained having a larger undercut in an underlying portion of the work piece, utilizing only a single resist application step. The work piece may be a multi-layer work piece having different layers formed of the same material, or it may be a single layer of material.