Abstract: A method for forming a capacitor on a substrate is disclosed herein. The method according to the present invention can increase the capacitance of a capacitor in one interface-etching process, the method mention above includes the following step. The first step is to form a storage node in a dielectric layer on the substrate, wherein the bottom of a cubic portion of the storage node faces the substrate is buried in the dielectric layer, and the storage node is coupled to the substrate. Next, interface-etching the dielectric layer to expose the surface including the bottom of the cubic portion of the storage node. In etching the dielectric layer made of BPSG, the buffer oxide etching (B.O.E) is utilized. Then an insulating layer is formed on the exposed surface including the bottom of the cubic portion of the storage node. Finally, a conductive layer is formed on the insulating layer. The storage node, the insulating layer, and the conductive layer constitute the capacitor.

Abstract: A two-step chemical mechanical polishing (CMP) process is provided for low dishing of metal lines in trenches in an insulation (oxide) layer, e.g., of silicon dioxide of a thickness of about 100-2000 nm, of a semiconductor wafer, e.g., of silicon, during its fabrication. The first step involves chemically mechanically polishing a metal layer, e.g., of copper of a thickness of about 200-2000 nm, disposed on the oxide layer and having a lower portion located in the trenches for forming metal lines and an upper portion overlying the lower portion. The first step polishing is effected at a high downforce, e.g., 3-8 psi, to remove at a high rate the upper portion of the metal layer substantially without removing the lower portion thereof and substantially without dishing of the lower portion located in the trenches. The second step involves continuing the CMP at a lower downforce, e.g.

Abstract: This present invention provides methods for isolating interconnects characterized by first isolating the top and bottom interconnects with an IMD consisting of a traditional low-k dielectric material, then dissolving the low-k material with a suitable solvent and using air or a noble gas instead of the traditional low-k dielectric material to isolate the interconnects.

Abstract: A method for forming shallow trench isolations includes the steps of defining a wafer substrate, forming a silicon dioxide insulating layer on the substrate, depositing a silicon nitride layer on the silicon dioxide insulating layer, and forming at least one trench in the substrate through the silicon dioxide and silicon nitride layers. The method also includes the steps of depositing a silicon dioxide layer over the silicon nitride layer and in the trench, removing the silicon dioxide layer deposited over the silicon nitride layer, anisotropically etching the silicon dioxide layer to produce silicon dioxide sidewalls in the trench contiguous with the silicon nitride layer, isotropically etching to remove the sidewalls and removing the silicon nitride layer.

Abstract: A method for cleaning polymer film residues from in-process integrated circuit devices is disclosed. Specifically, a method for forming a contact via in an integrated circuit is disclosed in which the formation of a metallization conductive element is exposed through a dry anisotropic etch. During the etch, a polymer film residue forms from masking materials, and coats the newly-formed via. The polymer film may have metals incorporated metals therein from the metallization conductive element. A fluorine based etchant is used to remove the polymer film. Protection of the metallization conductive element during the cleaning process is accomplished with passivation additives comprising straight, branched, cyclic, and aromatic hydrocarbons. Attached to the hydrocarbons are functional groups comprising at least 3 hydroxyls.

Abstract: A wafer cleaning process is disclosed for quenching etch reactions while rinsing etch reactants and etch products from the wafer. Holes are etched through an insulating layer by reactive ion etch, for example. The holes might comprise contact openings over a semiconductor substrate, or vias through insulating layers between metal lines. An organic or polymer residue left in the holes is cleaned by a wet process. The cleaning process continues to attack sidewalls of the holes, undesirably widening them. The wafer is therefore rinsed with a rinse agent below 0° C., thermally quenching further etching of the sidewalls and affording greater control over the hole dimensions. At the same time, the rinse agent allows relatively rapid diffusion of etchants and etch products from narrow and deep openings. An exemplary rinse agent for such low temperature rinsing is dilute ethylene glycol (C2H6O2).

Abstract: A microfabrication process for making enclosed, subsurface microfluidic tunnels, cavities, channels, and the like within suspended beams includes etching a single crystal silicon wafer to produce trenches defining a beam. The trench walls are oxidized, and the interior of the beam is etched through a channel via on the top of the beam to form a hollow beam with oxide sidewalls.

Abstract: A process of controlled wet etching of semiconductor wafers having a silicon dioxide layer on each of two surfaces, includes entirely removing the silicon dioxide layer from a top side and selectively removing the silicon dioxide layer from the opposite side bottom in a defined area which extends to the inside from the peripheral edge of the semiconductor wafer using an etching medium which includes hydrofluoric acid or a combination of hydrofluoric acid and ammonium fluoride and at least one carboxylic acid.

Abstract: Disclosed is a method for fabricating reliable interconnect structures on a semiconductor substrate that has at least a first dielectric layer, a first patterned metallization layer, a second dielectric layer over the first patterned metallization layer, and a plurality of tungsten plugs formed in the second dielectric layer. The method includes patterning a second metallization layer that overlies the second dielectric layer and the plurality of tungsten plugs, such that the patterning leaves at least one of the plurality of tungsten plugs not completely covered by the second metallization layer. Submersing the semiconductor substrate into a dilute nitric acid solution until a passivating tungsten oxide is formed over a portion of the at least one of the plurality of tungsten plugs that is not completely covered by the second metallization layer.

Abstract: A method of determining the carrier concentration depth profile in n-type wide bandgap semiconductor wafers is disclosed. The method includes placing a semiconductor wafer within a photoelectrochemical capacitance-voltage measurement system, in contact with a Schottky electrolyte solution. A high energy ultraviolet light is directed through the electrolyte solution to impinge upon the surface of the semiconductor wafer. The ultraviolet light has an energy greater than the energy bandgap of the semiconductor material and thus facilitates reliable etching thereof. The etch is allowed to continue until a desired depth in the sample is obtained. Upon cessation of the etch, the carrier concentration is determined. The steps of determining the carrier concentration and etching are repeated until the desired carrier concentration depth profile has been obtained.

Abstract: A method for stripping positive photoresist from a keyhole 17 in a passivation layer 18 before a heating process using NMP solvent strips after a photoresist strip. The process is summarized by the 5 steps as follows: (1) Photoresist strip 1 (e.g., EKC 830), (2) Photoresist strip 2 (e.g., EKC 830 photoresist stripper), (3) N-methly-2-pyrolidone (NMP) solvent strip-agitated (solvent is preferably the same solvent in the photoresist stripper (1 &2) (4) NMP solvent strip-agitated and (5) H.sub.2 O rinse. The NMP solvent strip steps (3) and (4) remove photoresist residue (16, FIG. 1) in the key hole 17. This prevents the formation of photoresist extrusions 24 while annealing the metal lines 14.

Abstract: A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an alignment mark area of a silicon wafer in process during the formation of integrated circuits thereon. The process comprising the steps of aligning said area of said wafer, such as an alignment mark on the wafer, to an etchant dispensing apparatus, placing the surface of the wafer adjacent at least a portion of an annular portion of the etchant dispensing apparatus, dispensing at least one etchant onto said area of said wafer, such as an alignment mark, and removing the at least one etching from the wafer.

Abstract: A method is provided for removing an bottom anti-reflective coating (BARC) from a transistor gate following at least one etch back process associated with a spacer formation and/or subsequent resistor protect etching process or processes. The method eliminates the need to use HF acid in the stripping process by substantially reducing the thickness of the BARC during each of the etching back processes, such that, only a thin layer of BARC material remains that can be easily removed with phosphoric acid.

Abstract: The present invention provides a method of planarizing a surface on a semiconductor wafer containing metal. In one embodiment, the method comprises selecting a slurry that contains conventional components of an abrasive and an oxidant. The oxidant is known to have a known rate of oxidation and is capable of oxidizing the metal. This embodiment further comprises reducing a rate of exposure of the metal to the oxidant by altering a property of the slurry, oxidizing the metal at the reduced rate to form an oxide of the metal, and removing the oxide with the abrasive to produce a planarized surface of the semiconductor wafer.

Abstract: The present invention provides a substrate treatment method to be performed after the steps of forming a desired resist pattern on a substrate and etching thereof, wherein said method comprises steps of: (I) removing the resist pattern on the substrate using a remover solution principally containing a salt derived from hydrofluoric acid and a metal-free base; (II) rinsing said substrate with a lithographic rinsing solution containing a water-soluble organic solvent and water; and (III) washing said substrate with water. According to the present invention, metallic films on the substrate are not corroded in the substrate treatment method, and the method can be performed at a low cost and with a reduced volume of labor for disposal of waste solution used for washing the substrate.

Abstract: A composition prepared from water, hydrofluoric acid (HF) and tetraalkylammonium hydroxide (TAAH, preferably tetramethylammonium hydroxide (TMAH)) or tetraalkylammonium fluoride and solvent with or without HF or TAAH is used to clean residue from a semiconductor wafer, where the residue is formed as a result of a planarization process, such as chemical mechanical polishing. Incorporation of TMAH into an aqueous HF composition retards the rate at which the composition dissolves borophosphosilicate (BPSG) without effecting the rate at which silica is dissolved. Thus, the aqueous HF/TMAH composition may be used to completely remove silica-containing residue from a BPSG surface, with a tolerable level of BPSG removal.

Abstract: The invention relates to a method for integrating semiconductor device epilayers with arbitrary host substrates, where an indium gallium arsenide etch-stop layer (34) is deposited on an indium phosphide growth substrate (32) and device epilayers (36, 38) are grown on the etch-stop layer in inverse order from their final orientation. The device epilayers are then joined to an aluminum nitride host substrate (42) by inverting the growth substrate and device epilayers. The epilayers are bonded to the host substrate using mono-molecular layer forming bonding material and the growth substrate is selectively etched away from the device epilayers. As a result of the inverse epilayer growth, the epilayers are not removed from the growth substrate prior to bonding to the host substrate, thus protecting the device epilayers and reducing processing steps. Additionally, by mono-molecular bonding, sturdy semiconductor devices are formed with low thermal impedance.

Abstract: An improved and new method for forming a planarized integrated cirsuit structure has been developed. The method uses a combination of etchback and chemical/mechanical polishing (CMP), in which the etchback process uses a tailored mask to compensate for non-unifomity of material removal by the subsequent chemical/mechanical (CMP) process, thereby resulting in improved planarization and superior thickness uniformity.

Abstract: A new method for planarization of shallow trench isolation is disclosed by using a polysilicon layer to prevent trench formed in a silicon nitride layer. The formation of the shallow trench isolation described herein includes a pad layer and a silicon nitride layer formed on a semiconductor wafer. A polysilicon layer is subsequently formed on the silicon nitride layer. A shallow trench is then created by photolithography and dry etching processes. The photoresist is subsequently removed in which an oxide layer is form in the shallow trench and on polysilicon layer for the purpose of isolation. A selective etching is used to etch the oxide layer. A CMP is performed to produce a planarized surface on a silicon wafer.

Abstract: A method for cleaning polymer film residues from in-process integrated circuit devices is disclosed. Specifically, a method for forming a contact via in an integrated circuit is disclosed in which the formation of a metallization conductive element is exposed through a dry anisotropic etch. During the etch, a polymer film residue forms from masking materials, and coats the newly-formed via. The polymer film may have metals incorporated metals therein from the metallization conductive element. A fluorine based etchant is used to remove the polymer film. Protection of the metallization conductive element during the cleaning process is accomplished with passivation additives comprising straight, branched, cyclic, and aromatic hydrocarbons. Attached to the hydrocarbons are functional groups comprising at least 3 hydroxyls.

Abstract: A method for producing a lead frame having outer leads and inner leads, for use in constructing a resin-sealed semiconductor package comprises etching processes for etching a blank. A first resist pattern having a first opening and a second resist pattern having second openings are formed on the first and the second major surfaces of a blank. The first and the second major surfaces of the blank are etched through the first and the second resist pattern by a first etching process using a first etchant to form a first recess corresponding to the first opening and second recesses corresponding to the second recesses in the first and the second major surfaces, respectively. The first recess is filled up with an etch-resistant layer. The second major surface is etched through the second resist pattern by a second etching process using a second etchant so that portions of the blank corresponding to the second openings of the second resist pattern are etched through to form the tips of the inner leads.

Abstract: A room temperature wet chemical digital etching technique for, gallium arsenide or other semiconductor material. Hydrogen peroxide and an acid are used in a two step etching cycle to remove the gallium arsenide in approximately 15 .ANG. limited increments. In the first step of the cycle, gallium arsenide is oxidized by, for example, 30% hydrogen peroxide to form an oxide layer that is diffusion limited to a thickness of, for example, 14-17 .ANG. for time periods from 15 seconds to 120 seconds. The second step of the cycle removes this oxide layer with an acid that does not attack unoxidized gallium arsenide. These steps are repeated in succession using new reactant materials and cleaning after each reactant (to prevent reactant contamination) until the desired etch depth is obtained. Experimental results are presented demonstrating the etch rate and process invariability with respect to hydrogen peroxide and acid exposure times.

Abstract: The evaluating method includes: dipping a mirror-polished silicon wafer in a dilute hydrofluoric acid; washing the surface of the silicon wafer; subjecting the surface-washed silicon wafer to a heat treatment in an oxygen atmosphere to form a thermal oxidation film; forming a predetermined number of polycrystalline silicon electrodes having a predetermined area on the thermal oxidation film; applying a voltage to each electrode between the predetermined number of polycrystalline silicon electrodes and the silicon wafer; and judging the quality of the mirror-polishing process of the silicon wafers in accordance with the breakdown electric field intensity of the leakage current obtained by measuring the oxide film insulation.

Abstract: A method of fabricating shallow trench isolation with multi-step HDP process for avoiding kinks is described. This method is to form two insulator layers with different etching rates, the etching rate of outer insulator layer being slower than that of inner insulator layer. Additionally, use of a multi-step HDP process produces better gapfilling and avoid clipping phenomenon in shallow trench isolations. This method comprises the following steps. A substrate having a mask layer thereabove is provided. A pattern is defined on the mask layer to form a trench. Then, a first insulator layer, which covers the inner wall of the trench and the top surface of the mask layer, is formed. Next, a second insulator layer is formed in the trench and over the first insulator layer, the etching rate of the first insulator layer being slower than that of the second insulator layer. The first and the second insulator layer are removed, using said mask layer as a etching stop layer.

Abstract: The present invention presents methods for, inter alia, cleaning and etching semiconductor wafers with a solution containing ammonium fluoride and control of the process used for preparing such a solution at its point of use.

Abstract: A method for removing from a patterned silicon containing dielectric layer a patterned partially fluorinated photoresist layer employed in patterning the patterned silicon containing dielectric layer. There is first formed over a semiconductor substrate a metal contact layer having a silicon containing dielectric layer formed thereover. There is then formed upon the silicon containing dielectric layer a patterned photoresist layer. There is then formed by use of a reactive ion etch (RIE) plasma etch method employing a fluorine containing etchant a via through the silicon containing dielectric layer to form a patterned silicon containing dielectric layer reaching the metal contact layer.

Abstract: A method of using diluted nitric acid and an edge bead removal tool to remove copper from the perimeter of a semiconductor wafer is provided. In one embodiment, sensitive areas of the wafer are covered with photoresist, and the wafer perimeter cleared of photoresist, before the acid is applied. In another embodiment, sensitive areas of the wafer are protected with water spray as the copper etchant is applied. In a third embodiment, the nitric acid is applied to clear the wafer perimeter of copper before a chemical mechanical polishing (CMP) is performed on the layer of deposited copper. The excess thickness of copper protects copper interconnection structures from reacting with the copper etchant. All these methods permit copper to be removed at a low enough temperature that copper oxides are not formed. A semiconductor wafer cleaned of copper in accordance with the above-described method, and a system for low temperature copper removal is also provided.

Abstract: A semiconductor wafer subject to a metallization etching process includes post-etching residue that is removed using a fluorine containing solution having a substantial amount of CO.sub.2 dissolved therein. Alternatively, or in addition, a fluorine containing solution, or the like, that has been used to remove the residue is rinsed from the wafer using a solvent containing a substantial amount of O.sub.3 dissolved therein. In each instance, pitting of the metallization layer is reduced.

Abstract: A new method of changing the surface property of a nitride film from hydrophobic to hydrophillic and thereby reducing nitride residue after photolithography is described. A pad oxide layer is provided on the surface of a semiconductor substrate. A nitride layer is deposited overlying the pad oxide layer. Thereafter, the surface of the nitride layer is cleaned wherein the surface is changed from hydrophobic to hydrophillic. The nitride layer is coated with a photoresist film which is developed to leave an opening where the field oxidation region is to be formed. The nitride layer and pad oxide layer are etched away where they are not covered by the photoresist film to expose a portion of the semiconductor substrate. The exposed portion of the semiconductor substrate is oxidized to form a field oxidation region in the fabrication of an integrated circuit.

Abstract: A method of preventing the occurrence of side etch in a wet etching method to form a circuit layer which meets the requirement of a high circuit density. First, etching is partially done using etchant having a relatively high etching rate with a spray pressure of a relatively small value, then etching is carried out using a second etchant having a relatively low etching rate with a high spray pressure. In an optional finishing step, etchant containing abrasive is used.

Abstract: The present invention discloses a method of planarizing an insulating layer of a semiconductor device. The method of the present invention comprises a first polishing step for rotating the platen and the rotating carrier holding the wafer contacted with the polishing pad secured to the platen, applying a nitrogen (N.sub.2) gas to the rear surface of the wafer to contact a surface of the wafer with the polishing pad, and applying force to the wafer through the rotating carrier to press the wafer against the polishing pad. Then, a second polishing step for increasing a speed of revolution of the platen and the rotating carrier and decreasing the force applied to the wafer is performed.

Abstract: A method of fabricating a specimen for analyzing defects of a semiconductor device is disclosed. The method includes the steps of: cutting a wafer to be adjacent to a defective portion that exists in a patterned layer formed on a substrate; molding the first specimen with a resin; grinding the substrate of the first specimen with a predetermined slope; and etching the ground face to expose the defective layer, wherein the wafer includes a semiconductor substrate and patterned layers where memory devices are formed on the semiconductor substrate.

Abstract: This is a method for improving contact openings during the manufacture of an integrated circuit. The process of forming a contact in an integrated circuit is often carried out rapidly, with imperfect control. As a result, incomplete removal of the insulating material may occur within the contact opening. In addition, the substrate material may be damaged to some extent within the contact opening by the contact formation process. In either case, high electrical resistance within the contact may result. Photo-resist may leave residue within the contact opening, low surface dopant concentrations, and insulative layer discontinuities may cause increased electrical resistance within the contact. A sequential application of two types of aqueous etchants will smooth the contact sidewall and remove a thin layer of relatively low dopant concentration at the surface of the substrate and other debris which may remain from the contact formation process and thereby allow lower resistance contacts to be formed.

Abstract: A new method for planarization of shallow trench isolation is disclosed by the wet etching and plasma etching, due to the surface sensitivity of SACVD O.sub.3 -TEOS that depends on substrate. The method described herein includes a pad oxide layer, a silicon nitride layer, and a doped polysilicon oxide layer formed on a silicon substrate. A shallow trench is formed by photolithography and dry etching process to etch the doped polysilicon oxide layer, the silicon nitride layer, the pad oxide layer, and the silicon substrate. A SACVD O.sub.3 -TEOS layer is subsequently formed on the on the doped polysilicon oxide layer and filling into the trench, the deposition rate of the ozone-TEOS layer on the doped polysilicon oxide layer is slower than the deposition rate of the ozone-TEOS layer on the silicon wafer, the wet etching rate of the ozone-TEOS layer on the doped polysilicon oxide layer is faster than the etching rate of the ozone-TEOS layer on the silicon wafer.

Abstract: Disclosed is a method for fabricating a planar buried heterostructure laser diode, comprising the steps of sequentially forming a first clad layer, an undoped active layer and a second clad layer on a substrate so as to complete a first crystal growth; forming a patterned mask layer on the second clad layer; non-selectively etching the second clad layer, the active layer, the first clad layer and the substrate using the mask layer as an etching mask; selectively etching the substrate and the first and second layers; sequentially forming a first and second current blocking layers on a structure formed by the selective etching step so as to complete a second crystal growth; sequentially forming a third clad layer and an ohmic contact layer thereon after removal of the mask layer so as to complete a third crystal growth; and forming a first electrode on a rear surface of the substrate and forming a second electrode on a surface of the third clad layer.

Abstract: A quantum bridge structure including wires of a semiconductor material such as silicon which are formed by selectively etching a superlattice of alternating layers of at least two semiconductor materials. The quantum bridge is useful as a photo emission device, a photo detector device, and a chemical sensor. The wires exhibit improved electrical conduction properties due to decreased Coulomb scattering.