By Reaction With Substrate Patents (Class 438/765)
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Patent number: 7553776Abstract: The present invention provides a method for preparing a silicon substrate and a silicon substrate having a silicon surface comprising a pattern of covalently bound monolayers. Each of the monolayers comprises an alkyne, wherein at least a portion of each monolayer is no more than about 5 molecules of the alkyne wide.Type: GrantFiled: August 4, 2006Date of Patent: June 30, 2009Assignee: Purdue Research FoundationInventors: Jillian M. Buriak, Patrick T. Hurley
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Patent number: 7547643Abstract: Adhesion of a porous low K film to an underlying barrier layer is improved by forming an intermediate layer lower in carbon content, and richer in silicon oxide, than the overlying porous low K film. This adhesion layer can be formed utilizing one of a number of techniques, alone or in combination. In one approach, the adhesion layer can be formed by introduction of a rich oxidizing gas such as O2/CO2/etc. to oxidize Si precursors immediately prior to deposition of the low K material. In another approach, thermally labile chemicals such as alpha-terpinene, cymene, and any other non-oxygen containing organics are removed prior to low K film deposition. In yet another approach, the hardware or processing parameters, such as the manner of introduction of the non-silicon containing component, may be modified to enable formation of an oxide interface prior to low K film deposition.Type: GrantFiled: January 28, 2005Date of Patent: June 16, 2009Assignee: Applied Materials, Inc.Inventors: Francimar Schmitt, Alexandros T. Demos, Derek R. Witty, Hichem M'Sadd, Sang H. Ahn, Lester A. D'Cruz, Khaled A. Elsheref, Zhenjiang Cui
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Patent number: 7541295Abstract: A method of manufacturing a semiconductor device according to one aspect of the present invention comprises: forming a gate insulation film on a semiconductor substrate in which element separation regions are formed; depositing a gate lower layer material on the semiconductor substrate via the gate insulation film; depositing a gate upper layer material, which is composed of a material different from the gate lower layer material, on the gate lower layer material; forming a gate comprising a gate upper layer and a gate lower layer by selectively processing the gate upper layer material and the gate lower layer material; increasing the size of the gate upper layer in a horizontal direction with respect to the semiconductor substrate by carrying out a chemical reaction processing treatment to which the gate upper layer has a higher reaction speed than the gate lower layer; forming an impurity implantation region by implanting ions into the semiconductor substrate using the gate upper layer as a mask; and forminType: GrantFiled: October 30, 2006Date of Patent: June 2, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Akiko Nomachi, Hideaki Harakawa
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Patent number: 7541294Abstract: To provide a semiconductor package mounting method, with excellent work efficiency, wherein the direction of a semiconductor package can be verified by a simple method before mounting. One corner of a square shaped display section provided on the surface of a semiconductor package body is chamfered such that the chamfer dimensions are different from those of the other corners. If image recognition by a camera determines that this chamfered part is located correctly, the orientation of a semiconductor package is determined to be correct. On the other hand, if image recognition determines that it is not located correctly, the orientation of the semiconductor package is adjusted until it is correct.Type: GrantFiled: November 14, 2005Date of Patent: June 2, 2009Assignee: Yamaha CorporationInventor: Kenichi Shirasaka
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Publication number: 20090130858Abstract: A process for depositing a thin film material on a substrate is disclosed, comprising simultaneously directing a series of gas flows from the output face of a delivery head of a thin film deposition system toward the surface of a substrate, and wherein the series of gas flows comprises at least a first reactive gaseous material, an inert purge gas, and a second reactive gaseous material, wherein the first reactive gaseous material is capable of reacting with a substrate surface treated with the second reactive gaseous material, wherein one or more of the gas flows provides a pressure that at least contributes to the separation of the surface of the substrate from the face of the delivery head. A system capable of carrying out such a process is also disclosed.Type: ApplicationFiled: January 8, 2007Publication date: May 21, 2009Inventor: David H. Levy
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Patent number: 7534729Abstract: Compositions and methods are provided herein that include modifications to at least one surface of a silicon-based semiconductor material. Modifications occur in a liquid and comprise alterations of surface states, passivation, cleaning and/or etching of the surface, thereby providing an improved surface to the semiconductor material. Modifications of surface states include reduction or elimination of an electrically active state of the surface, wherein, at the atomic level, the surface binding characteristics are changed. Passivation includes the termination of dangling bonds on the surface of the semiconductor material.Type: GrantFiled: August 21, 2006Date of Patent: May 19, 2009Assignee: Board of Regents, The University of Texas SystemInventors: Meng Tao, Muhammad Y. Ali
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Patent number: 7534730Abstract: Disclosed is a method for manufacturing a semiconductor device which comprises a step for carrying a plurality of substrates (1) in a process chamber (4), a step for supplying an oxygen-containing gas from the upstream side of the substrates (1) carried in the process chamber (4), a step for supplying a hydrogen-containing gas from at least one location corresponding to a position within the region where substrates (1) are placed in the process chamber (4), a step for oxidizing the substrates (1) by reacting the oxygen-containing gas with the hydrogen-containing gas in the process chamber (4), and a step for carrying the thus-processed substrates (1) out of the process chamber (4).Type: GrantFiled: August 25, 2004Date of Patent: May 19, 2009Assignee: Hitachi Kokusai Electric In.Inventors: Takashi Ozaki, Kazuhiro Yuasa, Kiyohiko Maeda
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Patent number: 7521344Abstract: A process of forming a compound film includes formulating a nano-powder material with a controlled overall composition and including particles of one solid solution The nano-powder material is deposited on a substrate to form a layer on the substrate, and the layer is reacted in at least one suitable atmosphere to form the compound film. The compound film may be used in fabrication of a radiation detector or solar cell.Type: GrantFiled: April 4, 2006Date of Patent: April 21, 2009Inventor: Bulent M. Basol
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Patent number: 7521376Abstract: A method and structure in which Ge-based semiconductor devices such as FETs and MOS capacitors can be obtained are provided. Specifically, the present invention provides a method of forming a semiconductor device including a stack including a dielectric layer and a conductive material located on and/or within a Ge-containing material (layer or wafer) in which the surface thereof is non-oxygen chalcogen rich. By providing a non-oxygen chalcogen rich interface, the formation of undesirable interfacial compounds during and after dielectric growth is suppressed and interfacial traps are reduced in density.Type: GrantFiled: October 26, 2005Date of Patent: April 21, 2009Assignee: International Business Machines CorporationInventors: Martin M. Frank, Steven J. Koester, John A. Ott, Huiling Shang
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Patent number: 7517812Abstract: A method and system for forming a nitrided germanium-containing layer by plasma processing. The method includes providing a germanium-containing substrate in a process chamber, generating a plasma from a process gas containing N2 and a noble gas, where the plasma conditions are selected effective to form plasma excited N2 species while controlling formation of plasma excited N species, and exposing the substrate to the plasma to form a nitrided germanium-containing layer on the substrate. A method is also provided that includes exposing a germanium-containing dielectric layer to liquid or gaseous H2O to alter the thickness and chemical composition of the layer.Type: GrantFiled: October 31, 2005Date of Patent: April 14, 2009Assignees: Tokyo Electron Limited, The Board of Trustees of the Leland Stanford Junior UniversityInventors: Takuya Sugawara, Paul C. McIntyre
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Publication number: 20090081883Abstract: A process of making an organic thin film on a substrate by atomic layer deposition is disclosed, the process comprising simultaneously directing a series of gas flows along substantially parallel elongated channels, and wherein the series of gas flows comprises, in order, at least a first reactive gaseous material, an inert purge gas, and a second reactive gaseous material, optionally repeated a plurality of times, wherein the first reactive gaseous material is capable of reacting with a substrate surface treated with the second reactive gaseous material wherein the first reactive gaseous material, the second reactive gaseous material or both is a volatile organic compound. The process is carried out substantially at or above atmospheric pressure and at a temperature under 250° C., during deposition of the organic thin film.Type: ApplicationFiled: September 26, 2007Publication date: March 26, 2009Inventors: Diane C. Freeman, David H. Levy, Peter J. Cowdery-Corvan
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Publication number: 20090053536Abstract: Compositions, inks and methods for forming a patterned silicon-containing film and patterned structures including such a film. The composition generally includes (a) passivated semiconductor nanoparticles and (b) first and second cyclic Group IVA compounds in which the cyclic species predominantly contains Si and/or Ge atoms. The ink generally includes the composition and a solvent in which the composition is soluble. The method generally includes the steps of (1) printing the composition or ink on a substrate to form a pattern, and (2) curing the patterned composition or ink. In an alternative embodiment, the method includes the steps of (i) curing either a semiconductor nanoparticle composition or at least one cyclic Group IVA compound to form a thin film, (ii) coating the thin film with the other, and (iii) curing the coated thin film to form a semiconducting thin film.Type: ApplicationFiled: October 29, 2008Publication date: February 26, 2009Inventors: Klaus KUNZE et al., Scott Haubrich, Fabio Zurcher, Brent Ridley, Joerg Rockenberger
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Publication number: 20090035947Abstract: The present invention provides a manufacturing method of a semiconductor device that has a rapid film formation rate and high productivity, and to provide a substrate processing apparatus.Type: ApplicationFiled: June 13, 2006Publication date: February 5, 2009Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventors: Sadayoshi Horii, Hideharu Itatani, Kazuhiro Harada
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Publication number: 20090029563Abstract: A method for producing semiconductor nanoparticles, wherein a reaction for forming nuclei of the semiconductor nanoparticles and a reaction for growing the nuclei of the semiconductor nanoparticles are performed in a stepwise manner. An apparatus for producing semiconductor nanoparticles includes a continuous reaction apparatus for performing a reaction for forming nuclei of semiconductor nanoparticles and a batch reaction apparatus for performing a reaction for growing the semiconductor nanoparticles.Type: ApplicationFiled: February 19, 2007Publication date: January 29, 2009Applicant: IDEMITSU KOSAN CO., LTD.Inventor: Satoshi Hachiya
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Publication number: 20080274624Abstract: Embodiments of the invention describe TiN deposition methods suitable for high volume manufacturing of semiconductor devices on large patterned substrates (wafers). One embodiment describes a chemical vapor deposition (CVD) process using high gas flow rate of a tetrakis(ethylmethylamino)titanium (TEMAT) precursor vapor along with an inert carrier gas at a low process chamber pressure that provides high deposition rate of conformal TiN films with good step coverage in surface reaction limited regime. Other embodiments describe cyclical TiN deposition methods using TEMAT precursor vapor and a nitrogen precursor.Type: ApplicationFiled: May 2, 2007Publication date: November 6, 2008Applicant: TOKYO ELECTRON LIMITEDInventor: Toshio Hasegawa
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Patent number: 7446052Abstract: In a process involving the formation of an insulating film on a substrate for an electronic device, the insulating film is formed on the substrate surface by carrying out two or more steps for regulating the characteristic of the insulating film involved in the process under the same operation principle. The formation of an insulating film having a high level of cleanness can be realized by carrying out treatment such as cleaning, oxidation, nitriding, and a film thickness reduction while avoiding exposure to the air. Further, carrying out various steps regarding the formation of an insulating film under the same operation principle can realize simplification of the form of an apparatus and can form an insulating film having excellent property with a high efficiency.Type: GrantFiled: March 31, 2003Date of Patent: November 4, 2008Assignee: Tokyo Electron LimitedInventors: Takuya Sugawara, Yoshihide Tada, Genji Nakamura, Shigenori Ozaki, Toshio Nakanishi, Masaru Sasakii, Seiji Matsuyama
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Patent number: 7420202Abstract: An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.Type: GrantFiled: November 8, 2005Date of Patent: September 2, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Vance H. Adams, Paul A. Grudowski, Venkat R. Kolagunta, Brian A. Winstead
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Patent number: 7413914Abstract: A process of manufacturing a semiconductor device utilizing a thermo-chemical reaction is started based on preset initial settings, a state function of an atmosphere associated with the thermo-chemical reaction is measured, a state of the atmosphere and a change thereof are analyzed based on measurement data obtained by the measurement, and then, analysis data obtained by the analysis is fed back to a manufacturing process.Type: GrantFiled: March 29, 2002Date of Patent: August 19, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Yukihiro Ushiku, Mitsutoshi Nakamura
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Publication number: 20080194115Abstract: A processing method includes a gas having a Si—CH3 bond supplied into a processing chamber after a target substrate to be processed is loaded into the processing chamber; and a silylation process performed on the target substrate. The internal pressure of the chamber by the supply of the gas having the Si—CH3 bond and the gas supply time are set to be within ranges where the silylation process can be performed while the internal pressure of the chamber is decreased to reach an eligible pressure level where the wafer can be unloaded after the internal pressure of the chamber is increased up to a preset pressure by the supply of the gas.Type: ApplicationFiled: February 4, 2008Publication date: August 14, 2008Applicant: TOKYO ELECTON LIMITEDInventors: Kazuhiro KUBOTA, Naotsugu Hoshi, Yuki Chiba, Ryuichi Asako
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Publication number: 20080166884Abstract: A process for depositing a thin film material on a substrate is disclosed, comprising simultaneously directing a series of gas flows from the output face of a delivery head of a thin film deposition system toward the surface of a substrate, and wherein the series of gas flows comprises at least a first reactive gaseous material, an inert purge gas, and a second reactive gaseous material, wherein the first reactive gaseous material is capable of reacting with a substrate surface treated with the second reactive gaseous material. A system capable of carrying out such a process is also disclosed.Type: ApplicationFiled: January 8, 2007Publication date: July 10, 2008Inventors: Shelby F. Nelson, David H. Levy, Roger S. Kerr
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Publication number: 20080132082Abstract: Embodiments of the invention contemplate the formation of a low cost solar cell using a novel electroplating apparatus and method to form a metal contact structure having metal lines formed using an electrochemical plating process. The apparatus and methods described herein remove the need to perform the often costly processing steps of performing a mask preparation and formation steps, such as screen printing, lithographic steps and inkjet printing steps, to form a contact structure. The resistance of interconnects formed in a solar cell device greatly affects the efficiency of the solar cell. It is thus desirable to form a solar cell device that has a low resistance connection that is reliable and cost effective. Therefore, one or more embodiments of the invention described herein are adapted to form a low cost and reliable interconnecting layer using an electrochemical plating process containing a common metal, such as copper.Type: ApplicationFiled: December 1, 2006Publication date: June 5, 2008Inventors: Sergey Lopatin, John O. Dukovic, David Eaglesham, Nicolay Y. Kovarsky, Robert Bachrach, John Busch, Charles Gay
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Patent number: 7378358Abstract: A substrate-processing apparatus (100, 40) comprises a radical-forming unit (26) for forming the nitrogen radicals and oxygen radicals through a high-frequency plasma, a processing vessel (21) in which a substrate (W) to be processed is held, and a gas-supplying unit (30) which is connected to the radical-forming unit. The gas-supplying unit (30) controls the mixture ratio between a first raw material gas containing the nitrogen and a second raw material gas containing oxygen, and supplies a mixture gas of a desired mixture ratio to the radical-forming unit. By supplying the nitrogen radicals and oxygen radicals mixed at the controlled mixture ratio to the surface of the substrate, an insulating film having a desired nitrogen concentration is formed on the surface of the substrate.Type: GrantFiled: September 19, 2003Date of Patent: May 27, 2008Assignee: Tokyo Electron LimitedInventors: Masanobu Igeta, Shintaro Aoyama, Hiroshi Shinriki
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Patent number: 7378319Abstract: A method of forming double gate dielectric layers composed of an underlying oxide layer and an overlying oxy-nitride layer is provided to prevent degradation of gate dielectric properties due to plasma-induced charges. In the method, the oxide layer is thermally grown on a silicon substrate under oxygen gas atmosphere to have a first thickness, and then the oxy-nitride layer is thermally grown on the oxide layer under nitrogen monoxide gas atmosphere to have a second thickness smaller than the first thickness. The substrate may have a high voltage area and a low voltage area, and the oxide layer may be partially etched in the low voltage area so as to have a reduced thickness. The oxy-nitride layer behaves like a barrier, blocking the inflow of the plasma-induced charges.Type: GrantFiled: December 29, 2005Date of Patent: May 27, 2008Assignee: Dongbu Electronics Co., Ltd.Inventor: Yong Soo Ahn
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Patent number: 7365028Abstract: The invention includes methods of forming metal oxide and/or semimetal oxide. The invention can include formation of at least one metal-and-halogen-containing material and/or at least one semimetal-and-halogen-containing material over a semiconductor substrate surface. The material can be subjected to aminolysis followed by oxidation to convert the material to metal oxide and/or semimetal oxide. The aminolysis and oxidation can be separate ALD steps relative to one another, or can be conducted in a reaction chamber in a common processing step.Type: GrantFiled: September 23, 2005Date of Patent: April 29, 2008Assignee: Micron Technology, Inc.Inventor: Eugene P. Marsh
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Patent number: 7358162Abstract: A method of manufacturing a semiconductor device, includes the steps of: raising a temperature of a sapphire substrate which is included in the semiconductor device from a room temperature to a preheat temperature of 150° C. to 450° C. and keeping the preheat temperature for a first predetermined time, thereby preheating the semiconductor device; and subsequently raising a temperature of the sapphire substrate from the preheat temperature to a thermal reaction temperature of 500° C. or higher and keeping the thermal reaction temperature for a second predetermined time, thereby performing a thermal reaction treatment of the semiconductor device.Type: GrantFiled: March 9, 2006Date of Patent: April 15, 2008Assignee: Oki Electric Industry Co., Ltd.Inventor: Makiko Kageyama
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Publication number: 20080032040Abstract: To provide a wafer support and a semiconductor substrate processing method by which dopants released from a rear surface of a semiconductor substrate can be adequately restrained from reaching a top surface of a semiconductor substrate and a reaction gas can be restrained from reaching a rear surface of the semiconductor substrate.Type: ApplicationFiled: November 9, 2004Publication date: February 7, 2008Inventors: Akira Okabe, Kazuhisa Kawamoto
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Patent number: 7312163Abstract: The invention includes methods in which at least two different precursors are flowed into a reaction chamber at different and substantially non-overlapping times relative to one another to form a material over at least a portion of a substrate, and in which at least one of the precursors is asymmetric with respect to a physical property. A field influencing the asymmetric physical property is oriented within the reaction chamber, and is utilized to affect alignment of the precursor having the asymmetric property as the material is formed. The asymmetric physical property can, for example, be an anisotropic charge distribution associated with the precursor, and in such aspect, the field utilized to influence the asymmetric physical property can be an electric field provided within the reaction chamber and/or a magnetic field provided within the reaction chamber. The methodology of the present invention can be utilized in atomic layer deposition processes.Type: GrantFiled: September 24, 2003Date of Patent: December 25, 2007Assignee: Micron Technology, Inc.Inventors: Garo J. Derderian, Gurtej S. Sandhu
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Patent number: 7309660Abstract: Methods for preparing a surface for selective silicon-germanium epitaxy by forming a thin silicon (Si) buffer layer or a thin, low concentration SiGe buffer layer for uniform nucleation, are disclosed.Type: GrantFiled: September 16, 2004Date of Patent: December 18, 2007Assignee: International Business Machines CorporationInventor: Huajie Chen
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Patent number: 7304002Abstract: A method for oxidation of an object to be processed is provided wherein an oxide film can provide favorable film quality and a laminate structure of nitride film and oxide film can be obtained by a thermal oxidation of a nitride film. In a method for oxidation of a surface of an object to be processed in a single processing container 8 which can contain a plurality of objects to be processed, at least a nitride film is exposed on said surface, and said oxidation is performed by mainly using active hydroxyl/oxygen species in a vacuum atmosphere, setting a processing pressure to 133 Pa or below, and setting a processing temperature to 400° C. or above. Under these conditions, high interplanar uniformity is maintained and oxide films with favorable film quality are obtained by oxidizing nitride films on the surfaces of a plurality of objects to be processed.Type: GrantFiled: July 7, 2003Date of Patent: December 4, 2007Assignee: Tokyo Electron LimitedInventors: Tatsuo Nishita, Tsukasa Yonekawa, Keisuke Suzuki, Toru Sato
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Patent number: 7288490Abstract: Method and system for fabricating an array of two or more carbon nanotube (CNT) structures on a coated substrate surface, the structures having substantially the same orientation with respect to a substrate surface. A single electrode, having an associated voltage source with a selected voltage, is connected to a substrate surface after the substrate is coated and before growth of the CNT structures, for a selected voltage application time interval. The CNT structures are then grown on a coated substrate surface with the desired orientation. Optionally, the electrode can be disconnected before the CNT structures are grown.Type: GrantFiled: December 7, 2004Date of Patent: October 30, 2007Assignee: United States of America as Represented by the Administrator of the National Aeronautics and Space Administration (NASA)Inventor: Lance D. Delzeit
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Patent number: 7268090Abstract: A method of manufacturing flash memory devices, comprises the steps of forming an oxide film on a semiconductor substrate, performing a pre-annealing process under N2 gas atmosphere, nitrifying the oxide film by performing a main annealing process under N2O atmosphere having the flow rate of 5 to 15 slm for 10 to 60 minutes, thus forming an oxynitride film, and performing a post-annealing process under N2 gas atmosphere.Type: GrantFiled: May 16, 2005Date of Patent: September 11, 2007Assignee: Hynix Semiconductor Inc.Inventor: Young Bok Lee
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Patent number: 7256259Abstract: The present invention is a method for a covalent ligation of one or more molecules to one or more surfaces, that is site-specific and both rapid and high yielding. The covalent ligation to the surface is based on the reaction of an azide and a phosphinothioester to form an amide bond. The method of the invention is particularly well-suited to the immobilization of peptides, proteins or protein fragments to surfaces.Type: GrantFiled: August 30, 2004Date of Patent: August 14, 2007Assignee: Wisconsin Alumni Research FoundationInventors: Ronald T. Raines, Matthew B. Soellner
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Patent number: 7250375Abstract: A method of processing a for an electronic device, comprising, at least: a nitridation step (a) of supplying nitrogen radicals on the surface of the electronic device substrate, to thereby form a nitride film on the surface thereof; and a hydrogenation step (b) of supplying hydrogen radicals to the surface of the electronic device substrate. By use of this method, it is possible to recover the degradation in the electric property of an insulating film due to a turnaround phenomenon which can occur at the time of nitriding an Si substrate, etc.Type: GrantFiled: August 2, 2002Date of Patent: July 31, 2007Assignee: Tokyo Electron LimitedInventors: Toshio Nakanishi, Takuya Sugawara, Seiji Matsuyama, Masaru Sasaki
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Patent number: 7238612Abstract: A metal salicide layer is formed by sequentially depositing a physical vapor deposition (PVD) metal layer and a chemical vapor deposition (CVD) metal layer on a semiconductor device having an exposed silicon surface so as to form a double metal layer. The semiconductor device is annealed to react the double metal layer with the silicon surface. At least a portion of the double layer that has not reacted with the silicon surface is stripped. The semiconductor device is annealed after stripping at least the portion of the double metal layer.Type: GrantFiled: January 27, 2005Date of Patent: July 3, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-ho Yun, Gil-heyun Choi, Seong-hwee Cheong, Sug-woo Jung, Hyun-su Kim, Woong-hee Sohn
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Patent number: 7238629Abstract: The present invention relates to a deposition method of a low dielectric constant insulating film, which comprises the steps of generating a first deposition gas containing at least one silicon source selecting from the group consisting of silicon containing organic compound having siloxane bond and silicon containing organic compound having CH3 group, and an oxidizing agent consisting of oxygen containing organic compound having alkoxyl group (OR: O is oxygen and R is CH3 or C2H5), and applying electric power to the first deposition gas to generate plasma and then causing reaction to form a low dielectric constant insulating film on a substrate.Type: GrantFiled: June 15, 2004Date of Patent: July 3, 2007Assignee: Semiconductor Process Laboratory Co., Ltd.Inventors: Yoshimi Shioya, Kazuo Maeda
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Patent number: 7232772Abstract: A substrate processing method comprises the step of forming an oxide film on a silicon substrate surface, and introducing nitrogen atoms into the oxide film by exposing the oxide film to nitrogen radicals excited in plasma formed by a microwave introduced via a planar antenna.Type: GrantFiled: November 16, 2004Date of Patent: June 19, 2007Assignee: Tokyo Electron LimitedInventors: Seiji Matsuyama, Takuya Sugawara, Shigenori Ozaki, Toshio Nakanishi, Masaru Sasaki
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Patent number: 7199063Abstract: A process for passivating polysilicon and a process for fabricating a polysilicon thin film transistor. A polysilicon layer is formed. Next, high-pressure annealing is performed using a fluorine-containing gas, a chlorine-containing gas, an oxygen-containing gas, a nitrogen-containing gas, or mixtures thereof to passivate the polysilicon layer.Type: GrantFiled: October 3, 2003Date of Patent: April 3, 2007Inventor: Ching-Wei Lin
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Patent number: 7176146Abstract: This invention is generally related to a method of making a molecule-surface interface comprising at least one surface comprising at least one material and at least one organic group wherein the organic group is adjoined to the surface and the method comprises contacting at least one organic group precursor with at least one surface wherein the organic group precursor is capable of reacting with the surface in a manner sufficient to adjoin the organic group and the surface.Type: GrantFiled: February 3, 2003Date of Patent: February 13, 2007Assignee: William Marsh Rice UniversityInventors: James M. Tour, Michael P. Stewart
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Patent number: 7172967Abstract: The present invention provides methods for forming cobalt silicide layers, including introducing a vaporized cobalt precursor onto a silicon substrate to form a cobalt layer. The vaporized cobalt precursor has the formula Co2(CO)6(R1—C?C—R2), wherein R1 is H or CH3, and R2 is H, t-butyl, methyl or ethyl. The silicon substrate is thermally treated so that silicon is reacted with cobalt to form a cobalt silicide layer. Methods for manufacturing semiconductor devices including the cobalt silicide layers described herein and such devices are also provided.Type: GrantFiled: August 23, 2004Date of Patent: February 6, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Su Kim, Gil-Heyun Choi, Sang-Bom Kang, Woong-Hee Sohn, Jong-Ho Yun, Kwang-Jin Moon
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Patent number: 7169713Abstract: An atomic layer deposition method for forming a microelectronic layer employs a reactor chamber pressure of greater than about 500 mtorr and more preferably from about 20 to about 50 torr. By employing a reactor chamber pressure within the foregoing range, the microelectronic layer is formed with an enhanced deposition rate while employing the atomic layer deposition method, due to a gas phase chemical vapor deposition component to the atomic layer deposition method.Type: GrantFiled: September 26, 2003Date of Patent: January 30, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Ta Wu, Kuo-Yin Lin, Chia-Shiung Tsai
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Patent number: 7160802Abstract: A process is described that forms a low resistivity connection between a tungsten layer and a silicon surface with high adherence of the tungsten to the silicon. The silicon surface is plasma-cleaned to remove native oxide. A very thin layer (one or more monolayers) of Si—NH2 is formed on the silicon surface, serving as an adhesion layer. A WNx layer is formed over the Si—NH2 layer, using an atomic layer deposition (ALD) process, to serve as a barrier layer. A thick tungsten layer is formed over the WNx layer by CVD. An additional metal layer (e.g., aluminum) may be formed over the tungsten layer.Type: GrantFiled: June 6, 2005Date of Patent: January 9, 2007Assignee: Novellus Systems, Inc.Inventors: Huong T. Nguyen, Dennis Hausmann
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Patent number: 7144746Abstract: The present invention provides a method for measuring an implantation depth of an impurity injected into a wafer by an ion implantation device, using a measurement device and monitoring whether the measured implantation depth of impurity falls within an allowable range, comprising the steps of using, as a measuring wafer, a wafer having an insulating film and an Si layer formed on the insulating film with a thickness of a 1000 ? unit or less; implanting the impurity in the measuring wafer from above the surface of the Si layer, corresponding to a main surface of the measuring wafer and heat-treating the measuring wafer; and measuring surface resistivity of the main surface of the heat-treated measuring wafer by the measurement device and detecting, as an implantation depth of the impurity from the main surface, a concentration peak depth from the main surface, which corresponds to the surface resistivity and at which a concentration of the impurity implanted in the measuring wafer reaches a peak.Type: GrantFiled: August 30, 2005Date of Patent: December 5, 2006Assignee: Oki Electric Industry Co., Ltd.Inventor: Koichi Kishiro
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Patent number: 7125811Abstract: An oxidation method for a semiconductor process, which oxidizes a surface of a target substrate, includes heating a process container that accommodates the target substrate, and supplying hydrogen gas and oxygen gas into the process container while exhausting the process container. The oxidation method also includes causing the hydrogen gas and the oxygen gas to react with each other in the process container at a process temperature and a process pressure to generate water vapor, and oxidizing the surface of the target substrate by the water vapor. The process pressure is set at 2000 Pa (15 Torr) or more.Type: GrantFiled: August 25, 2004Date of Patent: October 24, 2006Assignee: Tokyo Electron LimitedInventors: Keisuke Suzuki, Toshiyuki Ikeuchi, Kazuhide Hasebe
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Patent number: 7122484Abstract: A method for removing organic material from an opening in a low k dielectric layer and above a metal layer on a substrate is disclosed. An ozone water solution comprised of one or more additives such as hydroxylamine or an ammonium salt is applied as a spray or by immersion. A chelating agent may be added to protect the metal layer from oxidation. A diketone may be added to the ozone water solution or applied in a gas or liquid phase in a subsequent step to remove any metal oxide that forms during the ozone treatment. A supercritical fluid mixture that includes CO2 and ozone can be used to remove organic residues that are not easily stripped by one of the aforementioned liquid solutions. The removal method prevents changes in the dielectric constant and refractive index of the low k dielectric layer and cleanly removes residues which improve device performance.Type: GrantFiled: April 28, 2004Date of Patent: October 17, 2006Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Baw-Ching Perng, Yi-Chen Huang, Jun-Lung Huang, Bor-Wen Chan, Peng-Fu Hsu, Hsin-Ching Shih, Lawrance Hsu, Hun-Jan Tao
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Patent number: 7122464Abstract: A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum (silicon) nitride barrier layer, on a substrate by using a vapor deposition process with a refractory metal precursor compound, a disilazane, and an optional silicon precursor compound.Type: GrantFiled: August 30, 2004Date of Patent: October 17, 2006Assignee: Micron Technology, Inc.Inventor: Brian A. Vaartstra
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Patent number: 7105459Abstract: It is an object to provide, with a high productivity, a dielectric thin film having a high degree of pore and a very great mechanical strength, and there are included a surfactant film forming step of forming a film including a surfactant on a surface of a substrate on which a thin film is to be formed, a vapor deposition step of causing the substrate to come in contact with a gas phase containing a silica derivative to form a thin film including the silica derivative, and a step of calcining the substrate having the thin film formed thereon and decomposing and removing the surfactant, the thin film being thus formed.Type: GrantFiled: March 3, 2003Date of Patent: September 12, 2006Assignee: Rohm Co., Ltd.Inventors: Norikazu Nishiyama, Yoshiaki Oku, Shunsuke Tanaka, Korekazu Ueyama
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Patent number: 7091135Abstract: There is disclosed a method of manufacturing a semiconductor device, which comprises forming a film containing metal elements and silicon elements on a semiconductor substrate, exposing the semiconductor substrate to an atmosphere containing an oxidant to form a silicon dioxide film at the interface between the semiconductor substrate and the film containing metal elements and silicon elements, and nitriding the film containing metal elements and silicon elements after forming the silicon dioxide film.Type: GrantFiled: March 12, 2004Date of Patent: August 15, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Seiji Inumiya, Kazuhiro Eguchi
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Patent number: 7091136Abstract: A process of forming a compound film includes formulating a nano-powder material with a controlled overall composition and including particles of one solid solution. The nano-powder material is deposited on a substrate to form a layer on the substrate, and the layer is reacted in at least one suitable atmosphere to form the compound film. The compound film may be used in fabrication of a radiation detector or solar cell.Type: GrantFiled: April 11, 2002Date of Patent: August 15, 2006Inventor: Bulent M. Basol
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Patent number: 7084075Abstract: The invention relates to a method for the production of structures in the nanometer range from larger, existing structures. An elastic strain field in generated in an already structured layer and optionally in a substrate. A strain-dependent diffusion and reaction process subsequently takes place, wherein the existing structure can be reduced in a reproducible manner by means of material transport.Type: GrantFiled: November 16, 2002Date of Patent: August 1, 2006Assignee: Forschungszentrum Julich GmbHInventors: Patrick Kluth, Quing-Tai Zhao, Siegfried Mantl
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Patent number: 7071127Abstract: A method and apparatus are disclosed for reducing the concentration of chlorine and/or other bound contaminants within a semiconductor oxide composition that is formed by chemical vapor deposition (CVD) using a semiconductor-element-providing reactant such as dichlorosilane (DCS) and an oxygen-providing reactant such as N2O. In one embodiment, a DCS-HTO film is annealed by heating N2O gas to a temperature in the range of about 825° C. to about 950° C. so as to trigger exothermic decomposition of the N2O gas and flowing the heated gas across the DCS-HTO film so that disassociated atomic oxygen radicals within the heated N2O gas can transfer disassociating energy to chlorine atoms bound within the DCS-HTO film and so that the atomic oxygen radicals can fill oxygen vacancies within the semiconductor-oxide matrix of DCS-HTO film. An improved ONO structure may be formed with the annealed DCS-HTO film for use in floating gate or other memory applications.Type: GrantFiled: May 20, 2003Date of Patent: July 4, 2006Assignee: ProMOS Technologies, Inc.Inventors: Zhong Dong, Chuck Jang, Chia-Shun Hsiao