By Reaction With Substrate Patents (Class 438/765)
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Patent number: 6670286Abstract: A photopolymerization method is disclosed for attaching a chemical microsensor film to an oxide surface including the steps of pretreating the oxide surface to form a functionalized surface, coating the functionalized surface with a prepolymer solution, and polymerizing the prepolymer solution with ultraviolet light to form the chemical microsensor film. The method also allows the formation of molecular imprinted films by photopolymerization. Formation of multilayer sensing films and patterned films is allowed by the use of photomasking techniques to allow patterning of multiple regions of a selected sensing film, or creating a sensor surface containing several films designed to detect different compounds.Type: GrantFiled: February 13, 2002Date of Patent: December 30, 2003Assignee: The Regents of the University of CaliforniaInventors: Xiaoguang Yang, Basil I. Swanson, Xian-Xian Du
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Patent number: 6670248Abstract: A method for forming, on a semiconductor substrate, a dielectric layer having a variable thickness and composition. The dielectric layer so formed can be used to form electronic devices such as MOSFETS and CMOSFETS that require gate dielectrics of different thicknesses. On a silicon substrate in accord with the preferred embodiment, the method requires the formation of three regions, two with SiO2 layers of different thicknesses and a third region of substrate with no oxide. A final thin layer of high-k dielectric is formed covering the three regions, so that the region with no oxide has the thinnest dielectric layer of only high-k material and the other two regions have the high-k dielectric over SiO2 layers of different thickness. A final layer of gate electrode material can be formed and patterned to form the required device structure.Type: GrantFiled: August 7, 2002Date of Patent: December 30, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Chew Hoe Ang, Wenhe Lin, Jia Zhen Zheng
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Patent number: 6649495Abstract: The present invention relates to a manufacturing method of a semiconductor device in which a barrier insulating film and a main insulating film having low relative dielectric constant are sequentially formed while a wiring mainly consisting of copper film is coated.Type: GrantFiled: June 10, 2002Date of Patent: November 18, 2003Assignees: Canon Sales Co., Inc., Semiconductor Process Laboratory Co., Ltd.Inventors: Yoshimi Shioya, Yuhko Nishimoto, Tomomi Suzuki, Hiroshi Ikakura, Kazuo Maeda
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Publication number: 20030181062Abstract: There is provided a method for improving film quality of an insulating film, which includes the steps of forming a silicon oxide film on a substrate, and heating the silicon oxide film by contacting an exposed surface of the silicon oxide film with a steam-containing atmosphere after the silicon oxide film is formed.Type: ApplicationFiled: January 2, 2003Publication date: September 25, 2003Inventors: Setsu Suzuki, Kazuo Maeda
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Patent number: 6620745Abstract: A method is provided for forming a blocking layer in a multilayer semiconductor device for blocking diffusion of a chemical species including the steps of providing an insulating layer including a target surface for forming a metal nitride layer thereon said insulating layer forming a portion of a multilayer semiconductor device; treating the target surface with an RF generated plasma to cause a density increase over a thickness adjacent to and including a target surface sufficient to reduce a diffusion rate of chemical species therethrough; forming at least one metal nitride layer over the target surface; and, carrying out a photolithographic process wherein the surface of the at least one metal nitride layer is patterned for etching.Type: GrantFiled: October 19, 2001Date of Patent: September 16, 2003Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Syan-Mang Jang, Tien-I Bao, Lain-Jong Li, Shwang-Ming Jeng
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Publication number: 20030143863Abstract: A process for forming an oxide layer includes forming a first oxide portion over a substrate at a temperature below a threshold temperature. A second oxide portion is formed under the first oxide portion at a temperature above the threshold temperature. The substrate is illustratively oxidizable silicon and the threshold temperature is the viscoelastic temperature of silicon dioxide.Type: ApplicationFiled: February 7, 2003Publication date: July 31, 2003Applicant: Agere Systems Inc.Inventors: Yuanning Chen, Sundar Srinivasan Chetlur, Pradip Kumar Roy
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Patent number: 6589887Abstract: The present invention pertains to methods for forming metal-derived layers on substrates. Preferred methods apply to integrated circuit fabrication. In particular, selective methods may be used to form diffusion barriers on partially fabricated integrated circuits. In one preferred method, a wafer is heated and exposed to a metal vapor. Under specific conditions, the metal vapor reacts with dielectric surfaces to form a diffusion barrier, but does not react with metal surfaces. Thus, methods of the invention form diffusion barriers that selectively protect dielectric surfaces but leave metal surfaces free of diffusion barrier.Type: GrantFiled: October 11, 2001Date of Patent: July 8, 2003Assignee: Novellus Systems, Inc.Inventors: Jeremie Dalton, Ronald A. Powell, Sridhar K. Kailasam, Sasangan Ramanathan
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Publication number: 20030124872Abstract: A method for fabricating gate electrodes and gate interconnects with a protective silicon oxide or silicon nitride cap and spacer formed by high density plasma chemical vapor deposition (HDPCVD). Silicon oxide or silicon nitride is deposited in a reaction zone of a HDPCVD reactor while providing two or more selected substrate bias powers, source powers and/or selected gas mixtures to tailor the shape and thickness of the film for desired applications. In one embodiment, a low bias power of below 500 Watts is provided in a first stage HDPCVD and the bias power is then increased to between 500 and 3000 Watts for a second stage to produce a protective film having thin sidewall spacers for enhanced semiconductor device density and a relatively thick cap.Type: ApplicationFiled: December 16, 2002Publication date: July 3, 2003Inventors: Weimin Li, Sujit Sharan, Gurtej Sandhu
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Patent number: 6583468Abstract: An AlN film as an underlayer is epitaxially grown on a substrate having a dislocation density of 1011/cm2 or below and a crystallinity of 90 seconds or below in full width at half maximum (FWHM) of an X-ray rocking curve at (002) reflection. Then, on the AlN film an n-GaN film is epitaxially grown as a conductive layer having a dislocation density of 1010/cm2 or below and a crystallinity of 150 seconds or below in full width at half maximum (FWHM) of an X-ray rocking curve at (002) reflection, to fabricate a semiconductor element.Type: GrantFiled: December 4, 2001Date of Patent: June 24, 2003Assignee: NGK Insulators, Ltd.Inventors: Yuji Hori, Tomohiko Shibata, Osamu Oda, Mitsuhiro Tanaka
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Patent number: 6576980Abstract: A method of surface treating a surface and semiconductor article is disclosed. A deposited surface layer on a substrate, such as a semiconductor surface, is treated and annealed within an alkyl environment of a chemical vapor deposition chamber to passivate the surface layer by bonding with the silicon and attaching alkyl terminating chemical species on the surface of the surface layer to aid in dehydroxylating the surface. The surface layer comprises a silicon-oxy-carbide surface layer having a carbon content ranging from about 5% to about 20% at the molecular level and a dielectric constant of about 2.5 to about 3.0.Type: GrantFiled: November 30, 1999Date of Patent: June 10, 2003Assignee: Agere Systems, Inc.Inventors: Huili Shao, Kurt G. Steiner, Susan C. Vitkavage
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Patent number: 6562730Abstract: A barrier layer comprising silicon mixed with an impurity is disclosed for protection of gate dielectrics in integrated transistors. In particular, the barrier layer comprises silicon incorporating nitrogen. The nitrogen can be incorporated into an upper portion of the gate polysilicon during deposition, or a silicon layer doped with nitrogen after silicon deposition. The layer is of particular utility in conjunction with CVD tungsten silicide straps.Type: GrantFiled: June 28, 2001Date of Patent: May 13, 2003Assignee: Micron Technology, Inc.Inventor: Nanseng Jeng
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Patent number: 6559071Abstract: A process for forming a nanoporous silica dielectric coating on a substrate. A substrate containing a deposited film is suspended within a sealable hotplate, while remaining free of contact with the hotplate. The hotplate is sealed and an inert gas is flowed across the substrate. The hotplate is heated to a temperature of from about 350° C. or higher, and the substrate is forced to contact the heated hotplate. The substrate is heated for a time that sufficiently removes outgassing remnants from the resultant nanoporous dielectric coating.Type: GrantFiled: October 26, 2001Date of Patent: May 6, 2003Assignee: AlliedSignal Inc.Inventors: Teresa Ramos, Douglas M. Smith, James Drage, Rick Roberts
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Patent number: 6555483Abstract: A gate insulation film includes nitrogen, oxygen and silicon as constituent elements thereof. The nitrogen concentration profile of the gate insulation film in the thickness direction has a maximum concentration in the vicinity of the top surface of the gate insulation film and substantially zero concentration in the vicinity of the silicon substrate. The specified nitrogen profile is obtained by a steep rising slope and a relatively steep falling slope of the temperature profile with time in the step of nitriding a silicon oxide film to form a silicon oxynitride film.Type: GrantFiled: November 6, 2001Date of Patent: April 29, 2003Assignee: NEC CorporationInventor: Eiji Hasegawa
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Patent number: 6555487Abstract: A method for conditioning or repairing a dielectric structure of a semiconductor device structure with selectivity over an adjacent conductive or semiconductive structure of the semiconductor device structure, such as a capacitor dielectric and an adjacent bottom electrode of the capacitor. The method includes exposing the dielectric structure and at least an adjacent surface of the conductive or semiconductive structure to an oxidizing atmosphere that includes at least one oxidant and hydrogen species. The at least one hydrogen species adsorbs to a surface of the conductive or semiconductive structure so as to substantially prevent passage of the at least one oxidant into or through the conductive or semiconductive structure. The oxidant oxidizes or repairs voids or other defects that may be present in the dielectric structure. Semiconductor device structures fabricated by employing the method are also disclosed.Type: GrantFiled: August 31, 2000Date of Patent: April 29, 2003Assignee: Micron Technology, Inc.Inventors: Ronald A. Weimer, Don Carl Powell
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Patent number: 6552388Abstract: A field effect semiconductor device comprising a high permittivity hafnium (or hafnium-zirconium) nitride gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A hafnium (or hafnium-zirconium) nitride gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Hafnium (or hafnium-zirconium) nitride gate dielectric layer 36 has a dielectric constant is significantly higher than the dielectric constant of silicon dioxide.Type: GrantFiled: June 14, 2002Date of Patent: April 22, 2003Assignee: Texas Instruments IncorporatedInventors: Glen D. Wilk, Robert M. Wallace
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Patent number: 6551893Abstract: A capacitor structure is formed over a semiconductor substrate by atomic layer deposition to achieve uniform thickness in memory cell dielectric layers, particularly where the dielectric layer is formed in a container-type capacitor structure. In accordance with several embodiments of the present invention, a process for forming a capacitor structure over a semiconductor substrate is provided. Other embodiments of the present invention relate to processes for forming memory cell capacitor structures, memory cells, and memory cell arrays. Capacitor structures, memory cells, and memory cell arrays are also provided.Type: GrantFiled: November 27, 2001Date of Patent: April 22, 2003Assignee: Micron Technology, Inc.Inventors: Lingyi A. Zheng, Er-Xuan Ping, Lyle Breiner, Trung T. Doan
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Patent number: 6544899Abstract: There is provided a process for manufacturing a silicon epitaxial wafer capable of manufacturing an epitaxial wafer, which exerts a stable IG capability without being affected by a thermal history of a substrate for epitaxial growth and has the IG capability excellent from an early stage of a device process, and particularly, canceling an IG shortage in an N/N+ epitaxial wafer caused by a problem that oxygen precipitation is hard to proceed in an N+ substrate with a simple and easy way. RTA (rapid heating and rapid cooling heat treatment) is performed at a temperature of 1200° C. to 1350° C. for 1 to 120 seconds on a silicon substrate for epitaxial growth; further heat treatment is performed at a temperature of 900° C. to 1050° C. for 2 to 20 hours on the silicon substrate for epitaxial growth; and thereafter, an epitaxial layer is formed on a surface of the silicon substrate.Type: GrantFiled: January 4, 2002Date of Patent: April 8, 2003Assignee: Shin-Etsu Handotai Co.Inventors: Hiroshi Takeno, Norihiro Kobayashi
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Patent number: 6544907Abstract: The present invention provides a method for manufacturing a high quality oxide layer having a uniform thickness. The method includes providing a semiconductor substrate, and forming an oxide layer having a substantially uniform thickness on the semiconductor substrate, and in a zone of pressure of less than about 4 Torr or greater than about 25 Torr.Type: GrantFiled: October 12, 2000Date of Patent: April 8, 2003Assignee: Agere Systems Inc.Inventors: Yi Ma, Edith Yang
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Publication number: 20030054663Abstract: Systems and methods are described for synthesis of films, coatings or layers using templates. A method includes locating a template within at least one of a first precursor layer that is coupled to a first substrate and a second precursor layer that is coupled to a second substrate; forming a composition layer; and moving the first substrate relative to the second substrate, wherein the composition layer remains coupled to the second substrate.Type: ApplicationFiled: September 20, 2001Publication date: March 20, 2003Inventor: Billy J. Stanbery
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Patent number: 6531411Abstract: A method of improving surface morphology of a semiconductor substrate when using an SOI technique comprises providing a silicon ingot positioned on a support member, orientating the silicon ingot in relation to the support member, and a cutting device, and cutting the silicon ingot along about a (100) crystal plane of the silicon ingot, preferably using a wire saw. This then provides a silicon substrate having an initial surface defining a miscut angle which is less than about 0.15 degrees from the (100) crystal plane. The method then comprises processing the silicon substrate using SIMOX processing, which includes implanting oxygen atoms in the silicon substrate to form a buried oxide layer and annealing the silicon substrate to provide a final substrate surface. Finally, the method includes accepting the final substrate surface for further processing when the final substrate surface measures between 2-20 Å RMS using an atomic force microscopy technique.Type: GrantFiled: November 5, 2001Date of Patent: March 11, 2003Assignee: International Business Machines CorporationInventors: Anthony G. Domenicucci, Neena Garg, Kenneth J. Giewont, Richard J. Murphy, Gerd Pfeiffer, Gregory D. Pomarico, Frank J. Schmidt, Jr., Terrance M. Tornatore
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Publication number: 20030017714Abstract: A substrate processing apparatus and a method for manufacturing a semiconductor device can supply the vapor of the raw material to the substrate without fail.Type: ApplicationFiled: July 9, 2002Publication date: January 23, 2003Applicant: Hitachi Kokusai Electric Inc.Inventors: Tomoshi Taniyama, Kouji Tometsuka, Shusaku Yanagawa
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Patent number: 6509283Abstract: Atomic oxygen, or a mixture of atomic oxygen and atomic nitrogen, is utilized in thermally oxidizing silicon to form a layer of silicon dioxide, or nitrogen-doped silicon dioxide, on a surface of the silicon. Use of atomic oxygen (or O−+N−) provides a better stoichiometric silicon dioxide structure with fewer dangling bonds than results from standard oxidation processes. The atomic oxygen (or O−+N−) may be generated within the oxidation furnace, for example by passing the gas through a heated ceramic material (e.g., Al2O3) or by using internal UV radiation of the oxygen gas. Alternatively, the atomic oxygen (or O−+N−) may be generated at a remote source, for example in a plasma reactor, and then introduced to the oxidation furnace. Atomic chlorine can be generated and used prior to the oxidation step for pre-cleaning the silicon surface.Type: GrantFiled: May 13, 1998Date of Patent: January 21, 2003Assignee: National Semiconductor CorporationInventor: Michael E. Thomas
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Patent number: 6506678Abstract: An aluminum layer formed over an integrated circuit structure is patterned to form a plurality of aluminum metal lines. The patterned aluminum metal lines are then anodized in an acid anodizing bath to form anodized aluminum oxide on the exposed sidewall surfaces of the patterned aluminum. The anodization may be carried out until the anodized aluminum films on horizontally adjacent aluminum metal lines contact one another, or may be stopped prior to this point, leaving a gap between the anodized aluminum oxide films on adjacent aluminum metal lines. This gap may then be either filled with other low k dielectric material or by standard (non-low k) dielectric material. A capping layer of non-porous dielectric material is then formed over the porous anodized aluminum oxide.Type: GrantFiled: May 19, 2000Date of Patent: January 14, 2003Assignee: LSI Logic CorporationInventor: Valeriy Sukharev
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Publication number: 20020197806Abstract: Methods are provided that use disposable and permanent films to dope underlying layers through diffusion. Additionally, methods are provided that use disposable films during implantation doping and that provide a surface from which to dope underlying materials. Some of these disposable films can be created from a traditionally non-disposable film and made disposable. In this manner, solvents may be used that do not etch underlying layers of silicon-based materials. Preferably, deep implantation is performed to form source/drain regions, then an anneal step is performed to activate the dopants. A conformal layer is deposited and implanted with dopants. One or more anneal steps are performed to create very shallow extensions in the source/drain regions.Type: ApplicationFiled: August 16, 2002Publication date: December 26, 2002Inventors: Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, William H-L Ma, Patricia M. Marmillion, Donald W. Rakowski
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Patent number: 6498111Abstract: A method for protecting the surface of a semiconductor material from damage and dopant passivation is described. A barrier layer of dense or reactive material is deposited on the semiconductor material shortly after growth in a growth reactor such as a MOCVD reactor, using the MOCVD source gasses. The barrier layer blocks the diffusion of hydrogen into the material. The reactor can then be cooled in a reactive or non-reactive gas ambience. The semiconductor material can then be removed from the reactor with little or no passivation of the dopant species. The barrier layer can be removed using a variety of etching processes, including wet chemical etching or can be left at the semiconductor material for surface protection. The barrier layer can also be a gettering layer that chemically binds hydrogen trapped in the semiconductor material and/or blocks hydrogen diffusion into the material.Type: GrantFiled: August 23, 2000Date of Patent: December 24, 2002Assignee: Cree Lighting CompanyInventors: David Kapolnek, Brian Thibeault
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Publication number: 20020177329Abstract: A method of densifying a superficial layer on a low dielectric constant film. A substrate is provided. A low dielectric constant material layer is formed over the substrate. An inert gas plasma treatment of the low dielectric constant material layer is conducted so that a superficial layer of the low dielectric constant material layer is densified into a protective layer. The protective layer protects the low dielectric constant material layer against attacks by plasma and chemicals during subsequent processes and prevents any deterioration of electrical properties.Type: ApplicationFiled: April 9, 2001Publication date: November 28, 2002Inventors: Neng-Hui Yang, Ming-Sheng Yang
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Patent number: 6486078Abstract: One aspect of the present invention relates to a method of forming a low k material layer on a semiconductor substrate, involving the steps of depositing a mixture containing a low k material and a casting solvent on the semiconductor substrate; optionally contacting the mixture with a transition solvent whereby the casting solvent is removed from the mixture to form a second mixture containing the low k material and the transition solvent; contacting the second mixture with a supercritical fluid whereby the transition solvent is removed from the second mixture; and permitting the supercritical fluid to evaporate thereby forming the low k material layer.Type: GrantFiled: August 22, 2000Date of Patent: November 26, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Bharath Rangarajan, Ramkumar Subramanian, Bhanwar Singh
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Patent number: 6486080Abstract: A new method of forming a metal oxide high dielectric constant layer in the manufacture of an integrated circuit device has been achieved. A substrate is provided. A metal oxide layer is deposited overlying the substrate by reacting a precursor with an oxidant gas in a chemical vapor deposition chamber. The metal oxide layer may comprise hafnium oxide or zirconium oxide. The precursor may comprise metal alkoxide, metal alkoxide containing halogen, metal &bgr;-diketonate, metal fluorinated &bgr;-diketonate, metal oxoacid, metal acetate, or metal alkene. The metal oxide layer is annealed to cause densification and to complete the formation of the metal oxide dielectric layer in the manufacture of the integrated circuit device. A composite metal oxide-silicon oxide (MO2-SiO2) high dielectric constant layer may be deposited using a precursor comprising metal tetrasiloxane.Type: GrantFiled: November 30, 2000Date of Patent: November 26, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Simon Chooi, Wenhe Lin, Mei Sheng Zhou
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Publication number: 20020168847Abstract: A method of providing a stable interface between a metallic layer and a dielectric layer in a semiconductor device is provided. The method includes generating a remote nitrogen containing plasma and flowing activated nitrogen species, from the remote site to the location of the metallic layer. The activated nitrogen species are flowed over at least the surface of the metallic layer, where they react with the metallic surface to form a metal nitride. The treated layer can be used to provide a stable bottom electrode in a capacitor stack formation.Type: ApplicationFiled: May 9, 2001Publication date: November 14, 2002Applicant: Applied Materials, Inc.Inventors: Pravin Narwankar, Ravi Rajagopalan, Turgut Sahin
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Patent number: 6475926Abstract: A silicon substrate material based on silicon has a semi-insulating interior layer isolating the bulk of the substrate material from the top layers, where integrated circuits are to be built. The semi-insulating layer is created by producing submicron particles having Schotty barriers or pn-hereto-barriers and distributing X particles so that the depletion regions then produced around neighbouring particles overlap. Such particles will then deplete the silicon material from electric charge carriers. The substrate material can then be processed using the standard silicon processing methods and allows integrated circuits to be manufactured which are suitable for high frequency applications. A silicon substrate is made by sputtering a metal such as Co in a silicon wafer and then silicidizing the sputtered Co atoms by means of an annealing treatment. A top silicon wafer having a silicon dioxide layer at its bottom surface is then bonded to the sputted layer.Type: GrantFiled: December 13, 2000Date of Patent: November 5, 2002Assignee: Telefonaktiebolaget LM EricssonInventors: Andrej Litwin, Anders Söderbärg
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Patent number: 6461980Abstract: A process for controlling the temperature of a substrate in a plasma processing reactor chamber comprising flowing a cooling gas to a substrate at a flow pressure; and determining a temperature of the substrate. The difference between the temperature of the substrate and a desired temperature of the substrate is determined; and a pressure by which the flow pressure of the cooling gas is to be adjusted is determined. The flow pressure of the cooling gas to the substrate is adjusted in accordance with the determined pressure.Type: GrantFiled: January 28, 2000Date of Patent: October 8, 2002Assignee: Applied Materials, Inc.Inventors: Jeff S. Cheung, Alexandros T. Demos
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Patent number: 6461984Abstract: The present invention provides a highly reliable polycrystal silicon thin film transistor with N2O plasma oxide having an excellent leakage current characteristics comparable to the thermal oxide film formed on the crystalline silicon. Also, the present invention provides a method of fabricating EEPROM or flash memory using N2O plasma oxide as a tunnel oxide, and N2O plasma oxide film as an interpoly dielectric between the floating gate and the control gate.Type: GrantFiled: March 24, 2000Date of Patent: October 8, 2002Assignee: Korea Advanced Institute of Science & TechnologyInventors: Chui-Hi Han, Nae-In Lee, Sung-Hoi Hur, Jin-Woo Lee
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Publication number: 20020142493Abstract: A system and method are disclosed for providing in-situ monitoring of thin film thickness, such as by employing a non-destructive optical measurement technique. The monitored film thickness may be employed to help achieve a desired feature film thickness and uniformity across a surface of a substrate. By monitoring film thickness during semiconductor processing, for example, one or more process control parameters may be adjusted to help achieve a desired film thickness and/or uniformity thereof.Type: ApplicationFiled: April 2, 2001Publication date: October 3, 2002Inventors: Arvind Halliyal, Khoi A. Phan, Bhanwar Singh
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Publication number: 20020142621Abstract: A vapor-phase coating method forms a uniform and nanometer thick silanes on a silicon surface at ambient pressure using nitrogen as a carrier gas. A cleaned silicon wafer is placed in a chamber and flushed with dry nitrogen. As dry nitrogen is flushing through the chamber, a silanizing reagent such as alkyltrichlorosilane or alkyltrimethoxysilane is injected into the chamber and the nitrogen flushing is continued until the silanizing agent is depleted. The nitrogen gas serves as both a protecting medium and a diluent. The moisture free atmosphere yields a surface that is extremely smooth and without any detectable aggregates. The coatings and subsequent treatments are characterized with ellipsometry, scanning electron microscopy, contact angles, sum frequency generation (SFG) spectroscopy, and zeta potential in water.Type: ApplicationFiled: January 16, 1998Publication date: October 3, 2002Inventor: YUCHUNG WANG
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Patent number: 6451660Abstract: A bipolar device (10) includes an oxide layer (24) which is grown on the surface (16) of a semiconductor substrate (12) by immersing the surface in ozonated deionized water. By selecting an appropriate temperature of the water and concentration of the ozone, the thickness of the film can be maintained within fine tolerances from lot to lot, and over the surface of a wafer (W) comprising the substrate.Type: GrantFiled: June 9, 2000Date of Patent: September 17, 2002Assignee: Agere Systems Guardian Corp.Inventors: Yi Ma, Yih-Feng Chyan, Chung Wai Leung, Jane Qian Liu, Timothy Scott Campbell
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Publication number: 20020127829Abstract: A holder holding a wafer descends and the wafer comes in contact with a plating solution. In this state, the wafer is heated by a resistance heating element disposed in the holder so that the temperature of the wafer becomes gradually higher from its outer circumference to its center part. Then, voltage is applied between an anode electrode and the wafer to apply the plating on a face to be plated of the wafer.Type: ApplicationFiled: March 4, 2002Publication date: September 12, 2002Inventor: Yoshinori Marumo
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Patent number: 6448192Abstract: Highe quality silicon oxide having a plurality of monolayers is grown at a high temperature on a silicon substrate. A monolayer of silicon oxide is a single layer of silicon atoms and two oxygen atoms per silicon atom bonded thereto. The silicon oxide is etched one monolayer at a time until a desired thickness of the silicon layer is obtained. Each monolayer is removed by introducing a first gas to form a reaction layer on the silicon oxide. The gas is then purged. Then the reaction layer is activated by either another gas or heat. The reaction layer then acts to remove a single monolayer. This process is repeated until a desired amount of silicon oxide layer remains. Because this removal process is limited to removing one monolayer at a time, the removal of silicon oxide is well controlled. This allows for a precise amount of silicon oxide to remain.Type: GrantFiled: April 16, 2001Date of Patent: September 10, 2002Assignee: Motorola, Inc.Inventor: Vidya S. Kaushik
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Patent number: 6448180Abstract: For depositing semiconductor films on a plurality of sets of semiconductor wafers, a first set of semiconductor wafers carried by a wafer boat are placed within a reaction chamber. An in-situ doped amorphous semiconductor film is deposited on the first set of semiconductor wafers while the first set of semiconductor wafers carried by the wafer boat are within the reaction chamber. The first set of semiconductor wafers carried by the wafer boat are removed from the reaction chamber, and the first set of semiconductor wafers are removed from the wafer boat. The wafer boat that is empty of any semiconductor wafers is placed back within the reaction chamber. A first undoped semiconductor film having a thickness in a range of from about 8,000 Å (angstroms) to about 12,000 Å (angstroms) is deposited on the wafer boat and on components of the reaction chamber. The wafer boat is then removed from the reaction chamber, and a second set of semiconductor wafers are loaded within the wafer boat.Type: GrantFiled: February 5, 2001Date of Patent: September 10, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Balaraman Mani, Bill Chen
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Publication number: 20020115303Abstract: A semiconductor device has a strongly bonding structure for improving bond strength between the semiconductor and the insulating layer even if the insulating layer is formed by a traditional method which causes slight damage to the semiconductor. The strongly bonding structure includes an oxide layer 12 (containing a constituent element of the semiconductor), an oxide bonding layer, a bond-creating layer (which may disappear from the finished product), and an insulating layer, which are sequentially formed one over the other. The oxide layer may be either one which occurs naturally or one which is formed artificially. The oxide bonding layer is formed by reaction between oxygen in the oxide layer and a constituent element in the bond-creating layer. The bond-creating layer contains an element that oxidizes and an element that reacts with a constituent element of the insulating layer.Type: ApplicationFiled: December 13, 2001Publication date: August 22, 2002Applicant: Hitachi, Ltd.Inventors: Hiroshi Ohta, Shinichiro Takatani, Toshimi Yokoyama, Takeshi Kikawa
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Patent number: 6436745Abstract: In a method of producing a semiconductor device, an a-Si film is crystallized using nickel to form a CGS film. Then, an a-Si film containing phosphorus is directly formed on the whole surface of the CGS film, and then the CGS film and the a-Si film are subjected to heat treatment to thereby getter the nickel from the CGS film the a-Si film. The a-Si film containing nickel and phosphorus is removed. Then, using the thus obtained CGS film for an active region, a thin-film transistor is formed.Type: GrantFiled: October 31, 2000Date of Patent: August 20, 2002Assignee: Sharp Kabushiki KaishaInventors: Masahito Gotou, Yasumori Fukushima
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Patent number: 6436801Abstract: A field effect semiconductor device comprising a high permittivity hafnium (or hafnium-zirconium) nitride gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A hafnium (or hafnium-zirconium) nitride gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Hafnium (or hafnium-zirconium) nitride gate dielectric layer 36 has a dielectric constant is significantly higher than the dielectric constant of silicon dioxide.Type: GrantFiled: February 17, 2000Date of Patent: August 20, 2002Assignee: Texas Instruments IncorporatedInventors: Glen D. Wilk, Robert M. Wallace
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Patent number: 6429117Abstract: A method of preventing metal penetration and diffusion from metal structures formed over a semiconductor structure, comprising the following steps. A semiconductor structure including a patterned dielectric layer is provided. The patterned dielectric layer includes an opening and an upper surface. The dielectric layer surface is then passivated to form a passivation layer. A metal plug is formed within the dielectric layer opening. The passivation layer prevents penetration and diffusion of metal out from the metal plug into the semiconductor structure and the patterned dielectric layer.Type: GrantFiled: July 19, 2000Date of Patent: August 6, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: John Sudijono, Yakub Aliyu, Mei Sheng Zhou, Simon Chooi, Subhash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu
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Publication number: 20020102861Abstract: The present invention provides a method for creating microscopic high resistivity structures on a target by directing a focused ion beam toward an impact point on the target and directing a precursor gas toward the impact point, the ion beam causing the precursor gas to decompose and thereby deposit a structure exhibiting high resistivity onto the target. The precursor gas preferably comprises a first compound that would form a conductive layer and a second compound that would form an insulating layer if each of the first and second compounds were applied alone in the presence of the ion beam.Type: ApplicationFiled: January 23, 2002Publication date: August 1, 2002Inventors: Neil J. Bassom, Tung Mai
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Patent number: 6423647Abstract: For fabricating regions of dielectric material on a semiconductor substrate, a first layer of metal is deposited on the semiconductor substrate, and a first opening is etched through the first layer of metal at a first location area on the semiconductor substrate. First laser beams having a first laser power are directed toward the semiconductor substrate to form a first region of dielectric material having a first thickness at the first location area on the semiconductor substrate. The first layer of metal reflects the first laser beams away from the semiconductor substrate except at the first location area, and the first thickness of the first region of dielectric material is determined by the first laser power of the first laser beams. The first layer of metal is removed from the semiconductor substrate. A second layer of metal is then deposited on the semiconductor substrate, and a second opening is etched through the second layer of metal at a second location area on the semiconductor substrate.Type: GrantFiled: December 11, 2000Date of Patent: July 23, 2002Assignee: Advanced Micro Devices, Inc.Inventor: Bin Yu
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Patent number: 6417114Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.Type: GrantFiled: January 3, 2001Date of Patent: July 9, 2002Assignee: Hitachi, Ltd.Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
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Patent number: 6413866Abstract: A method of enriching the surface of a substrate with a solute material that was originally dissolved in the substrate material, to yield a uniform dispersion of the solute material at the substrate surface. The method generally entails the use of a solvent material that is more reactive than the solute material to a chosen reactive agent. The surface of the substrate is reacted with the reactive agent to preferentially form a reaction compound of the solvent material at the surface of the substrate. As the compound layer develops, the solute material segregates or diffuses out of the compound layer and into the underlying substrate, such that the region of the substrate nearest the compound layer becomes enriched with the solute material. At least a portion of the compound layer is then removed without removing the underlying enriched region of the substrate.Type: GrantFiled: March 15, 2000Date of Patent: July 2, 2002Assignee: International Business Machines CorporationInventors: Horatio S. Wildman, Lawrence A. Clevenger, Chenting Lin, Kenneth P. Rodbell, Stefan Weber, Roy C. Iggulden, Maria Ronay, Florian Schnabel
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Patent number: 6413321Abstract: Backside particle contamination of semiconductor wafers subjected to chemical vapor deposition is significantly reduced by optimizing various process parameters, alone or in combination. A high quality oxide seasoning layer is deposited to improve adhesion and trapping of contaminants remaining after a prior chamber cleaning step. Second, wafer pre-heating reduces thermal stress on the wafer during physical contact between the wafer and heater. Third, the duration of the gas stabilization flow of thermally reactive process gas species prior to CVD reaction is reduced, thereby preventing side products produced during this stabilization flow from affecting the wafer backside. Fourth, the wafer heater is redesigned to minimize physical contact between the heater surface and the wafer backside.Type: GrantFiled: December 7, 2000Date of Patent: July 2, 2002Assignee: Applied Materials, Inc.Inventors: Bok Hoen Kim, Mario Dave Silvetti, Ameeta Madhava, Davood Khalili, Martin Seamons, Emanuele Cappello, Nam Le, Lloyd Berken
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Patent number: 6410434Abstract: A LPCVD (Low Pressure Chemical Vapor Deposition) process is used for formation of a doped amorphous semiconductor film with in-situ doping of the semiconductor film on a plurality of semiconductor wafers with reduced defects and with predictable electrical characteristics. The plurality of semiconductor wafers are placed in a reaction chamber. The pressure within the reaction chamber is set to be less than approximately 1.0 Torr, and the temperature within the reaction chamber is set to a predetermined temperature in a range of from about 500° Celsius to about 550° Celsius. A semiconductor film reactant and a dopant reactant are introduced into the reaction chamber through at least two gas inlets. Each gas inlet is disposed on a respective location of the reaction chamber near the pluralty of semiconductor wafers, and each gas inlet carries both of the semiconductor film reactant and the dopant reactant.Type: GrantFiled: March 9, 2000Date of Patent: June 25, 2002Assignee: Advanced Micro Devices, Inc.Inventor: Balaraman Mani
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Patent number: 6403498Abstract: A substrate processing method of processing a surface of a substrate in manufacture of a semiconductor device, characterized by comprising a surface processing step for making a substance having an adsorption heat higher than that of an organic matter whose adsorption on the surface of the substrate, which has been cleaned, is undesirable, adsorbed on the surface of the substrate, and a film formation step for forming a thin film on the surface of the substrate which was processed in the above step.Type: GrantFiled: November 30, 1998Date of Patent: June 11, 2002Assignee: Tokyo Electron LimitedInventors: Takenobu Matsuo, Tsuyoshi Wakabayashi, Teruyuki Hayashi, Misako Saito
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Publication number: 20020068466Abstract: Methods of forming thin films include forming a first layer comprising a first element that is chemisorbed to a surface of a substrate, by exposing the surface to a first source gas having molecules therein that comprise the first element and a halogen. A step is then performed to expose the first layer to an activated hydrogen gas so that halogens associated with the first layer become bound to hydrogen provided by the activated hydrogen gas. The first layer may then be converted to a thin film comprising the first element and a second element, by exposing a surface of the first layer to a second source gas having molecules therein that comprise the second element.Type: ApplicationFiled: May 31, 2001Publication date: June 6, 2002Inventors: Seung-hwan Lee, Yeong-kwan Kim, Dong-chan Kim, Young-wook Park