Nitridation Patents (Class 438/775)
  • Patent number: 7563726
    Abstract: Disclosed are a semiconductor device with dual gate dielectric layers and a method for fabricating the same. The semiconductor device includes: a silicon substrate divided into a cell region where NMOS transistors are formed and a peripheral region where NMOS and PMOS transistors are formed; a targeted silicon oxide layer formed on the silicon substrate in the cell region; an oxynitride layer formed on the silicon substrate in the peripheral region; a first gate structure formed in the cell region; a second gate structure formed on the oxynitride layer in an NMOS region of the peripheral region; and a third gate structure formed on the oxynitride layer in a PMOS region of the peripheral region.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: July 21, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Heung-Jae Cho, Kwan-Yong Lim, Seung-Ryong Lee
  • Patent number: 7560394
    Abstract: A nanodot material including nanodots formed on silicon oxide, and a method of manufacturing the same, is provided. The nanodot material includes a substrate, a silicon oxide layer, and a plurality of nanodots on the silicon oxide layer.
    Type: Grant
    Filed: July 18, 2005
    Date of Patent: July 14, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-soo Park, Wan-jun Park, Alexander Alexandrovich Saranin, Andrey Vadimovich Zotov
  • Patent number: 7560393
    Abstract: A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum (silicon) nitride barrier layer, on a substrate by using a vapor deposition process with a refractory metal precursor compound, a disilazane, and an optional silicon precursor compound.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: July 14, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Brian A. Vaartstra
  • Patent number: 7550354
    Abstract: Nanoelectromechanical transistors (NEMTs) and methods of forming the same are disclosed. In one embodiment, an NEMT may include a substrate including a gate, a source region and a drain region; an electromechanically deflectable nanotube member; and a channel member electrically insulatively coupled to the nanotube member so as to be aligned with the source region and the drain region, wherein the electromechanical deflection of the nanotube member is controllable, in response to an electrical potential applied to the gate and the nanotube member, between an off state and an on state, the on state placing the channel member in electrical connection with the source region and the drain region to form a current path.
    Type: Grant
    Filed: July 11, 2007
    Date of Patent: June 23, 2009
    Assignee: International Business Machines Corporation
    Inventor: Huilong Zhu
  • Patent number: 7550353
    Abstract: One embodiment of a method for forming a semiconductor device can include forming a gate pattern on a semiconductor substrate and performing a selective re-oxidation process on the gate pattern in gas ambient including hydrogen, oxygen, and nitrogen. When the gate pattern includes a tunnel insulation layer, a metal nitride layer and a metal layer, the selective re-oxidation process heals the etching damage of a gate pattern and simultaneously prevents oxidation of the metal nitride layer and a tungsten electrode.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: June 23, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Hak Lee, Woong-Hee Sohn, Jae-Hwa Park, Gil-Heyun Choi, Byung-Hee Kim, Hee-Sook Park
  • Patent number: 7547646
    Abstract: A stress relief layer between a single-crystal semiconductor substrate and a deposited silicon nitride layer or pad nitride is formed from thermally produced silicon nitride. The stress relief layer made from thermally produced silicon nitride replaces a silicon dioxide layer or pad oxide which is customary at this location for example in connection with mask layers. After patterning of a mask, which includes a protective layer portion formed from deposited silicon nitride, the material which is provided according to the invention for the stress relief layer reduces the restrictions imposed for subsequent process steps, such as for example wet-etching steps, acting both on the semiconductor substrate or structures in the semiconductor substrate and also on the stress relief layer.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: June 16, 2009
    Assignee: Infineon Technologies AG
    Inventors: Henry Bernhardt, Michael Stadtmüller, Olaf Storbeck, Stefan Kainz
  • Patent number: 7541246
    Abstract: A gate insulating film and a gate electrode are formed on a silicon substrate. The gate insulating film contains at least hafnium, oxygen, fluorine, and nitrogen. The fluorine concentration is high in the vicinity of an interface with the silicon substrate and progressively decreases with decreasing distance from the gate electrode. The nitrogen concentration is high in the vicinity of an interface with the gate electrode and progressively decreases with decreasing distance from the silicon substrate. The fluorine concentration in the vicinity of the interface with the silicon substrate is preferably 1×1019 cm?3 or more. The nitrogen concentration in the vicinity of the interface with the gate electrode is preferably 1×1020 cm?3 or more.
    Type: Grant
    Filed: August 11, 2006
    Date of Patent: June 2, 2009
    Assignee: Fujitsu Limited
    Inventors: Yasuyuki Tamura, Takaoki Sasaki
  • Patent number: 7534731
    Abstract: A method for growing an oxynitride film on a substrate includes positioning the substrate in a process chamber, heating the process chamber, flowing a wet process gas comprising water vapor and a nitriding gas comprising nitric oxide into the process chamber. The wet process gas and the nitriding gas form a processing ambient that reacts with the substrate such that an oxynitride film grows on the substrate. In yet another embodiment, the method further comprises flowing a diluting gas into the process chamber while flowing the wet process gas to control a growth rate of the oxynitride film. In another embodiment, the method further comprises annealing the substrate and the oxynitride film in an annealing gas. According to embodiments of the method where the substrate is silicon, a silicon oxynitride film forms that exhibits a nitrogen peak concentration of at least approximately 6 atomic % and an interface state density of less than approximately 1.5 ×10 12 per cc.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: May 19, 2009
    Assignee: Tokyo Electron Limited
    Inventors: Kimberly G. Reid, Anthony Dip
  • Patent number: 7531411
    Abstract: A non-volatile memory structure comprises a trapping layer that includes a plurality of silicon-rich, silicon nitride layers. Each of the plurality of silicon-rich, silicon nitride layers can trap charge and thereby increase the density of memory structures formed using the methods described herein. In one aspect, the plurality of silicon-rich, silicon nitride layers are fabricated by converting an amorphous silicon layer by remote plasma nitrogen (RPN).
    Type: Grant
    Filed: October 12, 2005
    Date of Patent: May 12, 2009
    Assignee: Macronix International Co., Ltd.
    Inventors: Chi-Pin Lu, Ling-Wuu Yang, Kuang-Chao Chen
  • Patent number: 7531467
    Abstract: To provide a manufacturing method of a semiconductor device and a substrate processing apparatus capable of easily controlling a nitrogen concentration distribution in a film containing a metal atom and a silicon atom, and manufacturing a high quality semiconductor device. The method comprises a step of forming a film containing the metal atom and the silicon atom on a substrate 30 in a reaction chamber 4, and performing a nitriding process for the film, wherein the film is formed by changing a silicon concentration at least in two stages in the step of forming a film.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: May 12, 2009
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Atsushi Sano, Sadayoshi Horii, Hideharu Itatani, Masayuki Asai
  • Patent number: 7524774
    Abstract: An object of the present invention is to prevent an increase in film thickness and inhibit a reduction in capacity of a capacitor. In a semiconductor device having a capacitor, the capacitor includes a lower electrode, an upper electrode, and an insulating film interposed between the lower electrode and the upper electrode. A surface of the lower electrode on an insulating layer side is nitrided. If the lower electrode is made of polysilicon, nitriding the surface thereof increases oxidation resistance at the time of heat treatment in a post process. Particularly in a DRAM, the capacity of the capacitor is large, and therefore, this effect is significant. Further, leakage current inside the capacitor is also reduced.
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: April 28, 2009
    Assignee: Tokyo Electron Limited
    Inventors: Masaru Sasaki, Yoshiro Kabe
  • Publication number: 20090104743
    Abstract: Metal Oxide Semiconductor (MOS) transistors fabricated using current art may utilize a nitridation process on the gate dielectric to improve transistor reliability. Nitridation by the current art, which involves exposing the gate dielectric to a nitridation source, produces a significant concentration of nitrogen at the interface of the gate dielectric and the transistor substrate, which adversely affects transistor performance. This invention comprises the process of depositing a sacrificial layer on the gate dielectric prior to nitridation, exposing the sacrificial layer to a nitridation source, during which time nitrogen atoms diffuse through the sacrificial layer into the gate dielectric, then removing the sacrificial layer without degrading the gate dielectric. Work associated with this invention on high-k gate dielectrics has demonstrated a 20 percent reduction in nitrogen concentration at the gate dielectric-transistor substrate interface.
    Type: Application
    Filed: September 24, 2007
    Publication date: April 23, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Husam Alshareef, Manuel Quevedo Lopez
  • Patent number: 7521375
    Abstract: In methods of forming an oxide layer and an oxynitride layer, a substrate is loaded into a reaction chamber having a first pressure and a first temperature. The oxide layer is formed on the substrate using a reaction gas while increasing a temperature of the reaction chamber from the first temperature to a second temperature under a second pressure. Additionally, the oxide layer is nitrified in the reaction chamber to form the oxynitride layer on the substrate. When the oxide layer and/or the oxynitride layer are formed on the substrate, minute patterns of a semiconductor device, for example a DRAM device, an SRAM device or an LOGIC device may be easily formed on the oxide layer or the oxynitride layer.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: April 21, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-sub You, Hun-Hyeoung Leam, Seok-Woo Nam, Bong-Hyun Kim, Woong Lee, Sang-Hoon Lee
  • Patent number: 7517751
    Abstract: A substrate processing method includes the step of forming an oxide film by oxidizing a silicon substrate surface and the step of nitriding the oxide film to form an oxynitride film, wherein there is provided a step of purging oxygen after the oxidizing step but before said nitriding step from an ambient in which said nitriding processing is conducted.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: April 14, 2009
    Assignee: Tokyo Electron Limited
    Inventors: Takuya Sugawara, Seiji Matsuyama, Masaru Sasaki
  • Patent number: 7514376
    Abstract: A method for manufacturing a semiconductor device is disclosed which enables to suppress decrease in the mobility in a channel region by suppressing piercing of boron through a gate insulation film which boron is ion-implanted into a gate electrode. The method for manufacturing a semiconductor device includes: a step for forming a gate insulating layer on an active region of a semiconductor substrate; a step for introducing nitrogen through the front surface of the gate insulating layer using active nitrogen; and a step for conducting an annealing treatment in an NO gas atmosphere so that the nitrogen concentration distribution in the nitrogen-introduced gate insulating layer is high on the front surface side and low on the side of the interface with the semiconductor substrate.
    Type: Grant
    Filed: April 18, 2005
    Date of Patent: April 7, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Mitsuaki Hori
  • Patent number: 7514373
    Abstract: A method and apparatus for forming a nitrided gate dielectric layer. The method includes generating a nitrogen-containing plasma in a processing chamber via a smooth-varying modulated RF power source to reduce electron temperature spike. Field effect transistor channel mobility and gate leakage current results are improved when the power source is smooth-varying modulated, as compared to square-wave modulated.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: April 7, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Philip A. Kraus, Thai Cheng Chua
  • Patent number: 7507644
    Abstract: A method of manufacturing a flash memory device, wherein according to one embodiment, when a high dielectric material is formed by a remote plasma atomic layer deposition method, first and second dielectric layers are formed by one process at the same time using silicate as the first dielectric layer and the high dielectric layer formed on the silicate as the second dielectric layer. Accordingly, cost can be saved since the process is shortened, a film quality better than that of the existing dielectric layer structure can be obtained, and a film with improved step coverage can be formed. Furthermore, capacitance and insulating breakdown voltage can be increased by using silicate having a high dielectric constant and a high dielectric layer.
    Type: Grant
    Filed: July 19, 2006
    Date of Patent: March 24, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jae Hyoung Koo
  • Publication number: 20090072327
    Abstract: [Problems] To provide a semiconductor storage device with excellent electrical characteristics (write/erase characteristics) by means of favorable nitrogen concentration profile of a gate insulating film, and to provide a method for manufacturing such a device. [Means for Solving Problems] a semiconductor device fabricating method according to a first aspect of the invention, a method for fabricating a semiconductor storage device that operates by transferring charges through a gate insulating film formed between a semiconductor substrate and a gate electrode, includes a step for introducing an oxynitriding species previously diluted by plasma excitation gas, into a plasma processing apparatus, generating an oxynitriding species by means of a plasma, and forming an oxynitride film on the semiconductor substrate as the gate insulating film. The oxynitriding species contains NO gas at a ratio of 0.00001 to 0.01% to the total volume of gas introduced into the plasma processing apparatus.
    Type: Application
    Filed: September 30, 2005
    Publication date: March 19, 2009
    Applicants: TOKYO ELECTRON LIMITED, TOHOKU UNIVERSITY
    Inventors: Junichi Kitagawa, Shigenori Ozaki, Akinobu Teramoto, Tadahiro Ohmi
  • Patent number: 7498271
    Abstract: The present invention, in one embodiment, provides a method of forming a gate structure including providing a substrate including a semiconducting device region, a high-k dielectric material present atop the semiconducting device region, and a metal gate conductor atop the high-k dielectric material, applying a photoresist layer atop the metal gate conductor; patterning the photoresist layer to provide an etch mask overlying a portion of the metal gate conductor corresponding to a gate stack; etching the metal gate conductor and the high-k dielectric material selective to the etch mask; and removing the etch mask with a substantially oxygen free nitrogen based plasma.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: March 3, 2009
    Assignee: International Business Machines Corporation
    Inventors: Ricardo A. Donaton, Rashmi Jha, Siddarth A. Krishnan, Xi Li, Renee T. Mo, Naim Moumen, Wesley C. Natzle, Ravikumar Ramachandran, Richard S. Wise
  • Patent number: 7491652
    Abstract: A process for manufacturing semiconductor devices in an in-line processing includes the steps of: forming a silicon nitride film on a semiconductor wafer by nitrization in a reactor chamber having an inner pressure at a specific pressure; reducing the inner pressure from the specific pressure; raising the inner pressure up to the specific pressure; replacing the semiconductor wafer with another semiconductor wafer; and forming a nitride film on the another semiconductor wafer at the specific pressure.
    Type: Grant
    Filed: June 26, 2006
    Date of Patent: February 17, 2009
    Assignee: Elpida Memory, Inc.
    Inventors: Naonori Fujiwara, Hiroyuki Kitamura
  • Patent number: 7485516
    Abstract: A method of formation of integrated circuit devices includes forming a gate electrode stack over a portion of a semiconductor. The stack includes a gate dielectric layer with a gate electrode thereabove. Implant diatomic nitrogen and/or nitrogen atoms into the substrate aside from the stack at a maximum energy less than or equal to 10 keV for diatomic nitrogen and at a maximum energy less than or equal to 5 keV for atomic nitrogen at a temperature less than or equal to 1000° C. for a time of less than or equal to 30 minutes. Then form silicon oxide offset spacers on sidewalls of the stack. Form source/drain extension regions in the substrate aside from the offset spacers. Form nitride sidewall spacers on outer surfaces of the offset spacers over another portion of the nitrogen implanted layer. Then form source/drain regions in the substrate aside from the sidewall spacers.
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: February 3, 2009
    Assignee: International Business Machines Corporation
    Inventors: Thomas W. Dyer, Jinhong Li, Zhijiong Luo
  • Publication number: 20090026556
    Abstract: A method for producing a nitride semiconductor device according to the present invention includes the steps of: forming an insulating film containing oxygen on the surface of a group III nitride semiconductor; and placing the group III nitride semiconductor under a nitrogen atmosphere in advance of the step of forming the insulating film. A nitride semiconductor device according to the present invention includes a group III nitride semiconductor; and an insulating film containing oxygen formed on the surface of the group III nitride semiconductor, wherein the nitrogen concentration in a region provided with the insulating film is higher than the nitrogen concentration in a region not provided with the insulating film on the surface of the group III nitride semiconductor.
    Type: Application
    Filed: July 25, 2008
    Publication date: January 29, 2009
    Applicant: ROHM CO., LTD.
    Inventor: Hirotaka Otake
  • Patent number: 7482283
    Abstract: The present invention relates to a method and apparatus for forming a thin film using the ALD process. Prior to the ALD process where each of a plurality of source gasses is supplied one by one, plural times, a pretreatment process is performed in which the source gasses are simultaneously supplied to shorten an incubation period and improve throughput.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: January 27, 2009
    Assignee: Tokyo Electron Limited
    Inventors: Hideaki Yamasaki, Yumiko Kawano
  • Patent number: 7476627
    Abstract: Methods are provided herein for treating substrate surfaces in preparation for subsequent nucleation-sensitive depositions (e.g., polysilicon or poly-SiGe) and adsorption-driven deposition (e.g. atomic layer deposition or ALD). Prior to depositing, the surface is treated with non-depositing plasma products. The treated surface more readily nucleates polysilicon and poly-SiGe (such as for a gate electrode), or more readily adsorbs ALD reactants (such as for a gate dielectric). The surface treatment provides surface moieties more readily susceptible to a subsequent deposition reaction, or more readily susceptible to further surface treatment prior to deposition. By changing the surface termination of the substrate with a low temperature radical treatment, subsequent deposition is advantageously facilitated without depositing a layer of any appreciable thickness and without significantly affecting the bulk properties of the underlying material.
    Type: Grant
    Filed: May 9, 2006
    Date of Patent: January 13, 2009
    Assignee: ASM America, Inc.
    Inventors: Christophe F. Pomarede, Jeff Roberts, Eric J. Shero
  • Patent number: 7462571
    Abstract: An impurity-doped silicon nitride or oxynitride film is formed on a target substrate by CVD, in a process field to be selectively supplied with a first process gas containing a silane family gas, a second process gas containing a nitriding or oxynitriding gas, and a third process gas containing a doping gas. This method alternately includes first to fourth steps. The first step performs supply of the first and third process gases to the field. The second step stops supply of the first to third process gases to the field. The third step performs supply of the second process gas to the field while stopping supply of the first and third process gases to the field, and includes an excitation period of exciting the second process gas by an exciting mechanism. The fourth step stops supply of the first to third process gases to the field.
    Type: Grant
    Filed: July 26, 2005
    Date of Patent: December 9, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhide Hasebe, Mitsuhiro Okada, Pao-Hwa Chou, Chaeho Kim, Jun Ogawa
  • Patent number: 7459390
    Abstract: The present invention provides a method for manufacturing a semiconductor device having multiple gate dielectric thickness layers. The method, in one embodiment, includes forming a first layer of gate dielectric material over a semiconductor substrate in a first active region and a second active region of a semiconductor device, and patterning a masking layer to expose the first layer of gate dielectric material located in the first active region.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: December 2, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroaki Niimi, Reima Tapani Laaksonen
  • Patent number: 7456115
    Abstract: The present invention provides methods for forming semiconductor FET devices having reduced gate edge leakage current by using plasma or thermal nitridation and low-temperature plasma re-oxidation processes post gate etch.
    Type: Grant
    Filed: July 6, 2005
    Date of Patent: November 25, 2008
    Assignee: International Business Machines Corporation
    Inventors: Anthony I-Chih Chou, Shreesh Narasimha
  • Patent number: 7449384
    Abstract: Provided is a method of manufacturing a flash memory device. In accordance with the present invention, an undoped polysilicon layer is formed over a semiconductor substrate where a floating gate and a dielectric layer are formed. By performing N2 plasma process with respect to the undoped polysilicon layer, a heavily doped polysilicon layer is formed to form a control gate. Due to N2 plasma process, a nitrogen layer is formed at the interfaces between the dielectric layer and the undoped polysilicon layer. As a result, during a re-oxidization process, it is possible to prevent a thickness of the dielectric layer from being increased by reducing diffusion speed phosphorous and oxygen. Additionally, phosphorous of the heavily doped polysilicon layer is diffused into the undoped polysilicon layer in a subsequent process, thereby increasing a phosphorous concentration of the undoped polysilicon layer.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: November 11, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventor: Se Kyoung Choi
  • Patent number: 7446056
    Abstract: The present invention relates to a method for increasing the grain size of a polysilicon layer, which includes exposing a silicon oxide wafer in a deposition chamber to an amount, effective for the purpose, of nitrogen at a flow rate of at least about 240 standard liters per minute (slm). The instant invention further relates to a method for inhibiting the formation of a polysilicon seed in a furnace, which includes the treatment as noted above. The invention also relates to a method for forming a polysilicon layer, including: forming a silicon oxide layer on a substrate, the silicon oxide layer having a plurality of oxygen molecules therein; exposing the silicon oxide layer to a predetermined amount of nitrogen-containing gas in a furnace, whereby a plurality of nitrogen molecules in the nitrogen-containing gas replaces at least part of the oxygen molecules in the silicon oxide layer; and forming a polysilicon layer on the silicon oxide layer.
    Type: Grant
    Filed: December 1, 2005
    Date of Patent: November 4, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yao-Hui Huang, Tung-Li Lee, Chih-Hao Lin, Yen-Fei Lin, James Sun, Chen Pu-Fang, David Huang
  • Patent number: 7442653
    Abstract: An exemplary manufacturing method of an inter-metal dielectric of a semiconductor device according to an embodiment of the present invention includes forming a first silicon-rich oxide (SRO) layer on a silicon substrate provided with or otherwise having a copper line layer therein, forming a plasma enhanced fluorosilicate glass (PEFSG) layer on the first SRO layer, plasma-treating the PEFSG layer, and forming a second SRO layer on the plasma-treated PEFSG layer. According to the present invention, the thickness of the second SRO layer of the inter-metal dielectric can be reduced. Consequently, process cost can be reduced, and the total thickness of the inter-metal dielectric can be reduced so as to lower the dielectric constant thereof, reduce the aspect ratio of any via holes that are subsequently formed in the inter-metal dielectric, and potentially increase the yield as a result of the reduced via hole aspect ratio.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: October 28, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Tae-Young Lee
  • Patent number: 7439192
    Abstract: In a method of forming a thin layer for a semiconductor device through an ALD process and a CVD process in the same chamber, a semiconductor substrate is introduced into a processing chamber, and an interval between a showerhead and the substrate is adjusted to a first gap distance. A first layer is formed on the substrate at a first temperature through an ALD process. The interval between the showerhead and the substrate is additionally adjuted to a second gap distance, and a second layer is formed on the first layer at a second temperature through a CVD process. Accordingly, the thin layer has good current characteristics, and the manufacturing throughput of a semiconductor device is improved.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: October 21, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hun Seo, Young-Wook Park, Jin-Gi Hong
  • Patent number: 7432217
    Abstract: In a method of achieving uniform lengths of Carbon NanoTubes (CNTs) and a method of manufacturing a Field Emission Device (FED) using such CNTs, an organic film is coated to cover CNTs formed on a predetermined material layer. The organic film is etched to a predetermined depth to remove projected portions of the CNTs. After that, the organic film is removed.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: October 7, 2008
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Ha-Jin Kim, In-Taek Han
  • Publication number: 20080242109
    Abstract: A method for growing an oxynitride film on a substrate includes positioning the substrate in a process chamber, heating the process chamber, flowing a wet process gas comprising water vapor and a nitriding gas comprising nitric oxide into the process chamber. The wet process gas and the nitriding gas form a processing ambient that reacts with the substrate such that an oxynitride film grows on the substrate. In yet another embodiment, the method further comprises flowing a diluting gas into the process chamber while flowing the wet process gas to control a growth rate of the oxynitride film. In another embodiment, the method further comprises annealing the substrate and the oxynitride film in an annealing gas. According to embodiments of the method where the substrate is silicon, a silicon oxynitride film forms that exhibits a nitrogen peak concentration of at least approximately 6 atomic % and an interface state density of less than approximately 1.5×1012 per cc.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Kimberly G. Reid, Anthony Dip
  • Patent number: 7429538
    Abstract: A method of forming a silicon oxynitride gate dielectric. The method includes incorporating nitrogen into a dielectric film using a plasma nitridation process to form a silicon oxynitride film. The silicon oxynitride film is annealed in a first ambient. The first ambient comprises an inert ambient with a first partial pressure of oxygen at a first temperature. The silicon oxynitride film is then annealed in a second ambient comprising a second partial pressure of oxygen at a second temperature. The second partial pressure of oxygen is greater than the first partial pressure of oxygen.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: September 30, 2008
    Assignee: Applied Materials, Inc.
    Inventor: Christopher S. Olsen
  • Patent number: 7429540
    Abstract: A method for processing a semiconductor substrate in a chamber includes forming a silicon oxynitride film using a two-step anneal process. The first anneal step includes annealing the silicon oxynitride film in the presence of an oxidizing gas that has a partial pressure of about 1 to about 100 mTorr, and the second anneal step includes annealing the silicon oxynitride film with oxygen gas that has a flow rate of about 1 slm. The first anneal step is performed at a higher chamber temperature and higher chamber pressure than the second anneal step.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: September 30, 2008
    Assignee: Applied Materials, Inc.
    Inventor: Christopher S. Olsen
  • Publication number: 20080233763
    Abstract: In a method of achieving uniform lengths of Carbon NanoTubes (CNTs) and a method of manufacturing a Field Emission Device (FED) using such CNTs, an organic film is coated to cover CNTs formed on a predetermined material layer. The organic film is etched to a predetermined depth to remove projected portions of the CNTs. After that, the organic film is removed.
    Type: Application
    Filed: June 23, 2006
    Publication date: September 25, 2008
    Inventors: Ha-Jin Kim, In-Taek Han
  • Patent number: 7427572
    Abstract: A method for forming a silicon nitride film first deposits a silicon nitride film on a target substrate by CVD in a process field within a reaction container. This step is arranged to supply a first process gas containing a silane family gas and a second process gas containing a nitriding gas to the process field, and set the process field at a first temperature and a first pressure, for a first time period. The method then nitrides a surface of the silicon nitride film in the process field. This step is arranged to supply a surface-treatment gas containing a nitriding gas to the process field without supplying the first process gas, and set the process field at a second temperature and a second pressure, for a second time period shorter than the first time period.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: September 23, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhide Hasebe, Mitsuhiro Okada
  • Publication number: 20080224145
    Abstract: A semiconductor device includes a Si crystal having a crystal surface in the vicinity of a (111) surface, and an insulation film formed on said crystal surface, at least a part of said insulation film comprising a Si oxide film containing Kr or a Si nitride film containing Ar or Kr.
    Type: Application
    Filed: October 11, 2007
    Publication date: September 18, 2008
    Applicants: TOKYO ELECTRON LIMITED
    Inventors: Tadahiro Ohmi, Shigetoshi Sugawa, Katsuyuki Sekine, Yuji Saito
  • Patent number: 7420202
    Abstract: An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.
    Type: Grant
    Filed: November 8, 2005
    Date of Patent: September 2, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Vance H. Adams, Paul A. Grudowski, Venkat R. Kolagunta, Brian A. Winstead
  • Patent number: 7419918
    Abstract: In a method of forming a thin-film structure employed in a non-volatile semiconductor device, an oxide film is formed on a substrate. An upper nitride film is formed on the oxide film by nitrifying an upper portion of the oxide film through a plasma nitration process. A lower nitride film is formed between the substrate and the oxide film by nitrifying a lower portion of the oxide film through a thermal nitration process. A damage to the thin-film structure generated in the plasma nitration process may be at least partially cured in the thermal nitration process, and/or may be cured in a post-thermal treatment process.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: September 2, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul-Sung Kim, Yu-Gyun Shin, Bon-Young Koo, Ji-Hyun Kim, Young-Jin Noh
  • Patent number: 7413966
    Abstract: A method of forming a polycrystalline silicon active layer for use in a thin film transistor is provided. The method includes forming a buffer layer over a substrate, forming an amorphous silicon layer over the buffer layer, applying a catalytic metal to a surface of the amorphous silicon layer, crystallizing the amorphous silicon layer having the catalytic metal thereon into a polycrystalline silicon layer, annealing the polycrystalline silicon layer in an N2 gas atmosphere to stabilize the polycrystalline silicon layer, etching a surface of the polycrystalline silicon layer using an etchant, and patterning the polycrystalline silicon layer to form an island-shaped active layer.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: August 19, 2008
    Assignee: LG Phillips LCD Co., Ltd
    Inventors: Binn Kim, Jong-Uk Bae, Hae-Yeol Kim
  • Publication number: 20080194091
    Abstract: A method for fabricating a nitrided oxide layer. A plasma reactor including a pedestal for supporting a substrate is provided. A substrate having an oxide layer thereon is placed on the pedestal. Nitridation of the oxide layer is performed by exposing the substrate to decoupled nitrogen plasma, wherein a positive bias is applied to the pedestal during the nitridation to reduce a potential drop between the plasma and the substrate surface.
    Type: Application
    Filed: February 13, 2007
    Publication date: August 14, 2008
    Inventors: Su-Horng Lin, Hsuan-Yih Chu, Chi-Ming Yang
  • Publication number: 20080179714
    Abstract: A method comprises forming a material over a substrate and patterning the material to remove portions of the material and expose an underlying portion of the substrate. The method further includes performing an oxidation process to form an oxide layer over the exposed portion of the substrate and at an interface between the material and the substrate. A circuit comprises a non-critical device and an oxide formed as part of this non-critical device. A high-K dielectric material is formed over a substrate as part of the critical device within the circuit. An oxide based interface is provided between the high-K dielectric material and an underlying substrate. A second method forms a nitride or oxynitride as the first material.
    Type: Application
    Filed: January 25, 2007
    Publication date: July 31, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony I. Chou, Renee T. Mo, Shreesh Narasimha
  • Patent number: 7405125
    Abstract: Methods for forming a tunnel oxide structure device and methods for forming the structure are described. A structure comprising nitrogen is formed on a semiconductor substrate. The structure is oxidized. Nitrogen of the oxide structure is redistributed to form a region of concentrated nitrogen. Oxidizing the structure and redistributing the nitrogen is performed via radical oxidation. Nitrogen is added to the oxide structure. The region of concentrated nitrogen helps to regulate the depth of the added nitrogen.
    Type: Grant
    Filed: June 1, 2004
    Date of Patent: July 29, 2008
    Assignee: Macronix International Co., Ltd.
    Inventor: Szu-Yu Wang
  • Patent number: 7402472
    Abstract: A gate dielectric is treated with a nitridation step and an anneal. After this, an additional nitridation step and anneal is performed. The second nitridation and anneal results in an improvement in the relationship between gate leakage current density and current drive of the transistors that are ultimately formed.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: July 22, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sangwoo Lim, Paul A. Grudowski, Tien Ying Luo, Olubunmi O. Adetutu, Hsing H. Tseng
  • Patent number: 7399714
    Abstract: The invention includes a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the silicon dioxide is at least 10 ? above the substrate. After the nitrogen is formed within the silicon dioxide layer, conductively doped silicon is formed on the silicon dioxide layer.
    Type: Grant
    Filed: January 14, 2004
    Date of Patent: July 15, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Kevin L. Beaman, John T. Moore
  • Patent number: 7396776
    Abstract: A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: July 8, 2008
    Assignee: International Business Machines Corporation
    Inventors: Anthony I. Chou, Toshiharu Furukawa, Wilfried Haensch, Zhibin Ren, Dinkar V. Singh, Jeffrey W. Sleight
  • Patent number: 7381620
    Abstract: A method includes forming at least a portion of a semiconductor device in a processing chamber containing oxygen and removing substantially all of the oxygen from the processing chamber. The method further includes forming remaining portions of the semiconductor device in the processing chamber without the presence of oxygen.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: June 3, 2008
    Assignee: Spansion LLC
    Inventors: Boon-Yong Ang, Hidehiko Shiraiwa, Simon S. Chan, Harpreet K. Sachar, Mark Randolph
  • Patent number: 7371647
    Abstract: The invention encompasses a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the silicon dioxide is at least 10 ? above the substrate. After the nitrogen is formed within the silicon dioxide layer, conductively doped silicon is formed on the silicon dioxide layer. The invention encompasses a method of forming a pair of transistors associated with a semiconductor substrate. First and second regions of the substrate are defined. A first oxide region is formed to cover the first region of the substrate, and to not cover the second region of the substrate. Nitrogen is formed within the first oxide region, and a first conductive layer is formed over the first oxide region. After the first conductive layer is formed, a second oxide region is formed over the second region of the substrate.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: May 13, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Kevin L. Beaman, John T. Moore
  • Patent number: 7365028
    Abstract: The invention includes methods of forming metal oxide and/or semimetal oxide. The invention can include formation of at least one metal-and-halogen-containing material and/or at least one semimetal-and-halogen-containing material over a semiconductor substrate surface. The material can be subjected to aminolysis followed by oxidation to convert the material to metal oxide and/or semimetal oxide. The aminolysis and oxidation can be separate ALD steps relative to one another, or can be conducted in a reaction chamber in a common processing step.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: April 29, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh