Nitridation Patents (Class 438/775)
  • Patent number: 7361567
    Abstract: A nanocrystal non-volatile memory (NVM) has a dielectric between the control gate and the nanocrystals that has a nitrogen content sufficient to reduce the locations in the dielectric where electrons can be trapped. This is achieved by grading the nitrogen concentration. The concentration of nitrogen is highest near the nanocrystals where the concentration of electron/hole traps tend to be the highest and is reduced toward the control gate where the concentration of electron/hole traps is lower. This has been found to have the beneficial effect of reducing the number of locations where charge can be trapped.
    Type: Grant
    Filed: January 26, 2005
    Date of Patent: April 22, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Rajesh A. Rao, Ramachandran Muralidhar, Bruce E. White
  • Patent number: 7361560
    Abstract: A method for manufacturing a dielectric layer structure for a non-volatile memory cell is provided. A method includes forming a first dielectric layer for tunneling on a semiconductor substrate, a second dielectric layer on the first dielectric layer to store charges, nitrogenizing surface of the second dielectric layer, and forming a third dielectric layer the nitridedsecond dielectric layer.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: April 22, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jai-Dong Lee, Ki-Chul Kim, In-Wook Cho
  • Patent number: 7351668
    Abstract: An insulating film is formed on a target substrate by CVD, in a process field to be selectively supplied with a first process gas containing a silane family gas, a second process gas containing a nitriding or oxynitriding gas, and a third process gas containing a carbon hydride gas. This method alternately includes first to fourth steps. The first step performs supply of the first and third process gases to the field while stopping supply of the second process gas to the process field. The second step stops supply of the first to third process gases to the field. The third step performs supply of the second process gas to the field while stopping supply of the first and third process gases to the field. The fourth step stops supply of the first to third process gases to the field.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: April 1, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Pao-Hwa Chou, Kazuhide Hasebe
  • Patent number: 7345001
    Abstract: The present invention provides a gate dielectric having a flat nitrogen profile, a method of manufacture therefor, and a method of manufacturing an integrated circuit including the flat nitrogen profile. In one embodiment, the method of manufacturing the gate dielectric includes forming a gate dielectric layer (410) on a substrate (310), and subjecting the gate dielectric layer (410) to a nitrogen containing plasma process (510), wherein the nitrogen containing plasma process (510) has a ratio of helium to nitrogen of 3:1 or greater.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: March 18, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroaki Niimi, Husam N. Alshareef, Rajesh Khamankar, Toan Tran
  • Patent number: 7338900
    Abstract: A method for forming a tungsten nitride film including a first material gas supply step of supplying a first material gas composed of a tungsten compound gas, a reduction step of supplying a reducing gas, a second material gas supply step of supplying a second material gas composed of a tungsten compound gas, and a nitridation step of supplying a nitriding gas. Since a step of depositing tungsten on a substrate 5, and a step of forming tungsten nitride are performed separately, by varying the flow rate of each gas, the pressure when each gas is supplied, and the supply time, or the number of times each step is performed and the order in which the steps are performed, the quantity of tungsten deposited and the quantity of tungsten nitride formed can be controlled easily.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: March 4, 2008
    Assignee: Ulvac Inc.
    Inventors: Eiichi Mizuno, Narishi Gonohe, Masamichi Harada, Nobuyuki Kato
  • Patent number: 7338894
    Abstract: A semiconductor device includes a substrate (12), a first insulating layer (14) over a surface of the substrate (12), a layer of nanocrystals (13) over a surface of the first insulating layer (14), a second insulating layer (15) over the layer of nanocrystals (13). A nitriding ambient is applied to the second insulating layer (15) to form a barrier to further oxidation when a third insulating layer (22) is formed over the substrate (12). The nitridation of the second insulating layer (15) prevents oxidation or shrinkage of the nanocrystals and an increase in the thickness of the first insulating layer 14 without adding complexity to the process flow for manufacturing the semiconductor device (10).
    Type: Grant
    Filed: January 26, 2005
    Date of Patent: March 4, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sangwoo Lim, Robert F. Steimle
  • Publication number: 20080032513
    Abstract: An integrated circuit system including loading a wafer into a processing chamber and pre-purging the processing chamber with a first ammonia gas. Depositing a first nitride layer over the wafer and purging the processing chamber with a second ammonia gas. Depositing a second nitride layer over the first nitride layer that is misaligned with the first nitride layer. Post-purging the processing chamber with a third ammonia gas and purging the processing chamber with a nitrogen gas.
    Type: Application
    Filed: July 5, 2006
    Publication date: February 7, 2008
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Sripad Sheshagiri Nagarad, Hwa Weng Koh, Dong Kyun Sohn, Xiaoyu Chen, Louis Lim, Sung Mun Jung, Chiew Wah Yap, Pradeep Ramachandramurthy Yelehanka, Nitin Kamat
  • Patent number: 7312139
    Abstract: A method of fabricating a nitrogen-containing gate dielectric layer is described. First, a gate dielectric layer is formed on a substrate by performing a dilute wet oxidation process. Then, a nitridation step is performed for doping nitrogen into the gate dielectric layer. After that, a re-oxidation step is performed for repairing the nitrogen-doped gate dielectric layer. The above steps are carried out inside the same reaction chamber. Moreover, two or more wafers can be treated inside the reaction chamber at the same time.
    Type: Grant
    Filed: January 3, 2005
    Date of Patent: December 25, 2007
    Assignee: United Microelectronics Corp.
    Inventors: Yu-Ren Wang, Ying-Wei Yen, Michael Chan
  • Patent number: 7300890
    Abstract: A silicon nitride film formation method includes: Heating a substrate to be subjected to film formation to a substrate temperature; heating a wire to a wire temperature; supplying silane, ammonia, and hydrogen gases to the heating member; and forming a silicon nitride film on the substrate.
    Type: Grant
    Filed: July 17, 2003
    Date of Patent: November 27, 2007
    Assignee: Midwest Research Institute
    Inventor: Qi Wang
  • Patent number: 7297641
    Abstract: Multiple sequential processes are conducted in a reaction chamber to form ultra high quality silicon-containing compound layers, including silicon nitride layers. In a preferred embodiment, a silicon layer is deposited on a substrate using trisilane as the silicon precursor. A silicon nitride layer is then formed by nitriding the silicon layer. By repeating these steps, a silicon nitride layer of a desired thickness is formed.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: November 20, 2007
    Assignee: ASM America, Inc.
    Inventors: Michael A. Todd, Keith D. Weeks, Christiaan J. Werkhoven, Christophe F. Pomarede
  • Patent number: 7294582
    Abstract: Sequential processes are conducted in a batch reaction chamber to form ultra high quality silicon-containing compound layers, e.g., silicon nitride layers, at low temperatures. Under reaction rate limited conditions, a silicon layer is deposited on a substrate using trisilane as the silicon precursor. Trisilane flow is interrupted. A silicon nitride layer is then formed by nitriding the silicon layer with nitrogen radicals, such as by pulsing the plasma power (remote or in situ) on after a trisilane step. The nitrogen radical supply is stopped. Optionally non-activated ammonia is also supplied, continuously or intermittently. If desired, the process is repeated for greater thickness, purging the reactor after each trisilane and silicon compounding step to avoid gas phase reactions, with each cycle producing about 5-7 angstroms of silicon nitride.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: November 13, 2007
    Assignee: ASM International, N.V.
    Inventors: Ruben Haverkort, Yuet Mei Wan, Marinus J. De Blank, Cornelius A. van der Jeugd, Jacobus Johannes Beulens, Michael A. Todd, Keith D. Weeks, Christian J. Werkhoven, Christophe F. Pomarede
  • Patent number: 7291568
    Abstract: A method of fabricating a gate dielectric layer, including: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; performing a plasma nitridation in a reducing atmosphere to convert the silicon dioxide layer into a silicon oxynitride layer. The dielectric layer so formed may be used in the fabrication of MOSFETs.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: November 6, 2007
    Assignee: International Business Machines Corporation
    Inventors: Jay S. Burnham, James S. Nakos, James J. Quinlivan, Bernie A. Roque, Jr., Steven M. Shank, Beth A. Ward
  • Publication number: 20070238316
    Abstract: A method for manufacturing a semiconductor device includes the steps of: forming a SiO2 layer on a silicon substrate; forming on the SiO2 layer an SiN film having a N/Si composition ratio smaller than the stoichiometric composition ratio of SiN by using the ALD technique; and performing a plasma-nitriding process on the SiN layer at a substrate temperature of 550 degrees C. or below.
    Type: Application
    Filed: April 5, 2007
    Publication date: October 11, 2007
    Applicant: ELPIDA MEMORY INC.
    Inventor: Takuo Ohashi
  • Publication number: 20070238315
    Abstract: Semiconductor process technology and devices are provided, including a method for forming a high quality group III nitride layer on a silicon substrate and to a device obtainable therefrom. According to the method, a pre-dosing step is applied to a silicon substrate, wherein the substrate is exposed to at least 0.01 ?mol/cm2 of one or more organometallic compounds containing Al, in a flow of less than 5 ?mol/min. The preferred embodiments are equally related to the semiconductor structure obtained by the method, and to a device comprising said structure.
    Type: Application
    Filed: March 23, 2007
    Publication date: October 11, 2007
    Applicant: Interuniversitair Microelektronica Centrum (IMEC)
    Inventors: Kai Cheng, Maarten Leys, Stefan Degroote
  • Patent number: 7268050
    Abstract: A method for fabricating a MOS transistor in a semiconductor device is disclosed. An example method subjects a surface of a semiconductor substrate to thermal oxidation to form an oxide film for forming a gate insulating film, deposits a polysilicon layer on the oxide film for forming a gate, applies a coat of photoresist onto the polysilicon layer, and performs exposure and development by using an exposure mask which defines the gate to form a photoresist pattern covering a region where the gate is to be formed. The example method also performs dry etching to remove the polysilicon layer for forming the gate and the oxide film for forming the gate insulating film, which are not protected with the photoresist pattern, to form a gate pattern, performs annealing under a nitrogen environment to form a nitrided oxide film, and forms buried lightly doped impurity ion layers on opposite sides of the gate pattern.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: September 11, 2007
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Min Ho Jeong
  • Patent number: 7268087
    Abstract: In order to provide a manufacturing method of a semiconductor device which can improve the interconnection lifetime, while controlling the increase in resistance thereof, and, in addition, can raise the manufacturing stability; by applying a plasma treatment to the surface of a copper interconnection 17 with a source gas comprising a nitrogen element being used, a copper nitride layer 24 is formed, and thereafter a silicon nitride film 18 is formed. Hereat, under the copper nitride layer 24, a thin copper silicide layer 25 is formed.
    Type: Grant
    Filed: July 28, 2004
    Date of Patent: September 11, 2007
    Assignee: NEC Electronics Corporation
    Inventors: Hidemitsu Aoki, Hiroaki Tomimori, Norio Okada, Tatsuya Usami, Koichi Ohto, Takamasa Tanikuni
  • Patent number: 7268088
    Abstract: One or more aspects of the present invention relate to forming a dielectric suitable for use as a gate dielectric in a transistor. The gate dielectric is formed by a nitridation process that adds nitrogen to a semiconductor substrate.
    Type: Grant
    Filed: August 4, 2005
    Date of Patent: September 11, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Hiroaki Niimi
  • Patent number: 7265065
    Abstract: A method for fabricating a dielectric layer doped with nitrogen is provided according to the present invention. According to the method, a dielectric layer is formed on a semiconductor substrate. Two steps of nitridation processes are then performed on the dielectric layer. Following that, one step or two steps of annealing processes are performed on the dielectric layer. Dielectric layer formed by the method has uniform nitrogen dopant, and thus has fine electric properties.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: September 4, 2007
    Assignee: United Microelectronics Corp.
    Inventors: Yun-Ren Wang, Ying-Wei Yen, Chien-Hua Lung, Kuo-Tai Huang
  • Patent number: 7250375
    Abstract: A method of processing a for an electronic device, comprising, at least: a nitridation step (a) of supplying nitrogen radicals on the surface of the electronic device substrate, to thereby form a nitride film on the surface thereof; and a hydrogenation step (b) of supplying hydrogen radicals to the surface of the electronic device substrate. By use of this method, it is possible to recover the degradation in the electric property of an insulating film due to a turnaround phenomenon which can occur at the time of nitriding an Si substrate, etc.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: July 31, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Toshio Nakanishi, Takuya Sugawara, Seiji Matsuyama, Masaru Sasaki
  • Patent number: 7238625
    Abstract: The present invention provides a method for processing a semiconductor device wherein a dielectric layer is partially converted into a silicon-oxy-nitride by incorporation of nitrogen atoms into the dielectric layer, which comprises a silicon oxide. Before the introduction of the nitrogen atoms into the dielectric layer, the dielectric layer is provided as a silicon oxide in which the atomic silicon to oxygen ration is greater than ½. In this way, MOS transistors are obtained with a high quality interface between the dielectric region and semiconductor substrate, and a dielectric region which is impermeable to impurity atoms from the gate region and which has a thickness which is substantially equal to the dielectric layer as deposited.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: July 3, 2007
    Assignees: Interuniversitair Microelektronika Centrum (IMEC), Koninklijke Philips Electronics N.V.
    Inventors: Vincent Charles Venezia, Florence Nathalie Cubaynes
  • Patent number: 7232772
    Abstract: A substrate processing method comprises the step of forming an oxide film on a silicon substrate surface, and introducing nitrogen atoms into the oxide film by exposing the oxide film to nitrogen radicals excited in plasma formed by a microwave introduced via a planar antenna.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: June 19, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Seiji Matsuyama, Takuya Sugawara, Shigenori Ozaki, Toshio Nakanishi, Masaru Sasaki
  • Patent number: 7214613
    Abstract: A semiconductor device includes a cross diffusion barrier layer sandwiched between a gate layer and an electrode layer. The gate layer has a first gate portion of doped polysilicon of first conductivity type adjacent to a second gate portion doped polysilicon of second conductivity type. The cross diffusion barrier layer includes a combination of silicon and nitrogen. The cross diffusion barrier layer adequately prevents cross diffusion between the first and second gate portions while causing no substantial increase in the resistance of the gate layer.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: May 8, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Chih-Chen Cho, Robert Burke, Anuradha Iyengar, Eugene R. Gifford
  • Patent number: 7202186
    Abstract: Ultra-thin oxynitride layers are formed utilizing low-pressure processing to achieve self-limiting oxidation of substrates and provide ultra-thin oxynitride. The substrates to be processed can contain an initial dielectric layer such as an oxide layer, an oxynitride layer, or a nitride layer, or alternatively can lack an initial dielectric layer. The processing can be carried out using a batch type process chamber or a single-wafer process chamber.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: April 10, 2007
    Assignees: Tokyo Electron Limited, International Business Machines Corporation (IBM)
    Inventors: David L O'Meara, Cory Wajda, Anthony Dip, Michael Toeller, Toshihara Furukawa, Kristen Scheer, Alessandro Callegari, Fred Buehrer, Sufi Zafar, Evgeni Gousev, Anthony Chou, Paul Higgins
  • Patent number: 7189661
    Abstract: There are provided a method and an apparatus of forming an insulating layer including silicon oxynitride. The method includes performing a plasma treatment process for supplying a plasma reaction gas to a substrate to be treated after completing the annealing process. The apparatus includes a sealed processing room having gas supply and exhaust lines running thereto. A quartz inner tube and quartz inlet pipe both include holes therethrough, but in orthogonal directions to one another, to flow a reaction gas onto the wafers loaded within the sealed processing room.
    Type: Grant
    Filed: July 13, 2005
    Date of Patent: March 13, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Sub You, Cheol-Kyu Yang, Woong Lee, Jae-Chul Lee, Hun-Hyeoung Leam
  • Patent number: 7183143
    Abstract: A method for forming a nitrided tunnel oxide layer is described. A silicon oxide layer as a tunnel oxide layer is formed on a semiconductor substrate, and a plasma nitridation process is performed to implant nitrogen atoms into the silicon oxide layer. A thermal drive-in process is then performed to diffuse the implanted nitrogen atoms across the silicon oxide layer.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: February 27, 2007
    Assignee: Macronix International Co., Ltd.
    Inventor: Tzu-Yu Wang
  • Patent number: 7179754
    Abstract: A method and apparatus for forming a nitrided gate dielectric layer. The method includes generating a nitrogen-containing plasma in a processing chamber via a smooth-varying modulated RF power source to reduce electron temperature spike. Field effect transistor channel mobility and gate leakage current results are improved when the power source is smooth-varying modulated, as compared to square-wave modulated.
    Type: Grant
    Filed: April 6, 2004
    Date of Patent: February 20, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Philip A. Kraus, Thai Cheng Chua
  • Patent number: 7176094
    Abstract: DPN (decoupled plasma nitridation) is used to improve robustness of ultra thin gate oxides. Conventionally, this is followed by an anneal in pure helium to remove structural defects in the oxide. However, annealing under these conditions has been found to cause a deterioration of the electrical performance of devices. This problem has been overcome by annealing, in a 1:4 oxygen-nitrogen mixture (1,050° C. at about 10 torr) instead of in helium or nitrogen oxide. This results in a gate oxide that is resistant to boron contamination without suffering any loss in its electrical properties.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: February 13, 2007
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Dong Zhong, Yun Ling Tan, Chew Hoe Ang, Jia Zhen Zheng
  • Patent number: 7157332
    Abstract: Disclosed is a method for manufacturing a flash memory cell. A structure in which a floating gate, an ONO dielectric film and a control gate are stacked is formed by means of a gate mask process and an etch process. After a rapid thermal nitrification process is performed, a re-oxidization process is performed. Therefore, Si-dangling bonding broken during the gate etch process becomes a Si—N bonding structure by means of a rapid thermal nitrification process. As such, as abnormal oxidization occurring at the side of an ONO dielectric film during a re-oxidization process is prohibited, a smiling phenomenon of the ONO dielectric film is prevented.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: January 2, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventor: Noh Yeal Kwak
  • Patent number: 7148155
    Abstract: A silicon dioxide-based dielectric layer is formed on a substrate surface by a sequential deposition/anneal technique. The deposited layer thickness is insufficient to prevent substantially complete penetration of annealing process agents into the layer and migration of water out of the layer. The dielectric layer is then annealed, ideally at a moderate temperature, to remove water and thereby fully densify the film. The deposition and anneal processes are then repeated until a desired dielectric film thickness is achieved.
    Type: Grant
    Filed: October 26, 2004
    Date of Patent: December 12, 2006
    Assignee: Novellus Systems, Inc.
    Inventors: Raihan M. Tarafdar, George D. Papasouliotis, Ron Rulkens, Dennis M. Hausmann, Jeff Tobin, Adrianne K. Tipton, Bunsen Nie
  • Patent number: 7148101
    Abstract: Capacitors of semiconductor devices and methods of fabricating the same are disclosed. An example capacitor-fabricating method comprises: forming a first insulating layer by nitrifying a semiconductor substrate; forming a second insulating layer by depositing a transition element on the first insulating layer and performing a reoxidation process; forming a third insulating layer by nitrifying the second insulating layer using a forming gas; and forming a conducting layer on top of the third insulating layer.
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: December 12, 2006
    Assignee: Dongbu Electronics, Co., Ltd.
    Inventor: Jeong Ho Park
  • Patent number: 7135416
    Abstract: A method of manufacturing a semiconductor device including a gallium nitride related semiconductor. The method include preparing a substrate having surface of a gallium nitride related semiconductor; contacting the surface with atomic nitrogen, which is obtained by decomposing a nitrogen-containing gas in a catalytic reaction, to nitride the surface; and forming, on the surface, a gate electrode and source and drain electrodes opposing each other across the gate electrode.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: November 14, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masahiro Totsuka, Tomoki Oku
  • Patent number: 7132346
    Abstract: The present invention relates to a method for fabricating a capacitor employing ALD-TiN as an upper electrode and being suitable for preventing a deterioration of a leakage current property which uses an ALD-TiN as an upper electrode. The method for fabricating the capacitor includes: forming a lower electrode on a semiconductor substrate; forming a dielectric layer on the lower electrode; loading the semiconductor substrate containing the dielectric layer into a deposition chamber; nitriding a surface of the dielectric layer while NH3 gas is flowed into the deposition chamber; and forming an upper layer by using a source gas NH3, containing Titanium (Ti) on the nitrated surface of the dielectric layer through an atomic layer deposition (ALD) method.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: November 7, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yong-Soo Kim
  • Patent number: 7132328
    Abstract: The present invention relates to a method of manufacturing a semiconductor device. According to the present invention, an ONO1 HTO film and an ONO2 nitride film are sequentially formed on a polysilicon layer for floating gate and an oxide film for ONO3 is formed as a SiON film by oxidizing the surface of the ONO2 nitride film. Thus, the oxide film for ONO3 having a better film quality and a high dielectric constant compared to an existing HTO oxide film is formed. Accordingly, capacitance and a breakdown voltage are increased and charge leakage and retention properties are thus improved. Furthermore, it is possible to reduce the cost through reduction in process by replacing an ONO3 annealing process and a subsequent high temperature steam annealing process with a single process.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: November 7, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kwang Chul Joo
  • Patent number: 7129128
    Abstract: Methods for forming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are provided. A self-limiting nitric oxide (NO) anneal of a polysilicon layer such as an HSG polysilicon capacitor electrode, at less than 800° C., is utilized to grow a thin oxide (oxynitride) layer of about 40 angstroms or less over the polysilicon layer. The NO anneal provides a nitrogen layer at the polysilicon-oxide interface that limits further oxidation of the polysilicon layer and growth of the oxide layer. The oxide layer is exposed to a nitrogen-containing gas to nitridize the surface of the oxide layer and reduce the effective dielectric constant of the oxide layer. The process is particularly useful in forming high K dielectric insulating layers such as tantalum pentoxide over polysilicon.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: October 31, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Ronald A. Weimer
  • Patent number: 7129187
    Abstract: A method for low-temperature plasma-enhanced chemical vapor deposition of a silicon-nitrogen-containing film on a substrate. The method includes providing a substrate in a process chamber, exciting a reactant gas in a remote plasma source, thereafter mixing the excited reactant gas with a silazane precursor gas, and depositing a silicon-nitrogen-containing film on the substrate from the excited gas mixture in a chemical vapor deposition process. In one embodiment of the invention, the reactant gas can contain a nitrogen-containing gas to deposit a SiCNH film. In another embodiment of the invention, the reactant gas can contain an oxygen-containing gas to deposit a SiCNOH film.
    Type: Grant
    Filed: July 14, 2004
    Date of Patent: October 31, 2006
    Assignee: Tokyo Electron Limited
    Inventor: Raymond Joe
  • Patent number: 7129188
    Abstract: A transistor gate is formed which comprises semiconductive material and conductive metal. Source/drain regions are formed proximate the transistor gate. In one implementation, the transistor gate and source/drain regions are exposed to a gas mixture comprising H2O, H2, a noble gas and N2 under conditions effective to oxidize outer surfaces of the source/drain regions. The N2 is present in the gas mixture at greater than 0% and less than or equal to 20.0% by volume. In one implementation, the transistor gate and source/drain regions are exposed to a gas mixture comprising H2O, H2, and an inert gas under conditions effective to oxidize outer surfaces of the source/drain regions. The conditions comprise a pressure of greater than room ambient pressure. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: October 31, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Don Carl Powell
  • Patent number: 7122454
    Abstract: A method is provided wherein a gate dielectric film that is plasma nitrided in a chamber of one system is subsequently heated or “annealed” in another chamber of the same system. Processing delay can be controlled so that all wafers processed in the system experience similar nitrogen content.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: October 17, 2006
    Assignee: Applied Materials, Inc.
    Inventor: Christopher S. Olsen
  • Patent number: 7122464
    Abstract: A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum (silicon) nitride barrier layer, on a substrate by using a vapor deposition process with a refractory metal precursor compound, a disilazane, and an optional silicon precursor compound.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: October 17, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Brian A. Vaartstra
  • Patent number: 7101811
    Abstract: A dielectric layer may be formed by depositing the dielectric layer to an intermediate thickness and applying a nitridation process to the dielectric layer of intermediate thickness. The dielectric layer may then be deposited to the final, desired thickness.
    Type: Grant
    Filed: May 8, 2003
    Date of Patent: September 5, 2006
    Assignee: Intel Corporation
    Inventors: Ronald John Kuse, Tetsuji Yasuda
  • Patent number: 7094707
    Abstract: A method of nitriding a gate oxide layer by annealing a preformed oxide layer with nitric oxide (NO) gas in a hot wall, single wafer furnace is provided. The nitridation process can be carried out rapidly (i.e., at nitridation times of 30 seconds to 2 minutes) while providing acceptable levels of nitridation (i.e., up to 6 at. %) and desirable nitrogen/depth profiles. The nitrided gate oxide layer can optionally be reoxidized in a second oxidation step after the nitridation step. A gate electrode layer (e.g., boron doped polysilicon) can then be deposited on top of the nitrided gate oxide layer or on top of the reoxidized and nitrided gate oxide layer.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: August 22, 2006
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Sundar Narayanan
  • Patent number: 7091136
    Abstract: A process of forming a compound film includes formulating a nano-powder material with a controlled overall composition and including particles of one solid solution. The nano-powder material is deposited on a substrate to form a layer on the substrate, and the layer is reacted in at least one suitable atmosphere to form the compound film. The compound film may be used in fabrication of a radiation detector or solar cell.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: August 15, 2006
    Inventor: Bulent M. Basol
  • Patent number: 7091135
    Abstract: There is disclosed a method of manufacturing a semiconductor device, which comprises forming a film containing metal elements and silicon elements on a semiconductor substrate, exposing the semiconductor substrate to an atmosphere containing an oxidant to form a silicon dioxide film at the interface between the semiconductor substrate and the film containing metal elements and silicon elements, and nitriding the film containing metal elements and silicon elements after forming the silicon dioxide film.
    Type: Grant
    Filed: March 12, 2004
    Date of Patent: August 15, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiji Inumiya, Kazuhiro Eguchi
  • Patent number: 7092287
    Abstract: A method of forming silicon nitride nanodots that comprises the steps of forming silicon nanodots and then nitriding the silicon nanodots by exposing them to a nitrogen containing gas. Silicon nanodots were formed by low pressure chemical vapor deposition. Nitriding of the silicon nanodots was performed by exposing them to nitrogen radicals formed in a microwave radical generator, using N2 as the source gas.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: August 15, 2006
    Assignee: ASM International N.V.
    Inventors: Jacobus Johannes Beulens, Yuet Mei Wan
  • Patent number: 7078354
    Abstract: After a first gate oxide film (302) is formed on a substrate (301), a nitride layer (303) is formed by a first oxynitriding process. The first gate oxide film is selectively removed from a thinner film part area of the substrate. A second gate oxide film forming process forms a second gate oxide film (305A) in the thinner film part area and a third gate oxide film (305B) in a thicker film part area. By executing second oxynitriding process, nitride layers (306A and 306B) are formed at the thinner and the thicker part areas.
    Type: Grant
    Filed: May 12, 2004
    Date of Patent: July 18, 2006
    Assignee: Elpida Memory, Inc.
    Inventor: Takayuki Kanda
  • Patent number: 7074708
    Abstract: A method for processing a substrate including depositing a dielectric layer containing silicon, oxygen, and carbon on the substrate by chemical vapor deposition, wherein the dielectric layer has a carbon content of at least 1% by atomic weight and a dielectric constant of less than about 3, and depositing a silicon and carbon containing layer on the dielectric layer. The dielectric constant of a dielectric layer deposited by reaction of an organosilicon compound having three or more methyl groups is significantly reduced by further depositing an amorphous hydrogenated silicon carbide layer by reaction of an alkylsilane in a plasma of a relatively inert gas.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: July 11, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Frederic Gaillard, Li-Qun Xia, Tian-Hoe Lim, Ellie Yieh, Wai-Fan Yau, Shin-Puu Jeng, Kuowei Liu, Yung-Cheng Lu
  • Patent number: 7067425
    Abstract: A method of manufacturing a flash memory device includes the steps of forming a nitride film on an entire surface of a trench by means of an annealing process to prevent implanted ions for adjusting a threshold voltage from diffusing to a device isolation region, and forming a side wall oxide film on a surface of the nitride film. The nitride film plays a role of preventing ions implanted into a substrate for adjusting a threshold voltage from flowing into the side wall oxidation film.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: June 27, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventor: Keun Woo Lee
  • Patent number: 7064085
    Abstract: A feed-forward method and apparatus for controlling spacer width measures spacer width during processing then further processes the spacers in a spacer width adjustment operation to achieve a desired final spacer width. Silicon nitride spacers may be measured after plasma etching and the measured spacer width is automatically compared to the final desired spacer width and a time for further processing is calculated based on a correlation between processing time and spacer width loss. Using computer interface manufacturing, the measured spacer width data is provided to a computer that performs the calculation and provides the further processing time or a recipe to the tool used for the spacer width adjustment operation. The spacer width adjustment operation may be wet processing in an SPM solution that oxidizes the spacers and an HF clean operation may be used to remove the oxidized portion and yield spacer widths within acceptable specification limits.
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: June 20, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yih-Song Chiu, Wen-Ting Tsai, Jao-Sheng Huang, Chen-Hsiang Leu
  • Patent number: 7056836
    Abstract: In a method for manufacturing a semiconductor device, a first silicon oxide film is formed on a semiconductor substrate. The first silicon oxide film is nitrided so that silicon oxynitride forms at an interface between the semiconductor substrate and the first silicon oxide film. The first silicon oxide film is removed from a portion of the semiconductor substrate using a chemical containing at least an ammonia-hydrogen peroxide solution so that the silicon oxynitride formed at the interface between the portion of the semiconductor substrate and the first silicon oxide film is completely removed. Thereafter, a second silicon oxide film is formed in the portion of the semiconductor substrate from which the first silicon oxide film and the silicon oxynitride have been removed.
    Type: Grant
    Filed: July 10, 2003
    Date of Patent: June 6, 2006
    Assignee: Seiko Instruments Inc.
    Inventor: Hitomi Watanabe
  • Patent number: 7056842
    Abstract: According to the invention, while performing plasma-enhanced chemical vapor deposition on a substrate by exposing the substrate in a vacuum to a flow of particles generated by a plasma, which particles react to form a passivation layer on the substrate, a grid is interposed between the plasma and the substrate, thereby reducing the flow of charged particles towards the substrate while conserving a flow of neutral particles. The grid is formed of metal wires that are crossed at a pitch that is less than two or three times the Debye length (?D) of the plasma used, at least at the beginning of deposition. The aging properties of semiconductor components made by such a method is thereby improved.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: June 6, 2006
    Assignee: Alcatel
    Inventors: Christophe Jany, Michel Puech
  • Patent number: 7056835
    Abstract: Methods are provided herein for treating substrate surfaces in preparation for subsequent nucleation-sensitive depositions (e.g., polysilicon or poly-SiGe) and adsorption-driven deposition (e.g. atomic layer deposition or ALD). Prior to depositing, the surface is treated with non-depositing plasma products. The treated surface more readily nucleates polysilicon and poly-SiGe (such as for a gate electrode), or more readily adsorbs ALD reactants (such as for a gate dielectric). The surface treatment provides surface moieties more readily susceptible to a subsequent deposition reaction, or more readily susceptible to further surface treatment prior to deposition. By changing the surface termination of the substrate with a low temperature radical treatment, subsequent deposition is advantageously facilitated without depositing a layer of any appreciable thickness and without significantly affecting the bulk properties of the underlying material.
    Type: Grant
    Filed: July 24, 2003
    Date of Patent: June 6, 2006
    Assignee: ASM America, Inc.
    Inventors: Christophe F. Pomarede, Jeff Roberts, Eric J. Shero