Silicon Oxide Formation Patents (Class 438/787)
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Patent number: 7973390Abstract: A modifier for lowering relative dielectric constant of a low dielectric constant film used in semiconductor devices, the modifier of the low dielectric constant film being characterized in that it contains as an effective component a silicon compound represented by formula (1) R3-nHnSiN3??(1) in which R is a C1-C4 alkyl group, and n is an integer from 0 to 3.Type: GrantFiled: July 11, 2007Date of Patent: July 5, 2011Assignee: Central Glass Company, LimitedInventors: Tsuyoshi Ogawa, Mitsuya Ohashi
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Publication number: 20110156128Abstract: The present invention provides a manufacturing method of a dielectric film which reduces a leak current value while suppressing the reduction of a relative permittivity, suppresses the reduction of a deposition rate caused by the reduction of a sputtering rate, and also provides excellent planar uniformity. A dielectric film manufacturing method according to an embodiment of the present invention is forms a dielectric film of a metal oxide mainly containing Al, Si, and O on a substrate, and comprises steps of forming the metal oxide having an amorphous structure in which a molar fraction between an Al element and a Si element, Si/(Si+Al), is 0<Si/(Si+Al)?0.1, and subjecting the metal oxide having the amorphous structure to annealing treatment at a temperature of 1000° C. or more to form the metal oxide including a crystalline phase.Type: ApplicationFiled: December 21, 2010Publication date: June 30, 2011Applicant: CANON ANELVA CORPORATIONInventors: Junko ONO, Naomu KITANO, Takashi NAKAGAWA
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Patent number: 7964516Abstract: A method for using a film formation apparatus includes, in order to inhibit metal contamination: performing a cleaning process using a cleaning gas on an inner wall of a process container and a surface of a holder with no productive target objects held thereon; and then, performing a coating process of forming a silicon nitride film by alternately supplying a silicon source gas and a nitriding gas to cover with the silicon nitride film the inner wall of the process container and the surface of the holder with no productive target objects held thereon.Type: GrantFiled: March 10, 2009Date of Patent: June 21, 2011Assignee: Tokyo Electron LimitedInventors: Mitsuhiro Okada, Yamato Tonegawa
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Patent number: 7960294Abstract: Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer on the substrate, wherein the barrier layer comprises silicon and carbon and has a dielectric constant less than 4, depositing a dielectric initiation layer adjacent the barrier layer, and depositing a first dielectric layer adjacent the dielectric initiation layer, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less.Type: GrantFiled: July 21, 2009Date of Patent: June 14, 2011Assignee: Applied Materials, Inc.Inventors: Francimar Campana Schmitt, Li-Qun Xia, Son Van Nguyen, Shankar Venkataraman
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Patent number: 7955948Abstract: A manufacturing method of a semiconductor device includes the steps of carrying a substrate in a processing chamber, bringing the processing chamber into a state at a first pressure by supplying a silicon compound gas which contains carbon and hydrogen into the processing chamber, forming a silicon oxide film on the substrate by irradiating a UV light to the silicon compound gas supplied into the processing chamber in the state kept at the first pressure, and decompression process to bring the processing chamber into a state at a second pressure lower than the first pressure. This makes it possible to form the dense silicon oxide film in the trench with high aspect ratio and small width.Type: GrantFiled: September 1, 2009Date of Patent: June 7, 2011Assignee: Hitachi Kokusai Electric Inc.Inventors: Naofumi Ohashi, Yuichi Wada, Nobuo Owada, Takeshi Taniguchi
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Patent number: 7951728Abstract: A method for selective oxidation of silicon containing materials in a semiconductor device is disclosed and claimed. In one aspect, a rapid thermal processing apparatus is used to selectively oxidize a substrate by in-situ steam generation at high pressure in a hydrogen rich atmosphere. Other materials, such as metals and barrier layers, in the substrate are not oxidized.Type: GrantFiled: September 24, 2007Date of Patent: May 31, 2011Assignee: Applied Materials, Inc.Inventors: Yoshitaka Yokota, Norman Tam, Balasubramanian Ramachandran, Martin John Ripley
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Publication number: 20110124204Abstract: A semiconductor device manufacturing method includes: forming a layer on a substrate by supplying source gas into a process vessel; changing the layer into an oxide layer by supplying gases containing oxygen and hydrogen into the process vessel heated and kept lower than atmospheric pressure; and forming an oxide film on the substrate by alternately repeating the forming of the layer and the changing of the layer while purging an inside of the process vessel therebetween. In the forming of the layer, the source gas is supplied toward the substrate through a nozzle at a side of the substrate, and inert or hydrogen-containing gas is supplied together with the source gas through the nozzle toward the substrate, such that the velocity of the source gas flowing parallel to the substrate is greater than the velocity of the inert gas flowing parallel to the substrate in the purging of the process vessel.Type: ApplicationFiled: November 19, 2010Publication date: May 26, 2011Applicant: Hitachi-Kokusai Electric Inc.Inventors: Yosuke Ota, Naonori Akae, Yushin Takasawa, Yoshiro Hirose
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Patent number: 7943531Abstract: A method of depositing a silicon oxide layer over a substrate includes providing a substrate to a deposition chamber. A first silicon-containing precursor, a second silicon-containing precursor and a NH3 plasma are reacted to form a silicon oxide layer. The first silicon-containing precursor includes at least one of Si—H bond and Si—Si bond. The second silicon-containing precursor includes at least one Si—N bond. The deposited silicon oxide layer is annealed.Type: GrantFiled: October 22, 2007Date of Patent: May 17, 2011Assignee: Applied Materials, Inc.Inventors: Srinivas D. Nemani, Abhijit Basu Mallick, Ellie Y. Yieh
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Patent number: 7932187Abstract: A semiconductor device has a first interlayer insulating film formed on a substrate, having a first interconnection buried therein, and having a depressed portion and an insulating barrier film formed on the first interlayer insulating film. A second interlayer insulating film is formed to fill in the depressed portion, cover the upper surface of the insulating barrier film, and have a second interconnection buried therein.Type: GrantFiled: February 10, 2009Date of Patent: April 26, 2011Assignee: Panasonic CorporationInventor: Kenji Kobayashi
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Patent number: 7932189Abstract: An electronic device can include a layer of discontinuous storage elements. A dielectric layer overlying the discontinuous storage elements can be substantially hydrogen-free. A process of forming the electronic device can include forming a layer including silicon over the discontinuous storage elements. In one embodiment, the process includes oxidizing at least substantially all of the layer. In another embodiment, the process includes forming the layer using a substantially hydrogen-free silicon precursor material and oxidizing at least substantially all of the layer.Type: GrantFiled: January 26, 2007Date of Patent: April 26, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Tushar P. Merchant, Chun-Li Liu, Ramachandran Muralidhar, Marius K. Orlowski, Rajesh A. Rao, Matthew Stoker
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Patent number: 7932102Abstract: A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.Type: GrantFiled: December 18, 2008Date of Patent: April 26, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Yoon-Jong Song, Byung-Seo Kim, Kyung-Chang Ryoo
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Patent number: 7928019Abstract: Embodiments of the present disclosure include semiconductor processing methods and systems. One method includes forming a material layer on a semiconductor substrate by exposing a deposition surface of the substrate to at least a first and a second reactant sequentially introduced into a reaction chamber having an associated process temperature. The method includes removing residual first reactant from the chamber after introduction of the first reactant, removing residual second reactant from the chamber after introduction of the second reactant, and establishing a temperature differential substantially between an edge of the substrate and a center of the substrate via a purge process.Type: GrantFiled: August 10, 2007Date of Patent: April 19, 2011Assignee: Micron Technology, Inc.Inventor: Shyam Surthi
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Patent number: 7928020Abstract: A method for fabricating a nitrogen-containing dielectric layer and semiconductor device including the dielectric layer in which a silicon oxide layer is formed on a substrate, such that an interface region resides adjacent to substrate and a surface region resides opposite the interface region. Nitrogen is introduced into the silicon oxide layer by applying a nitrogen plasma. After applying nitrogen plasma, the silicon oxide layer is annealed. The processes of introducing nitrogen into the silicon oxide layer and annealing the silicon oxide layer are repeated to create a bi-modal nitrogen concentration profile in the silicon oxide layer. In the silicon oxide layer, the peak nitrogen concentrations are situated away from the interface region and at least one of the peak nitrogen concentrations is situated in proximity to the surface region. A method for fabricating a semiconductor device is incorporating the nitrogen-containing silicon oxide layers also disclosed.Type: GrantFiled: September 27, 2007Date of Patent: April 19, 2011Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Jinping Liu, Ben Ong, Zhengquan Zhang, Jae Gon Lee, Lydia Wong, Bin Yang, K. H. Alex See, Meisheng Zhou, Liang Choo Hsia
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Publication number: 20110084367Abstract: A method of producing an epitaxial wafer, comprising: implanting oxygen ions from a surface of a silicon wafer, thereby forming an ion implanted layer in a surface layer of the silicon wafer; after forming the ion implanted layer, implanting boron ions from the surface of the silicon wafer to the whole area in the ion implanted layer; performing heat treatment of the silicon wafer after implanting boron ions, thereby forming a thinning-stopper layer including a mixture of silicon particles, silicon oxides, and boron, and forming an active layer in the silicon wafer on the surface side of the thinning-stopper layer; and forming an epitaxial layer on the surface of the silicon wafer after the heat treatment.Type: ApplicationFiled: October 5, 2010Publication date: April 14, 2011Applicant: SUMCO CORPORATIONInventors: Hideki NISHIHATA, Yoshihisa NONOGAKI, Akihiko ENDO
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Patent number: 7923383Abstract: This invention relates to a method of treating a semiconductor wafer and in particular, but not exclusively, to planarisation. The method consists of depositing a liquid short-chain polymer formed from a silicon containing bas or vapour. Subsequently water and OH are removed and the layer is stabilised.Type: GrantFiled: March 28, 2003Date of Patent: April 12, 2011Assignee: Tokyo Electron LimitedInventors: Knut Beekmann, Guy Patrick Tucker
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Patent number: 7923384Abstract: In a formation method of a porous insulating film by supplying at least organosiloxane and an inert gas to a reaction chamber and forming an insulating film by a plasma vapor deposition method, a partial pressure of the organosiloxane in the reaction chamber is changed by varying a volume ratio of the organosiloxane and the inert gas to be supplied during deposition. Thus, the dielectric constant of the insulating film in the semiconductor device is reduced while the adhesion of the insulating film with other materials is improved. It is desirable that the organosiloxane be cyclic organosiloxane including at least silicon, oxygen, carbon, and hydrogen, and that the total pressure of the reaction chamber be constant during deposition.Type: GrantFiled: November 24, 2006Date of Patent: April 12, 2011Assignee: NEC CorporationInventors: Munehiro Tada, Naoya Furutake, Tsuneo Takeuchi, Yoshihiro Hayashi
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Patent number: 7923376Abstract: The present invention provides high deposition rate PECVD methods for depositing TEOS films. The methods significantly reduce the number of particles in the TEOS films, thereby eliminating or minimizing defects. According to various embodiments, the methods involve adding a relatively small amount of helium gas to the process gas. The addition of helium significantly reduces the number of defects in the film, particularly for high deposition rate processes.Type: GrantFiled: March 30, 2006Date of Patent: April 12, 2011Assignee: Novellus Systems, Inc.Inventors: N. Arul Dhas, Jon Henri
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Publication number: 20110081786Abstract: Methods for reducing and inhibiting defect formation on silicon dioxide formed by atomic layer deposition (ALD) are disclosed. Defect reduction is accomplished by performing processing on the silicon dioxide subsequent to deposition by ALD. The post-deposition processing may include at least one of a pump/purge cycle and a water exposure cycle performed after formation of the silicon dioxide on a substrate.Type: ApplicationFiled: December 10, 2010Publication date: April 7, 2011Applicant: MICRON TECHNOLOGY, INC.Inventor: Shyam Surthi
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Publication number: 20110074013Abstract: A silicon compound gas, an oxidizing gas, and a rare gas are supplied into a chamber (2) of a plasma processing apparatus (1). A microwave is supplied into the chamber (2), and a silicon oxide film is formed on a target substrate with plasma generated by the microwave. A partial pressure ratio of the rare gas is 10% or more of a total gas pressure of the silicon compound gas, the oxidizing gas, and the rare gas, and an effective flow ratio of the silicon compound gas and the oxidizing gas (oxidizing gas/silicon compound gas) is not less than 3 but not more than 11.Type: ApplicationFiled: May 11, 2009Publication date: March 31, 2011Applicant: TOKYO ELECTRON LIMITEDInventors: Hirokazu Ueda, Yoshinobu Tanaka, Yusuke Ohsawa, Toshihisa Nozawa, Takaaki Matsuoka
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Patent number: 7915179Abstract: In a method for forming an insulating film by performing plasma nitriding process to an oxide film on a substrate and then by annealing the substrate in a process chamber (51), the substrate is annealed under a low pressure of 667 Pa or lower. The annealing is performed for 5 or 45 seconds. The plasma nitriding process is performed by microwave plasma by using a planar antenna whereupon a multitude of slot holes are formed.Type: GrantFiled: November 2, 2005Date of Patent: March 29, 2011Assignee: Tokyo Electron LimitedInventors: Yoshihiro Sato, Tomoe Nakayama, Hiroshi Kobayashi, Yoshinori Osaki, Tetsuro Takahashi
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Patent number: 7915152Abstract: A boule formed by high rate vapor phase growth of Group III-V nitride boules (ingots) on native nitride seeds, from which wafers may be derived for fabrication of microelectronic device structures. The boule is of microelectronic device quality, e.g., having a transverse dimension greater than 1 centimeter, a length greater than 1 millimeter, and a top surface defect density of less than 107 defects cm?2. The Group III-V nitride boule may be formed by growing a Group III-V nitride material on a corresponding native Group III-V nitride seed crystal by vapor phase epitaxy at a growth rate above 20 micrometers per hour. Nuclear transmutation doping may be applied to an (Al,Ga,In)N article comprises a boule, wafer, or epitaxial layer.Type: GrantFiled: February 2, 2010Date of Patent: March 29, 2011Assignee: Cree, Inc.Inventors: Robert P. Vaudo, Jeffrey S. Flynn, George R. Brandes, Joan M. Redwing, Michael A. Tischler
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Patent number: 7915159Abstract: A treating agent composition for increasing the hydrophobicity of an organosilicate glass dielectric film when applied to said film. It includes a component capable of alkylating or arylating silanol moieties of the organosilicate glass dielectric film via silylation, and an activating agent which may be an acid, a base, an onium compound, a dehydrating agent, and combinations thereof, and a solvent or mixture of a main solvent and a co-solvent.Type: GrantFiled: August 12, 2005Date of Patent: March 29, 2011Assignee: Honeywell International Inc.Inventors: Anil S. Bhanap, Boris A. Korolev, Roger Y. Leung, Beth C. Munoz
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Patent number: 7910419Abstract: A method for making a transistor with self-aligned gate and ground plane includes forming a stack, on one face of a semi-conductor substrate, the stack including an organometallic layer and a dielectric layer. The method also includes exposing a part of the organometallic layer, a portion of the organometallic layer different to the exposed part being protected from the electron beams by a mask, the shape and the dimensions of a section, in a plane parallel to the face of the substrate, of the gate of the transistor being substantially equal to the shape and to the dimensions of a section of the organometallic portion in said plane. The method also includes removing the exposed part, and forming dielectric portions in empty spaces formed by the removal of the exposed part of the organometallic layer, around the organometallic portion.Type: GrantFiled: June 11, 2009Date of Patent: March 22, 2011Assignee: Commissariat a l'Energie AtomiqueInventors: Claire Fenouillet-Beranger, Philippe Coronel
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Patent number: 7902084Abstract: Embodiments disclosed herein pertain to silicon dioxide deposition methods using at least ozone and tetraethylorthosilicate (TEOS) as deposition precursors. In one embodiment, a silicon dioxide deposition method using at least ozone and TEOS as deposition precursors includes flowing precursors comprising ozone and TEOS to a substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material having an outer surface onto the substrate. The outer surface is treated effective to one of add hydroxyl to or remove hydroxyl from the outer surface in comparison to any hydroxyl presence on the outer surface prior to said treating. After the treating, precursors comprising ozone and TEOS are flowed to the substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material onto the treated outer surface of the substrate. Other embodiments are contemplated.Type: GrantFiled: July 5, 2007Date of Patent: March 8, 2011Assignee: Micron Technology, Inc.Inventors: John Smythe, Gurtej S. Sandhu
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Patent number: 7902088Abstract: A method is provided for fabricating a high quantum efficiency silicon (Si) nanoparticle embedded SiOXNY film for luminescence (electroluminescence—EL and photoluminescence—PL) applications. The method provides a bottom electrode, and deposits a Si nanoparticle embedded non-stoichiometric SiOXNY film, where (X+Y<2 and Y>0), overlying the bottom electrode. The Si nanoparticle embedded SiOXNY film is annealed. The annealed Si nanoparticle embedded SiOXNY film has an extinction coefficient (k) of less than about 0.001 as measured at 632 nanometers (nm), and a PL quantum efficiency (PLQE) of greater than 20%.Type: GrantFiled: October 11, 2008Date of Patent: March 8, 2011Assignee: Sharp Laboratories of America, Inc.Inventors: Pooran Chandra Joshi, Jiandong Huang, Apostolos T. Voutsas
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Patent number: 7897521Abstract: Disclosed is a low dielectric constant plasma polymerized thin film using linear organic/inorganic precursors and a method of manufacturing the low dielectric constant plasma polymerized thin film through plasma enhanced chemical vapor deposition and annealing using an RTA apparatus. The low dielectric constant plasma polymerized thin film is effective for the preparation of multilayered metal thin films having a thin film structure with very high thermal stability, a low dielectric constant, and superior mechanical properties.Type: GrantFiled: August 14, 2008Date of Patent: March 1, 2011Assignee: Sungkyunkwan University Foundation For Corporate CollaborationInventors: Donggeun Jung, Sungwoo Lee, Jihyung Woo
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Patent number: 7893538Abstract: An insulating-film-forming composition for a semiconductor device comprising an organic silica sol with a carbon atom content of 11 to 17 atom % and an organic solvent is disclosed. The organic silica sol comprises a hydrolysis-condensation product P1 and a hydrolysis-condensation product P2. The hydrolysis-condensation product P1 is obtained by hydrolyzing and condensing (A) a silane monomer comprising a hydrolyzable group and (B) a polycarbosilane comprising a hydrolyzable group in the presence of (C) a basic catalyst, and the hydrolysis-condensation product P2 is obtained by hydrolyzing and condensing (D) a silane monomer comprising a hydrolyzable group.Type: GrantFiled: January 31, 2007Date of Patent: February 22, 2011Assignee: JSR CorporationInventors: Hisashi Nakagawa, Tatsuya Yamanaka, Masahiro Akiyama, Terukazu Kokubo, Youhei Nobe
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Patent number: 7888233Abstract: Methods of this invention relate to filling gaps on substrates with a solid dielectric material by forming a flowable film in the gap. The flowable film provides consistent, void-free gap fill. The film is then converted to a solid dielectric material. In this manner gaps on the substrate are filled with a solid dielectric material. According to various embodiments, the methods involve reacting a dielectric precursor with an oxidant to form the dielectric material. In certain embodiments, the dielectric precursor condenses and subsequently reacts with the oxidant to form dielectric material. In certain embodiments, vapor phase reactants react to form a condensed flowable film.Type: GrantFiled: March 25, 2009Date of Patent: February 15, 2011Assignee: Novellus Systems, Inc.Inventors: Vishal Gauri, Raashina Humayun, Chi-I Lang, Judy H. Huang, Michael Barnes, Sunil Shanker
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Publication number: 20110034039Abstract: A method of forming a silicon oxide layer is described. The method may include the steps of mixing a carbon-free silicon-and-nitrogen containing precursor with a radical precursor, and depositing a silicon-and-nitrogen containing layer on a substrate. The silicon-and-nitrogen containing layer is then converted to the silicon oxide layer.Type: ApplicationFiled: July 21, 2010Publication date: February 10, 2011Applicant: Applied Materials, Inc.Inventors: Jingmei Liang, Nitin K. Ingle, Shankar Venkataraman
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Patent number: 7879737Abstract: Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPOX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPOX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.Type: GrantFiled: May 24, 2010Date of Patent: February 1, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Woong-Hee Sohn, Gil-Heyun Choi, Byung-Hee Kim, Byung-Hak Lee, Tae-Ho Cha, Hee-Sook Park, Jae-Hwa Park, Geum-Jung Seong
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Publication number: 20110021037Abstract: The present invention relates to compositions, which are useful for the generation of patterned or structured SiO2-layers or of SiO2-lines during the manufacturing process of semiconductor devices, and which are suitable for the application in inkjet operations. The present invention also relates to a modified process of manufacturing semiconductor devices taking advantage of these new compositions.Type: ApplicationFiled: March 2, 2009Publication date: January 27, 2011Applicant: MERCK PATENT GESELLSCHAFTInventors: Werner Stockum, Ingo Koehler, Arjan Meijer, Paul Craig Brookes, Katie Patterson, Mark James
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Patent number: 7871940Abstract: A silicon nitride thin film formation apparatus is provided for stationary and moving substrates and a process for forming such films. The process provides high uniformity of film thickness and film properties as well as a high deposition rate. The film properties are adequate for application as an antireflection layer or passivation layer in solar cell devices or as dielectric layer in thin film transistors. The apparatus includes a number of metal filaments. In the space within the formation apparatus opposite to the substrate with respect to the filaments, a gas dosage system is arranged at a predetermined distance of the filaments. The film formation apparatus for stationary substrates also contains a shutter to control the starting and ending conditions for film formation and to control the film thickness.Type: GrantFiled: March 3, 2005Date of Patent: January 18, 2011Assignee: Universiteit Utrecht Holding B.V.Inventors: Rudolf Emmanuel Isidore Schropp, Catharina Henriette Maria Van Der Werf, Bernd Stannowski
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Publication number: 20110008972Abstract: Methods of forming a silicon dioxide material by an atomic layer deposition process and methods of preparing a substrate for the formation of a silicon dioxide material by an atomic layer deposition process are provided. In at least one such method, prior to forming the silicon oxide material, at least one pump and exhaust cycle is conducted. Such a pump and exhaust cycle includes at least one pump step, whereby a purge gas is pumped into the reaction chamber, and at least one exhaust step, whereby the purge gas is exhausted from a reaction chamber. The silicon oxide material is then formed on a surface of the substrate.Type: ApplicationFiled: July 13, 2009Publication date: January 13, 2011Inventors: Daniel Damjanovic, Shyam Surthi
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Patent number: 7867920Abstract: There is provided a method for modifying a high-k dielectric thin film provided on the surface of an object using a metal organic compound material. The method includes a preparation process for providing the object with the high-k dielectric thin film formed on the surface thereof, and a modification process for applying UV rays to the highly dielectric thin film in an inert gas atmosphere while maintaining the object at a predetermined temperature to modify the high-k dielectric thin film. According to the above constitution, the carbon component can be eliminated from the high-k dielectric thin film, and the whole material can be thermally shrunk to improve the density, whereby the occurrence of defects can be prevented and the film density can be improved to enhance the specific permittivity and thus to provide a high level of electric properties.Type: GrantFiled: November 22, 2006Date of Patent: January 11, 2011Assignee: Tokyo Electron LimitedInventors: Kazuyoshi Yamazaki, Shintaro Aoyama, Koji Akiyama
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Patent number: 7867922Abstract: The present invention is a film forming method for an SiOCH film, comprising a unit-film-forming step including: a deposition step of depositing an SiOCH film element by using an organic silicon compound as a raw material and by using a plasma CVD method; and a hydrogen plasma processing step of providing a hydrogen plasma process to the deposited SiOCH film element, wherein the unit-film-forming step is repeated several times so as to form an SiOCH film on a substrate.Type: GrantFiled: December 5, 2006Date of Patent: January 11, 2011Assignee: Tokyo Electron LimitedInventors: Shinji Ide, Yasuhiro Oshima, Yusaku Kashiwagi
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Patent number: 7867918Abstract: A semiconductor topography is provided which includes a silicon dioxide layer with a thickness equal to or less than approximately 10 angstroms and a silicon nitride layer arranged upon the silicon dioxide layer. In addition, a method is provided which includes growing an oxide film upon a semiconductor topography in the presence of an ozonated substance and depositing a silicon nitride film upon the oxide film. In some embodiments, the method may include growing the oxide film in a first chamber at a first temperature and transferring the semiconductor topography from the first chamber to a second chamber while the semiconductor topography is exposed to a substantially similar temperature as the first temperature. In either embodiment, the method may be used to form a semiconductor device including an oxide-nitride gate dielectric having an electrical equivalent oxide gate dieletric thickness of less than approximately 20 angstroms.Type: GrantFiled: March 11, 2008Date of Patent: January 11, 2011Assignee: Cypress Semiconductor CorporationInventor: Krishnaswamy Ramkumar
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Patent number: 7867921Abstract: A processing chamber is seasoned by providing a flow of season precursors to the processing chamber. A high-density plasma is formed from the season precursors by applying at least 7500 W of source power distributed with greater than 70% of the source power at a top of the processing chamber. A season layer having a thickness of at least 5000 ? is deposited at one point using the high-density plasma. Each of multiple substrates is transferred sequentially into the processing chamber to perform a process that includes etching. The processing chamber is cleaned between sequential transfers of the substrates.Type: GrantFiled: September 4, 2008Date of Patent: January 11, 2011Assignee: Applied Materials, Inc.Inventors: Anchuan Wang, Young S. Lee, Manoj Vellaikal, Jason Thomas Bloking, Jin Ho Jeon, Hemant P. Mungekar
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Patent number: 7867923Abstract: A method of depositing a silicon and nitrogen containing film on a substrate. The method includes introducing silicon-containing precursor to a deposition chamber that contains the substrate, wherein the silicon-containing precursor comprises at least two silicon atoms. The method further includes generating at least one radical nitrogen precursor with a remote plasma system located outside the deposition chamber. Moreover, the method includes introducing the radical nitrogen precursor to the deposition chamber, wherein the radical nitrogen and silicon-containing precursors react and deposit the silicon and nitrogen containing film on the substrate. Furthermore, the method includes annealing the silicon and nitrogen containing film in a steam environment to form a silicon oxide film, wherein the steam environment includes water and acidic vapor.Type: GrantFiled: October 22, 2007Date of Patent: January 11, 2011Assignee: Applied Materials, Inc.Inventors: Abhijit Basu Mallick, Srinivas D. Nemani, Ellie Yieh
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Patent number: 7858531Abstract: A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising at least one transistor element. An etch stop layer is formed over the transistor element. A stressed first dielectric layer is formed over the etch stop layer. A protective layer adapted to reduce an intrusion of moisture into the first dielectric layer is formed over the first dielectric layer. At least one electrical connection to the transistor element is formed. At least a portion of the protective layer remains over the first dielectric layer after completion of the formation of the at least one electrical connection.Type: GrantFiled: January 22, 2008Date of Patent: December 28, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Ralf Richter, Joerg Hohage, Michael Finken, Jana Schlott
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Patent number: 7858535Abstract: Methods for reducing and inhibiting defect formation on silicon dioxide formed by atomic layer deposition (ALD) are disclosed. Defect reduction is accomplished by performing processing on the silicon dioxide subsequent to deposition by ALD. The post-deposition processing may include at least one of a pump/purge cycle and a water exposure cycle performed after formation of the silicon dioxide on a substrate.Type: GrantFiled: May 2, 2008Date of Patent: December 28, 2010Assignee: Micron Technology, Inc.Inventor: Shyam Surthi
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Patent number: 7858534Abstract: A semiconductor device manufacturing method comprises a process of forming a film on each of multiple substrates arrayed in a processing chamber by a thermal CVD method by supplying a film forming gas into the processing chamber while heating the interior of the processing chamber, wherein in the film forming process, a cycle is performed one time or multiple times with one cycle including a step of flowing the film forming gas from one end towards the other end along the substrate array direction, and a step of flowing the film forming gas from the other end towards the one end along the substrate array direction, without forming temperature gradient along the substrate array direction in the processing chamber.Type: GrantFiled: August 7, 2008Date of Patent: December 28, 2010Assignee: Hitachi Kokusai Electric Inc.Inventor: Kiyohiko Maeda
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Patent number: 7858536Abstract: A semiconductor device comprising a semiconductor substrate, a gate dielectrics formed on the semiconductor substrate and including a silicon oxide film containing a metallic element, the silicon oxide film containing the metallic element including a first region near a lower surface thereof, a second region near an upper surface thereof, and a third region between the first and second regions, the metallic element contained in the silicon oxide film having a density distribution in a thickness direction of the silicon oxide film, a peak of the density distribution existing in the third region, and an electrode formed on the gate dielectrics.Type: GrantFiled: September 20, 2007Date of Patent: December 28, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhiro Eguchi, Seiji Inumiya, Yoshitaka Tsunashima
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Patent number: 7855154Abstract: A cap layer that enables a photopatternable, spin-on material to be used in the formation of semiconductor device structures at wavelengths that were previously unusable. The photopatternable, spin-on material is applied as a layer to a semiconductor substrate. The cap layer and a photoresist layer are each formed over the photopatternable layer. The cap layer absorbs or reflects radiation and protects the photopatternable layer from a first wavelength of radiation used in patterning the photoresist layer. The photopatternable, spin-on material is convertible to a silicon dioxide-based material upon exposure to a second wavelength of radiation.Type: GrantFiled: March 29, 2006Date of Patent: December 21, 2010Assignee: Micron Technology, Inc.Inventors: Weimin Li, Gurtej S. Sandhu
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Patent number: 7851385Abstract: The present invention generally provides apparatus and method for processing a semiconductor substrate. Particularly, embodiments of the present invention relate to a method and apparatus for forming semiconductor devices having a conformal silicon oxide layer formed at low temperature. One embodiment of the present invention provides a method for forming a semiconductor gate structure. The method comprises forming a gate stack on a semiconductor substrate, forming a conformal silicon oxide layer on the semiconductor substrate using a low temperature cyclic method, and forming a spacer layer on the conformal silicon oxide layer.Type: GrantFiled: September 30, 2008Date of Patent: December 14, 2010Assignee: Applied Materials, Inc.Inventors: Matthew Spuller, Melody Agustin, Meiyee (Maggie Le) Shek, Li-Qun Xia, Reza Arghavani
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Patent number: 7842621Abstract: The total film thickness T1N of silicon oxynitride film and silicon oxide film remaining as its underlying layer is measured. A measurement target substrate is re-oxidized, and, after the re-oxidization, the total film thickness (T2N) of the silicon oxynitride film, silicon oxide film and silicon oxide film resulting from the re-oxidization on the target substrate is measured. Separately, a reference substrate provided with silicon oxide film is re-oxidized, and, after the re-oxidization, the total film thickness T2 of the silicon oxide film and silicon oxide film resulting from the re-oxidization on the reference substrate is measured. Re-oxidization rate reduction ratio RORR of the measurement target substrate is calculated by the following formula (1) from the values of total film thicknesses T1N, T2N and T2. The nitrogen concentration of the silicon oxynitride film of the target substrate is determined from the calculated re-oxidization rate reduction ratio RORR. RORR (%)={(T2?T2N)/(T2?T1N)}×100 (1).Type: GrantFiled: May 17, 2007Date of Patent: November 30, 2010Assignee: Tokyo Electron LimitedInventors: Jiro Katsuki, Tetsuro Takahashi, Shuuichi Ishizuka
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Patent number: 7838442Abstract: A method for producing a solar cell including the steps of forming a p-type microcrystalline silicon oxide layer on a glass substrate using a PECVD method and raw gases comprising Silane gas, Diborane gas, Hydrogen gas and Carbon Dioxide gas. The method may employ a frequency of between about 13.56-60 MHz. The PECVD method may be performed at a power density of between about 10-40 mW/cm2 and a pressure of between about 0.5-2 Torr, and with a ratio of Carbon Dioxide to Silane of between about 0.10-0.24; a ratio of Diborane to Silane of 0.10 or less, and a ratio of Silane to Hydrogen of 0.01 or less. A tandem solar cell structure may be formed by forming top and bottom layers by the method described above, and placing the top layer over the bottom layer.Type: GrantFiled: October 8, 2008Date of Patent: November 23, 2010Assignee: National Science and Technology Development AgencyInventors: Porponth Sichanugrist, Nirut Pingate, Decha Yotsaksri
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Patent number: 7825038Abstract: Methods of depositing a silicon oxide layer on a substrate are described. The methods may include the steps of providing a substrate to a deposition chamber, generating an atomic oxygen precursor outside the deposition chamber, and introducing the atomic oxygen precursor into the chamber. The methods may also include introducing a silicon precursor to the deposition chamber, where the silicon precursor and the atomic oxygen precursor are first mixed in the chamber. The silicon precursor and the atomic oxygen precursor react to form the silicon oxide layer on the substrate, and the deposited silicon oxide layer may be annealed. Systems to deposit a silicon oxide layer on a substrate are also described.Type: GrantFiled: May 29, 2007Date of Patent: November 2, 2010Assignee: Applied Materials, Inc.Inventors: Nitin K. Ingle, Zheng Yuan, Paul Gee, Kedar Sapre
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Patent number: 7820482Abstract: A method for producing an electronic component with an electronic circuit and electrical contacts, disposed at least on a first surface of the electronic component, for the electrical bonding of the electronic circuit includes at least one flexible elevation of an insulating material disposed on the first surface, at least one electrical contact disposed on the flexible elevation, and a conduction path disposed on the surface or in the interior of the flexible elevation between the electrical contact and the electronic circuit.Type: GrantFiled: May 6, 2005Date of Patent: October 26, 2010Assignee: Qimonda AGInventors: Harry Hedler, Alfred Haimerl
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Publication number: 20100267248Abstract: Methods and apparatus for post treating an oxide layer on a semiconductor substrate are disclosed. In one or more embodiments, the oxide layer is formed by thermal oxidation or plasma oxidation and treated with a plasma comprising helium. The helium-containing plasma may also include hydrogen, neon, argon and combinations thereof. In one or more embodiments, a SiO2 oxide layer is formed on a silicon substrate and treated with a plasma to improve the interface between the silicon substrate and the SiO2 oxide layer.Type: ApplicationFiled: April 19, 2010Publication date: October 21, 2010Applicant: Applied Materials, Inc.Inventors: Kai Ma, Christopher S. Olsen, Yoshitaka Yokota
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Patent number: 7816272Abstract: A process of cleaning a semiconductor manufacturing system, and a method of manufacturing a semiconductor device. The cleaning process includes, for example, positioning a ceramic cover on the electrostatic chuck in tight contact with the chuck, and feeding a fluoride-based cleaning gas into a chamber. After the cleaning process, a process of forming a semiconductor film (deposition process) is performed. It is possible to prevent fluorine degasification from a substrate-supporting electrode (electrostatic chuck) during the deposition process. A semiconductor film can be formed without causing a temperature drop near the substrate. This prevents irregular film thickness, defective etching, film flaking, etc.Type: GrantFiled: March 31, 2009Date of Patent: October 19, 2010Assignee: Oki Electric Industry Co., Ltd.Inventor: Hiroomi Tsutae