Radiation Or Energy Treatment Modifying Properties Of Semiconductor Region Of Substrate (e.g., Thermal, Corpuscular, Electromagnetic, Etc.) Patents (Class 438/795)
  • Patent number: 8293661
    Abstract: One embodiment of the present invention is to achieve high mobility in a device using an oxide semiconductor and provide a highly reliable display device. An oxide semiconductor layer including a crystal region in which c-axis is aligned in a direction substantially perpendicular to a surface is formed and an oxide insulating layer is formed over and in contact with the oxide semiconductor layer. Oxygen is supplied to the oxide semiconductor layer by third heat treatment. A nitride insulating layer containing hydrogen is formed over the oxide insulating layer and fourth heat treatment is performed, so that hydrogen is supplied at least to an interface between the oxide semiconductor layer and the oxide insulating layer.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: October 23, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8293563
    Abstract: Disclosed herein is a method for making a semiconductor device including the steps of: forming a light-receiving portion for carrying out photoelectric conversion in a semiconductor substrate; forming an insulating film to cover a light-receiving side of the semiconductor substrate; forming a metallic light-shielding film to partly cover the insulating film in correspondence to the light-receiving portion; and heating the metallic light-shielding film by irradiation of the metallic light-shielding film with a microwave to permit selective annealing of a laminated portion with the metallic light-shielding film in the insulating film.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: October 23, 2012
    Assignee: Sony Corporation
    Inventor: Susumu Hiyama
  • Patent number: 8293646
    Abstract: A high quality interface is formed at a low oxygen-carbon density between a substrate and a thin film while preventing heat damage on the substrate and increase of thermal budget. This method includes a step of loading a wafer into a reaction furnace, a step of pretreating the wafer in the reaction furnace, a step of performing a main processing of the pretreated wafer in the reaction furnace, and a step of unloading the wafer from the reaction furnace after the main processing. Hydrogen gas is continuously supplied to the reaction furnace in the period from the end of the pretreating step to the start of the main processing and at least during vacuum-exhausting an interior of the reaction furnace.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: October 23, 2012
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Takashi Ozaki, Osamu Kasahara, Takaaki Noda, Kiyohiko Maeda, Atsushi Moriya, Minoru Sakamoto
  • Patent number: 8287649
    Abstract: The present invention is a vertical boat for heat treatment having an auxiliary supporting member removably attached to each of supporting parts of a boat body, the auxiliary supporting member on which a substrate to be treated is to be placed, in which the auxiliary supporting member has a guiding member attached to the supporting part and a substrate supporting plate on which the substrate to be treated is to be placed, a hole is formed on an upper surface of the guiding member, the substrate supporting plate is inserted and fitted into the hole of the guiding member so as to be fixed, a height position of a placing surface for the substrate to be treated is higher than a height position of the upper surface of the guiding member, the substrate supporting plate is composed of silicon carbide and the guiding member is composed of quartz.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: October 16, 2012
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Takeshi Kobayashi
  • Patent number: 8288826
    Abstract: A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: October 16, 2012
    Assignee: International Business Machines Corporation
    Inventors: Anthony I. Chou, Toshiharu Furukawa, Wilfried Haensch, Zhibin Ren, Dinkar V. Singh, Jeffrey W. Sleight
  • Patent number: 8288259
    Abstract: With the evacuation of an interior of a vacuum chamber halted and with gas supply into the vacuum chamber halted, in a state that a mixed gas of helium gas and diborane gas is sealed in the vacuum chamber, a plasma is generated in a vacuum vessel and simultaneously a high-frequency power is supplied to a sample electrode. By the high-frequency power supplied to the sample electrode, boron is introduced to a proximity to a substrate surface.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: October 16, 2012
    Assignee: Panasonic Corporation
    Inventors: Tomohiro Okumura, Ichiro Nakayama, Satoshi Maeshima, Bunji Mizuno, Yuichiro Sasaki
  • Publication number: 20120258605
    Abstract: A device is intended for a laser lift-off method to sever at least one layer from a carrier. The device includes a laser that generates pulsed laser radiation and at least one beam splitter. The laser radiation is divided into at least two partial beams by the at least one beam splitter. The partial beams are superimposed in an irradiation plane, the irradiation plane being provided such that a major side of the carrier remote from the layer is arranged therein. At the irradiation plane, an angle (?) between the at least two partial beams is at least 1.0°.
    Type: Application
    Filed: October 21, 2010
    Publication date: October 11, 2012
    Applicant: OSRAM Opto Semiconductors GmbH
    Inventor: Ralph Wagner
  • Patent number: 8283260
    Abstract: A method for preparing an interlayer dielectric to minimize damage to the interlayer's dielectric properties, the method comprising the steps of: depositing a layer of a silicon-containing dielectric material onto a substrate, wherein the layer has a first dielectric constant and wherein the layer has at least one surface; providing an etched pattern in the layer by a method that includes at least one etch process and exposure to a wet chemical composition to provide an etched layer, wherein the etched layer has a second dielectric constant, and wherein the wet chemical composition contributes from 0 to 40% of the second dielectric constant; contacting the at least one surface of the layer with a silicon-containing fluid; optionally removing a first portion of the silicon-containing fluid such that a second portion of the silicon-containing fluid remains in contact with the at least one surface of the layer; and exposing the at least one surface of the layer to UV radiation and thermal energy, wherein the lay
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: October 9, 2012
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Scott Jeffrey Weigel, Mark Leonard O'Neill, Mary Kathryn Haas, Laura M. Matz, Glenn Michael Mitchell, Aiping Wu, Raymond Nicholas Vrtis, John Giles Langan
  • Patent number: 8283203
    Abstract: Some embodiments include methods in which microwave radiation is used to activate dopant and/or increase crystallinity of semiconductor material during formation of a semiconductor construction. In some embodiments, the microwave radiation has a frequency of about 5.8 gigahertz, and a temperature of the semiconductor construction does not exceed about 500° C. during the exposure to the microwave radiation.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: October 9, 2012
    Assignee: Micron Technology, Inc.
    Inventors: John Smythe, Bhaskar Srinivasan, Ming Zhang
  • Publication number: 20120252229
    Abstract: An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly linear lamps for emitting light energy onto a wafer. The linear lamps can be placed in various configurations. In accordance with the present invention, tuning devices which are used to adjust the overall irradiance distribution of the light energy sources are included in the heating device. The tuning devices can be, for instance, are lamps or lasers.
    Type: Application
    Filed: June 15, 2012
    Publication date: October 4, 2012
    Applicant: MATTSON TECHNOLOGY, INC.
    Inventor: Paul Janis Timans
  • Publication number: 20120248550
    Abstract: The embodiments of methods and structures disclosed herein provide mechanisms of performing doping an inter-level dielectric film, ILD0, surrounding the gate structures with a dopant to reduce its etch rates during the processes of removing dummy gate electrode layer and/or gate dielectric layer for replacement gate technologies. The ILD0 film may be doped with a plasma doping process (PLAD) or an ion beam process. Post doping anneal is optional.
    Type: Application
    Filed: March 31, 2011
    Publication date: October 4, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lien HUANG, Chia-Pin LIN, Sheng-Hsiung WANG, Fan-Yi HSU, Chun-Liang TAI
  • Publication number: 20120244722
    Abstract: A selective crystallization method includes placing a first substrate including first crystallization regions on a second substrate including second crystallization regions such that the first crystallization regions and the second crystallization regions are arranged alternately, and crystallizing the alternately-arranged first crystallization regions and the second crystallization regions with a laser beam. A laser crystallization apparatus can be used in the selective crystallization method.
    Type: Application
    Filed: February 10, 2012
    Publication date: September 27, 2012
    Applicant: SAMSUNG MOBILE DISPLAY CO., LTD.
    Inventors: Do-Young Kim, June-Woo Lee, Won-Kyu Lee
  • Publication number: 20120244723
    Abstract: Embodiments of the invention relate to methods and apparatus for laser drilling holes in a silicon substrate during the fabrication of back contact solar cells, such as emitter-wrap-through (EWT) solar cells. In one embodiment, the method and apparatus use a short focal length flat field lens and a dynamic scanning technique to accomplish single pulse drilling in the silicon substrate. The method and apparatus result in increased speed and quality of holes in an EWT solar cell substrate as compared to conventional apparatus and processes.
    Type: Application
    Filed: September 17, 2010
    Publication date: September 27, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Jeff M. Franklin, James M. Gee
  • Publication number: 20120238111
    Abstract: A thermal processing apparatus and method in which a first laser source, for example, a CO2 emitting at 10.6 ?m is focused onto a silicon wafer as a line beam and a second laser source, for example, a GaAs laser bar emitting at 808 nm is focused onto the wafer as a larger beam surrounding the line beam. The two beams are scanned in synchronism in the direction of the narrow dimension of the line beam to create a narrow heating pulse from the line beam when activated by the larger beam. The energy of GaAs radiation is greater than the silicon bandgap energy and creates free carriers. The energy of the CO2 radiation is less than the silicon bandgap energy so silicon is otherwise transparent to it, but the long wavelength radiation is absorbed by the free carriers.
    Type: Application
    Filed: May 31, 2012
    Publication date: September 20, 2012
    Inventors: Dean Jennings, Haifan Liang, Mark Yam, Vijay Parihar, Abhilash J. Mayur, Aaron Hunter, Bruce Adams, Joseph Michael Ranish
  • Publication number: 20120238110
    Abstract: The first flash irradiation is performed on a semiconductor wafer preheated to 500° C. to heat a front surface of the semiconductor wafer. Thereafter, the second flash irradiation is performed to reheat the front surface of the semiconductor wafer before the temperature of the front surface of the semiconductor wafer becomes equal to the temperature of a back surface of the semiconductor wafer. Thus, the second flash irradiation is performed before the temperature of the front surface of the semiconductor wafer falls. Even if less energy is consumable by the second flash irradiation, the efficiency of heating of the front surface of the semiconductor wafer resulting from each iteration of the flash irradiation is improved.
    Type: Application
    Filed: February 6, 2012
    Publication date: September 20, 2012
    Inventor: Kenichi YOKOUCHI
  • Patent number: 8268656
    Abstract: An optical device wafer processing method including a protective plate attaching step of attaching a transparent protective plate through a double-sided adhesive tape to the front side of a sapphire substrate constituting an optical device wafer, the double-sided adhesive tape being composed of a sheet capable of blocking ultraviolet radiation and adhesive layers formed on both sides of the sheet, wherein the adhesive force of each adhesive layer can be reduced by applying ultraviolet radiation; a sapphire substrate grinding step of grinding the back side of the sapphire substrate; a modified layer forming step of applying a laser beam to the sapphire substrate from the back side thereof to thereby form a modified layer in the sapphire substrate along each street; a protective plate removing step of removing the protective plate in the condition where the double-sided adhesive tape is left on the sapphire substrate; and a wafer dividing step of breaking the sapphire substrate along each street where the modif
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: September 18, 2012
    Assignee: Disco Corporation
    Inventor: Keiichi Kajiyama
  • Patent number: 8268733
    Abstract: A method of forming a device is presented. The method includes providing a wafer having an active surface and dividing the wafer into a plurality of portions. The wafer is selectively processed by localized heating of a first of the plurality of portions. The wafer is then repeatedly selectively processed by localized heating of a next of the plurality of portions until all plurality of portions have been selectively processed.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: September 18, 2012
    Assignees: Nanyang Technological University, National University of Singapore, Globalfoundries Singapore Pte. Ltd.
    Inventors: Dexter Tan, Chee Chong Lim, Sai Hooi Yeong, Chee Mang Ng
  • Publication number: 20120231614
    Abstract: The present invention related to a method for manufacturing a semiconductor, comprising steps of: providing a growing substrate; forming a semiconductor substrate on the growing substrate; forming a first structure with plural grooves and between the growing substrate and the semiconductor substrate; and changing the temperature of the growing substrate and the semiconductor substrate.
    Type: Application
    Filed: June 17, 2011
    Publication date: September 13, 2012
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: YewChung Sermon Wu, Bau-Ming Wang, Feng-Ching Hsiao
  • Publication number: 20120231636
    Abstract: A process for treating a semiconductor-on-insulator structure that has, in succession, a support substrate, a layer of an oxide or oxynitride of a semiconductor material, and a thin semiconductor layer of the semiconductor material. The process includes providing, on the surface of the thin layer, a mask defining exposed regions of the thin layer; providing a layer of nitride or oxynitride of the semiconductor material on the exposed regions of the thin layer; and applying a heat treatment causing at least some of the oxygen in the oxide or oxynitride layer to diffuse through the exposed regions. The nitride or oxynitride layer is provided at a thickness sufficient to provide a ratio of the rate of oxygen diffusion though the exposed regions to that through the regions covered with the mask that is greater than 2.
    Type: Application
    Filed: December 7, 2011
    Publication date: September 13, 2012
    Inventors: Didier Landru, Gregory Riou
  • Patent number: 8263483
    Abstract: A method including producing a monocrystalline layer is disclosed. A first lattice constant on a monocrystalline substrate has a second lattice constant at least in a near-surface region. The second lattice constant is different from the first lattice constant. Lattice matching atoms are implanted into the near-surface region. The near-surface region is momentarily melted. A layer is epitaxially deposited on the near-surface region that has solidified in monocrystalline fashion.
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: September 11, 2012
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Hans-Joachim Schulze
  • Publication number: 20120225568
    Abstract: An annealing method irradiates a target object, having a film formed on its surface, with a laser beam to perform an annealing process to the target object. The surface of the target object is irradiated with the laser beam obliquely at an incident angle that is determined to achieve an improved laser absorptance of the film.
    Type: Application
    Filed: February 28, 2012
    Publication date: September 6, 2012
    Applicant: Tokyo Electron Limited
    Inventors: Yusaku IZAWA, Junjun LIU, Hongyu YUE, Dorel TOMA
  • Patent number: 8261368
    Abstract: Devices for performing nanofabrication are provided which provide small volume reaction space and high reaction versatility. A device may include a reaction chamber adapted for nanoscale modification of a substrate and vacuum conditions; a scanning probe tip assembly enclosed within the reaction chamber; a first port coupled to the reaction chamber for delivering a gas; a second port coupled to the reaction chamber for applying a vacuum; and a substrate assembly insertedly mounted to the reaction chamber. The reaction chamber may include a body having one or more flexible walls and one or more supports to prevent the reaction chamber from collapsing under a vacuum. The device may further include an electrical conduit for coupling the tips of the scanning probe tip assembly to electrical components outside the reaction chamber. Also provided are apparatuses incorporating the devices and methods of using the devices and apparatuses.
    Type: Grant
    Filed: May 13, 2009
    Date of Patent: September 4, 2012
    Assignee: NanoInk, Inc.
    Inventors: John Edward Bussan, Michael R. Nelson, Joseph S. Fragala, Albert K. Henning, Jeffrey R. Rendlen
  • Publication number: 20120220140
    Abstract: Provided is a forming device and method making it possible to obtain a low-temperature polysilicon film in which the size of crystal grains fluctuates minimally, and is uniform. A mask has laser-light-blocking areas and laser-light-transmission areas arranged in the form of a grid such that the light-blocking areas and transmission areas are not adjacent to one another. Laser light is directed by the microlenses through the masks to planned channel-area-formation areas. The laser light transmitted by the transmission areas is directed onto an a-Si:H film, annealing and polycrystallzing the irradiated parts thereof. The mask is then removed, and when the entire planned channel-area-formation area is irradiated with laser light, the already-polycrystallized area, having a higher melting point, does not melt, while the area in an amorphous state melts and solidifies, leading to polycrystallization.
    Type: Application
    Filed: October 14, 2010
    Publication date: August 30, 2012
    Inventors: Koichi Kajiyama, Kuniyuki Hamano, Michinobu Mizumura
  • Patent number: 8252703
    Abstract: Methods of forming a roughened metal surface on a substrate are provided, along with structures comprising such roughened surfaces. In preferred embodiments roughened surfaces are formed by selectively depositing metal or metal oxide on a substrate surface to form discrete, three-dimensional islands. Selective deposition may be obtained, for example, by modifying process conditions to cause metal agglomeration or by treating the substrate surface to provide a limited number of discontinuous reactive sites. The roughened metal surface may be used, for example, in the manufacture of integrated circuits.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: August 28, 2012
    Assignee: ASM International N.V.
    Inventors: Hannu Huotari, Suvi Haukka
  • Patent number: 8242033
    Abstract: Methods for making and/or treating articles of semiconducting material are disclosed. In various methods, a first article of semiconducting material is provided, the first article of semiconducting material is heated sufficiently to melt the semiconducting material, and the melted semiconducting material is solidified in a direction substantially parallel to a shortest dimension of the melted article of semiconducting material. Articles of semiconducting materials made by methods described herein are also disclosed.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: August 14, 2012
    Assignee: Corning Incorporated
    Inventors: Glen Bennett Cook, Prantik Mazumder, Balram Suman, Natesan Venkataraman
  • Patent number: 8242028
    Abstract: A method for the ultraviolet (UV) treatment of etch stop and hard mask film increases etch selectivity and hermeticity by removing hydrogen, cross-linking, and increasing density. The method is particularly applicable in the context of damascene processing. A method provides for forming a semiconductor device by depositing an etch stop film or a hard mask film on a substrate and exposing the film to UV radiation and optionally thermal energy. The UV exposure may be direct or through another dielectric layer.
    Type: Grant
    Filed: April 3, 2007
    Date of Patent: August 14, 2012
    Assignee: Novellus Systems, Inc.
    Inventors: Bart van Schravendijk, Christian Denisse
  • Publication number: 20120202357
    Abstract: Methods for preparing a substrate for a subsequent film formation process are described. Methods for preparing a substrate for a subsequent film formation process, without immersion in an aqueous solution, are also described. A process is described that includes disposing a substrate into a process chamber, the substrate having a thermal oxide surface with substantially no reactive surface terminations. The thermal oxide surface is exposed to a partial pressure of water above the saturated vapor pressure at a temperature of the substrate to convert the dense thermal oxide with substantially no reactive surface terminations to a surface with hydroxyl surface terminations. This can occur in the presence of a Lewis base such as ammonia.
    Type: Application
    Filed: July 27, 2011
    Publication date: August 9, 2012
    Applicant: Applied Materials, Inc.
    Inventors: Tatsuya E. Sato, David Thompson, Jeffrey W. Anthis, Vladimir Zubkov, Steven Verhaverbeke, Roman Gouk, Maitreyee Mahajani, Patricia M. Liu, Malcolm J. Bevan
  • Publication number: 20120199953
    Abstract: The present invention relates to a process for smoothing the surface of a semiconductor wafer by fusion. The process includes defining a reference length which dimensions wafer surface roughness that is to be reduced or removed, and scanning the surface with a fusion beam while adjusting parameters of the fusion beam so as to fuse, during the scanning of the surface, a local surface zone of the wafer whose length is greater than or equal to the reference length, with the scanning continued to smooth the entire surface of the wafer by eliminating surface roughnesses of period lower than the reference length. The present invention also relates to a semiconductor wafer having a surface layer made of a semiconducting material that is smoothed by the process and that does not exhibit any roughness of period lower than the reference length.
    Type: Application
    Filed: January 12, 2012
    Publication date: August 9, 2012
    Applicant: SOITEC
    Inventor: Michel Bruel
  • Patent number: 8236677
    Abstract: A method of semiconductor junction formation in RTA process for fabrication of solar cells provides for delivery of inert gases in the vicinity of the Si wafer while dopant species are being driven form a dopant source into the surface of the wafer irradiated by a laser beam. The laser beam is emitted by CW- or pulsed operated lasers including fiber lasers operative to provide annealing and diffusion operation. Optionally, the passivation of the surface and formation of the antireflection coating are performed simultaneously with the penetration the dopant species.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: August 7, 2012
    Assignee: IPG Photonics Corporation
    Inventor: Bernhard P. Piwczyk
  • Patent number: 8236674
    Abstract: A substrate micro-processing method and a semiconductor device manufacturing method in which a stained part does not remain in a finished product even if a residual ion-injected part stays in the finished product. The substrate micro-processing method is one that carries out processing of a substrate by dividing the substrate depthwise, and comprises a proton injection step S11 in which protons are injected from one principal surface side of the substrate and an irradiation step S12 in which the substrate is irradiated with light having the wavelength nearly equal to the absorption wavelength of the defect level formed within the substrate due to the proton injection in order to divide the substrate.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: August 7, 2012
    Assignee: Japan Atomic Energy Agency
    Inventor: Shintaro Ishiyama
  • Publication number: 20120196454
    Abstract: Various embodiments may be used for laser-based modification of target material of a workpiece while advantageously achieving improvements in processing throughput and/or quality. Embodiments of a method of processing may include focusing and directing laser pulses to a region of the workpiece at a pulse repetition rate sufficiently high so that material is efficiently removed from the region and a quantity of unwanted material within the region, proximate to the region, or both is reduced relative to a quantity obtainable at a lower repetition rate. Embodiments of an ultrashort pulse laser system may include a fiber amplifier or fiber laser. Various embodiments are suitable for at least one of dicing, cutting, scribing, and forming features on or within a semiconductor substrate. Workpiece materials may include metals, inorganic or organic dielectrics, or any material to be micromachined with femtosecond, picosecond, and/or nanosecond pulses.
    Type: Application
    Filed: March 15, 2012
    Publication date: August 2, 2012
    Applicant: IMRA AMERICA, INC.
    Inventors: Lawrence Shah, Gyu Cheon Cho, Jingzhou Xu
  • Publication number: 20120196453
    Abstract: Systems and methods for microwave annealing are disclosed. In some embodiments, the system may comprise a microwave emitter configured to emit a microwave at a single frequency during an anneal time. In some embodiments, the system may further comprise an anneal unit to be annealed, the anneal unit having a top side, a bottom side, and one or more edge sides. In some embodiments, the system may further comprise a susceptor configured to absorb microwave energy, where the susceptor is adjacent to the edge side and at the bottom side of the anneal unit.
    Type: Application
    Filed: February 1, 2012
    Publication date: August 2, 2012
    Applicant: Arizona Board of Regents for and on Behalf of Arizona State University
    Inventor: Terry L. Alford
  • Patent number: 8231848
    Abstract: Ternary and quaternary Chalcopyrite CuInxGa1-xSySe2-y (CIGS, where 0?x and y?1) nanoparticles were synthesized from molecular single source precursors (SSPs) by a one-pot reaction in a high boiling solvent using salt(s) (i.e. NaCl as by-product) as heat transfer agent via conventional convective heating method. The nanoparticles sizes were 1.8 nm to 5.2 nm as reaction temperatures were varied from 150° C. to 190° C. with very high-yield. Tunable nanoparticle size is achieved through manipulation of reaction temperature, reaction time, and precursor concentrations. In addition, the method developed in this study was scalable to achieve ultra-large quantities production of tetragonal and quaternary Chalcopyrite CIGS nanoparticles.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: July 31, 2012
    Assignee: Sun Harmonics Ltd
    Inventors: Yuhang Ren, Chivin Sun, Kai Shum
  • Patent number: 8231852
    Abstract: It is possible to provide a silicon wafer that as well as being free of COPs and dislocation clusters, has defects (grown-in defects including silicon oxides), which are not overt in an as-grown state, such as OSF nuclei and oxygen precipitate nuclei existing in the PV region, to be vanished or reduced, by adopting a method for producing a silicon wafer, the method comprising the steps of: growing a single crystal silicon ingot by the Czochralski method; cutting a silicon wafer out of the ingot; subjecting the wafer to an RTP at 1,250° C. or more for 10 seconds or more in an oxidizing atmosphere; and removing a grown-in defect region including silicon oxides in the vicinity of wafer surface layer after the RTP.
    Type: Grant
    Filed: May 14, 2010
    Date of Patent: July 31, 2012
    Assignee: Sumco Corporation
    Inventors: Wataru Itou, Takashi Nakayama, Shigeru Umeno, Hiroaki Taguchi, Yasuo Koike
  • Patent number: 8227359
    Abstract: A method for manufacturing a Group III nitride semiconductor layer according to the present invention includes a sputtering step of disposing a substrate and a target containing a Group III element in a chamber, introducing a gas for formation of a plasma in the chamber and forming a Group III nitride semiconductor layer added with Si as a dopant on the substrate by a reactive sputtering method, wherein a Si hydride is added in the gas for formation of a plasma.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: July 24, 2012
    Assignee: Showa Denko K.K.
    Inventors: Yasunori Yokoyama, Hisayuki Miki
  • Patent number: 8227708
    Abstract: A system of via structures disposed in a substrate. The system includes a first via structure that comprises an outer conductive layer, an inner insulating layer, and an inner conductive layer disposed in the substrate. The outer conductive layer separates the inner insulating layer and the substrate and the inner insulating layer separates the inner conductive layer and the outer conductive layer. A first signal of a first complementary pair passes through the inner conductive layer and a second signal of the first complementary pair passes through the outer conductive layer. In different embodiments, a method of forming a via structure in an electronic substrate is provided.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: July 24, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Wei Zhao, Yu Cao, Shiqun Gu, Seung H. Kang, Ming-Chu King
  • Publication number: 20120184112
    Abstract: A mask for crystallizing a semiconductor layer includes a plurality of first main-slit portions, a plurality of second main-slit portions, upper slit portion and lower slit portion. The first main-slit portions extend along an inclined direction with respect to a first direction. The second main-slit portions are spaced apart from the first main-slit portions. The upper slit portion is disposed on the first main-slit portions along a second direction to be parallel to the first main-slit portions, and extends partway over the second main-slit portions to be longer than the first main-slit portions. The lower slit portion is disposed under the second main-slit portions along the second direction to be parallel to the second main-slit portions, and extends partway under the first main-slit portions to be longer than the second main-slit portions.
    Type: Application
    Filed: March 27, 2012
    Publication date: July 19, 2012
    Inventor: Cheol-Ho PARK
  • Patent number: 8222087
    Abstract: Magnetic recording heads and associated fabrication methods are disclosed. A heat spreader structure in a magnetic recording head includes a seed layer with a heat spreader layer formed on the seed layer. When the heat spreader layer (e.g., Aluminum Nitride) is grown on the seed layer (e.g., NiTa or Alumina), the heat spreader layer forms a well-oriented crystalline structure that allows for a desired thermal conductivity, such as a thermal conductivity greater than about 55 W/m?K. As a result of using the seed layer, a material such as Aluminum Nitride can be used for a heat spreader layer to effectively dissipate heat in a magnetic recording head.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: July 17, 2012
    Assignee: HGST Netherlands, B.V.
    Inventors: James M. Freitag, Howard G. Zolla
  • Patent number: 8222126
    Abstract: It is an object of the present invention to provide a laser irradiation apparatus being able to irradiate the irradiation object with the laser beam having homogeneous energy density without complicating the optical system. The laser irradiation apparatus of the present invention comprises a laser oscillator, an optical system for scanning repeatedly a beam spot of the laser beam emitted from the laser oscillator in a uniaxial direction over the surface of the irradiation object, and a position controlling means for moving the position of the irradiation object relative to the laser beam in a direction perpendicular to the uniaxial direction.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: July 17, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koichiro Tanaka, Yoshiaki Yamamoto
  • Publication number: 20120175652
    Abstract: The present invention is a system and method for laser-assisted singulation of light emitting electronic devices manufactured on a substrate, having a processing surface and a depth extending from the processing surface. It includes providing a laser processing system having a picosecond laser having controllable parameters; controlling the laser parameters to form light pulses from the picosecond laser, to form a modified region having a depth which spans about 50% of the depth and substantially including the processing surface of the substrate and having a width less than about 5% of the region depth; and, singulating the substrate by applying mechanical stress to the substrate thereby cleaving the substrate into said light emitting electronic devices having sidewalls formed at least partially in cooperation with the linear modified regions.
    Type: Application
    Filed: January 6, 2011
    Publication date: July 12, 2012
    Applicant: ELECTRO SCIENTIFIC INDUSTRIES, INC.
    Inventors: Irving Chyr, Jonathan Halderman, Juan Chacin
  • Publication number: 20120175585
    Abstract: A unique family of nanoparticles characterized by their nanometric size and cage-like shapes (hollow structures), capable of holding in their hollow cavity a variety of materials is disclosed herein.
    Type: Application
    Filed: September 16, 2010
    Publication date: July 12, 2012
    Applicant: YISSUM RESEARCH DEVELOPMENT COMPANY OF THE HEBREW UNIVERSITY OF JERUSALEM, LTD.,
    Inventors: Uri Banin, Elizabeth Janet Macdonald
  • Patent number: 8216924
    Abstract: Fabrication of a Group III-nitride transistor device can include implanting dopant ions into a stacked Group III-nitride channel layer and Group III-nitride barrier layer to form source/drain regions therein with a channel region therebetween. The channel layer has a lower bandgap energy than the barrier layer along a heterojunction interface between the channel layer and the barrier layer. The source/drain regions have a lower defect centers energy than the channel region. The source/drain regions and the channel region are exposed to a laser beam with a wavelength having a photon energy that is less than the bandgap energy of the channel region and higher than the defect centers energy of the source/drain regions to locally heat the source/drain regions to a temperature that anneals the source/drain regions.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: July 10, 2012
    Assignee: Cree, Inc.
    Inventor: Alexander V. Suvorov
  • Publication number: 20120171876
    Abstract: A method for irradiating semiconductor material is provided which includes selecting a region of a semiconductor layer surface, irradiating the region with an excimer laser which has a beam spot size, and adjusting the beam spot size to match the selected region size. Further, an apparatus for irradiating semiconductor material is provided. The apparatus includes an excimer laser for irradiating a selected region of a semiconductor layer surface, the laser has a laser beam spot size, and a system for adjusting the laser beam spot size to match the selected region size.
    Type: Application
    Filed: March 29, 2010
    Publication date: July 5, 2012
    Applicant: EXCICO FRANCE
    Inventors: Julien Venturini, Bruno Godard, Cyril Dutems, Marc Bucchia
  • Publication number: 20120171875
    Abstract: A system and method for reducing warpage of a semiconductor wafer. The system includes a device for securing the semiconductor wafer in a heating area. The device includes a holding mechanism for securing an edge of the semiconductor wafer. The device further includes a pressure reducing device that reduces the pressure underneath the semiconductor device, which further secures the semiconductor device in the heating area. The heating area includes a plurality of heating and cooling zones in which the semiconductor wafer is subjected to various temperatures.
    Type: Application
    Filed: December 30, 2010
    Publication date: July 5, 2012
    Applicant: STMICROELECTRONICS PTE. LTD.
    Inventors: Kah Wee Gan, Yonggang Jin
  • Patent number: 8211731
    Abstract: A dielectric film stack of a solar cell is ablated using a laser. The dielectric film stack includes a layer that is absorptive in a wavelength of operation of the laser source. The laser source, which fires laser pulses at a pulse repetition rate, is configured to ablate the film stack to expose an underlying layer of material. The laser source may be configured to fire a burst of two laser pulses or a single temporally asymmetric laser pulse within a single pulse repetition to achieve complete ablation in a single step.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: July 3, 2012
    Assignee: SunPower Corporation
    Inventors: Gabriel Harley, Taeseok Kim, Peter John Cousins
  • Patent number: 8207068
    Abstract: Example embodiments relate to a method of fabricating a memory device and a memory device. The method of fabricating a memory device comprises forming a lower electrode and an oxide layer on a lower structure and radiating an energy beam on a region of the oxide layer. The memory device comprises a lower structure and an oxide layer and a lower structure formed on the lower structure, the oxide layer including an electron beam radiation region that received radiation from an electron beam source creating an artificially formed current path through the oxide layer to the lower electrode. A reset current of the memory device may be decreased and stabilized.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: June 26, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-eon Ahn, Hye-young Kim, Byoung-ho Park, Jung-bin Yun, You-seon Kim
  • Patent number: 8207055
    Abstract: A method for generating an electrode layer pattern in an organic functional device (101; 201) comprising a first transparent electrode layer (103; 203), a second electrode layer (104; 204) and an organic functional layer (102; 202) sandwiched between said first and second electrode layers (103, 104; 203, 204). The method comprises the steps of arranging (601) a laser (704; 804) to irradiate said organic functional device (701; 801) through said first transparent electrode layer (103; 203), selecting (602) a set of laser parameters in order to enable said laser (704; 804) to locally modify an electric conductivity of said second electrode layer (104; 204), and locally modifying, by said laser (704; 804) in accordance with said set of laser parameters, the electric conductivity of said second electrode layer (104; 204), thereby generating said electrode layer pattern.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: June 26, 2012
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Michael Büchel, Ivar Jacco Boerefijn, Edward Willem Albert Young, Adrianus Sempel
  • Publication number: 20120138136
    Abstract: This invention describes a semiconductor material of general formula (I) Me12Me21-xMe3xMe4(C11-yC2y)4, in which x stands for a numeric value from 0 to 1, and y stands for a numeric value of 0 to 1, as well as its use as an absorber material in a solar cell. The metal Mel is a metal which is selected from the metals in group 11 of the periodic table of the elements (Cu, Ag or Au). The metals Me2 and Me3 are selected from the elements of the 12th group of the periodic table of elements (Zn, Cd & Hg). The metal Me4 is a metal which is selected from the 4th main group of the periodic table of elements (C, Si, Ge, Sn and Pb). The non-metals C1 and C2 are selected from the group of chalcogenides (S, Se and Te).
    Type: Application
    Filed: July 15, 2009
    Publication date: June 7, 2012
    Inventors: Dieter Meissner, Mare Altosaar, Enn Mellikov, Jaan Raudoja, Kristi Timmo
  • Patent number: 8193088
    Abstract: A method of forming metal lines of a semiconductor device includes forming an etch stop layer over a semiconductor substrate over which underlying structures are formed, forming an insulating layer over the etch stop layer, etching the etch stop layer and the insulating layer to form trenches through which the underlying structures are exposed, shrinking the insulating layer by using a thermal treatment process in order to widen openings of the trenches, and filling the trenches with a conductive material.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: June 5, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Suk Joong Kim
  • Patent number: 8192648
    Abstract: A method of forming a material from a source material including the following steps of grinding the source material to get powders if the source material is not already in the form of powders; sintering the powders with at least one compression step and one thermal processing step; and purifying the material with a gas flow, the gas flow passing through the porosity channels of the material.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: June 5, 2012
    Assignee: S'Tile
    Inventor: Alain Straboni