Radiation Or Energy Treatment Modifying Properties Of Semiconductor Region Of Substrate (e.g., Thermal, Corpuscular, Electromagnetic, Etc.) Patents (Class 438/795)
  • Patent number: 8557715
    Abstract: The present invention relates to a CO2 laser-transparent material having a mark on the surface thereof and the method for making the same. The method includes the following steps: providing a first substrate, which has a top surface and a bottom surface; providing a second substrate which has a top surface; putting the bottom surface of the first substrate on the top surface of the second substrate; irradiating a CO2 laser beam to the top surface of the second substrate by passing through the top surface and the bottom surface of the first substrate; and forming a mark on the bottom surface of the first substrate. The material of the mark is oxide of the second substrate or the same as the material of the second substrate. Whereby the cheap CO2 laser is utilized to form the mark on the first substrate, and the mark can be erased easily by a proper chemical for recycling the first substrate.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: October 15, 2013
    Assignee: National Cheng Kung University
    Inventors: Chen-Kuei Chung, Meng-Yu Wu, En-Jou Hsiao, Shih-Lung Lin
  • Patent number: 8551441
    Abstract: New methods for improving thermoelectric properties of bismuth telluride based materials are described. Constrained deformation, such as by canned/sandwich, or encapsulated, rolling and plane strain channel die compression, particularly at temperatures above 80% of the melting point of the material on an absolute temperature scale, changes the crystallographic texture and grain size to desirably increase the values of both the thermoelectric power factor and the thermoelectric figure of merit ZT for the material.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: October 8, 2013
    Assignee: United States of America as represented by the Secretary of the Air Force
    Inventors: Raghavan Srinivasan, Jonathan E. Spowart, Nicholas Gothard
  • Patent number: 8551865
    Abstract: A method of cutting an object which can accurately cut the object is provided. An object to be processed 1 such as a silicon wafer is irradiated with laser light L while a light-converging point P is positioned therewithin, so as to form a modified region 7 due to multiphoton absorption within the object 1, and cause the modified region 7 to form a starting point region for cutting 8 shifted from the center line CL of the thickness of the object 1 toward the front face 3 of the object 1 along a line along which the object should be cut. Subsequently, the object 1 is pressed from the rear face 21 side thereof. This can generate a fracture from the starting point region for cutting 8 acting as a start point, thereby accurately cutting the object 1 along the line along which the object should be cut.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: October 8, 2013
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Fumitsugu Fukuyo, Kenshi Fukumitsu
  • Patent number: 8546920
    Abstract: A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: October 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: Anthony I. Chou, Toshiharu Furukawa, Wilfried Haensch, Zhibin Ren, Dinkar V. Singh, Jeffrey W. Sleight
  • Patent number: 8546248
    Abstract: A method of forming a polycrystalline silicon layer and an atomic layer deposition apparatus used for the same. The method includes forming an amorphous silicon layer on a substrate, exposing the substrate having the amorphous silicon layer to a hydrophilic or hydrophobic gas atmosphere, placing a mask having at least one open and at least one closed portion over the amorphous silicon layer, irradiating UV light toward the amorphous silicon layer and the mask using a UV lamp, depositing a crystallization-inducing metal on the amorphous silicon layer, and annealing the substrate to crystallize the amorphous silicon layer into a polycrystalline silicon layer. This method and apparatus provide for controlling the seed position and grain size in the formation of a polycrystalline silicon layer.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: October 1, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yun-Mo Chung, Ki-Yong Lee, Min-Jae Jeong, Jin-Wook Seo, Jong-Won Hong, Heung-Yeol Na, Eu-Gene Kang, Seok-Rak Chang, Tae-Hoon Yang, Ji-Su Ahn, Young-Dae Kim, Byoung-Keon Park, Kil-Won Lee, Dong-Hyun Lee, Sang-Yon Yoon, Jong-Ryuk Park, Bo-Kyung Choi, Maxim Lisachenko
  • Patent number: 8546277
    Abstract: Process for heating a plastic by means of at least one source of electromagnetic radiation, characterized in that the electromagnetic radiation is emitted in the infrared at a wavelength or in a wavelength spectrum contained in one of the following ranges: 1110-1160 nm; 1390-1450 nm; 1610-1650 nm; 1675-1700 nm; 1880-2100 nm; 2170-2230 nm.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: October 1, 2013
    Assignee: Sidel Participations
    Inventor: Bernard Plantamura
  • Publication number: 20130252424
    Abstract: An apparatus, a system and a method are disclosed. An exemplary apparatus includes a wafer holder including a first portion and a second portion. The first and second portions are formed of the same continuous material. The first portion includes a first upper surface and a first lower surface, and the second portion including a second upper surface and a second lower surface. The apparatus further includes an interface between the first and second portions. The interface provides for a transition such that the first upper surface of the first portion tends toward the second upper surface of the second portion. The apparatus further includes a tapered region formed in the first portion. The tapered region starts at a radial distance from a center line of the wafer holder and terminates at the interface. The tapered region has an initial thickness that gradually decreases to a final thickness.
    Type: Application
    Filed: March 21, 2012
    Publication date: September 26, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Hung Lin, Li-Ting Wang, Tze-Liang Lee
  • Patent number: 8541319
    Abstract: A laser processing method comprises a laser light converging step of converging a laser light at a sheet-like object to be processed made of silicon so as to form a modified region within the object, and an etching step of anisotropically etching the object so as to thin the object to a target thickness and advancing the etching selectively along the modified region so as to form the object with a through hole tilted with respect to a thickness direction of the object after the laser light converging step, wherein the laser light converging step forms a first modified region as the modified region in a part corresponding to the through hole in the object and a second modified region as the modified region extending parallel to the thickness direction and joining with the first modified region in a part to be removed upon thinning by the anisotropic etching in the object, and wherein the etching step advances the etching selectively along the second modified region and then along the first modified region whil
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: September 24, 2013
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Hideki Shimoi, Keisuke Araki
  • Publication number: 20130244449
    Abstract: A picosecond laser beam shaping assembly is disclosed for shaping a picosecond laser beam for use in patterning (e.g., scribing) semiconductor devices. The assembly comprises a pulsed fibre laser source of picosecond laser pulses, a harmonic conversion element for converting laser pulses at a first laser wavelength having a first spectral bandwidth to laser pulses at a second laser wavelength having a second spectral bandwidth, and a beam shaping apparatus for shaping the laser beam at the second laser wavelength, the beam shaping apparatus having a spectral bandwidth that substantially corresponds to the second spectral bandwidth so as to produce a laser beam having a substantially rectangular cross-sectional profile.
    Type: Application
    Filed: September 6, 2011
    Publication date: September 19, 2013
    Applicant: FIANIUM LTD.
    Inventors: Brian W. Baird, Timothy D. Gerke
  • Publication number: 20130235895
    Abstract: A laser light source (100) according to the present invention includes a laser resonator (150) including a fiber (107) containing a laser active medium and a fiber grating (105, 160) coupled to each of two ends of the fiber (107); an pumping laser light source (104) for emitting pump light into the laser resonator (150); a driving current supply circuit (102) for supplying a pulse-like driving current to the pumping laser light source (104); and a wavelength conversion element (101) for converting a wavelength of laser light which is output from the laser resonator. The laser resonator (150) generates laser light including a principal pulse and a plurality of superimposing pulses which are superimposed on the principal pulse, in accordance with incidence of the pump light; and converted light having the wavelength of each of the principal pulse and the superimposing pulses shortened is generated by the wavelength conversion element (101).
    Type: Application
    Filed: November 17, 2010
    Publication date: September 12, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Kiminori Mizuuchi, Susumu Takagi
  • Patent number: 8530361
    Abstract: A method for depositing a silicon containing film on a substrate using an organoaminosilane is described herein. The organoaminosilanes are represented by the formulas: wherein R is selected from a C1-C10 linear, branched, or cyclic, saturated or unsaturated alkyl group with or without substituents; a C5-C10 aromatic group with or without substituents, a C3-C10 heterocyclic group with or without substituents, or a silyl group in formula C with or without substituents, R1 is selected from a C3-C10 linear, branched, cyclic, saturated or unsaturated alkyl group with or without substituents; a C6-C10 aromatic group with or without substituents, a C3-C10 heterocyclic group with or without substituents, a hydrogen atom, a silyl group with substituents and wherein R and R1 in formula A can be combined into a cyclic group and R2 representing a single bond, (CH2)n chain, a ring, C3-C10 branched alkyl, SiR2, or SiH2.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: September 10, 2013
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Manchao Xiao, Xinjian Lei, Heather Regina Bowen, Mark Leonard O'Neill
  • Patent number: 8526473
    Abstract: Processing workpieces such as semiconductor wafers or other materials with a laser includes selecting a target to process that corresponds to a target class associated with a predefined temporal pulse profile. The temporal pulse profile includes a first portion that defines a first time duration, and a second portion that defines a second time duration. A method includes generating a laser pulse based on laser system input parameters configured to shape the laser pulse according to the temporal pulse profile, detecting the generated laser pulse, comparing the generated laser pulse to the temporal pulse profile, and adjusting the laser system input parameters based on the comparison.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: September 3, 2013
    Assignee: Electro Scientific Industries
    Inventors: Brian W. Baird, Clint R. Vandergiessen, Steve Swaringen, Robert Hainsey, Yunlong Sun, Kelly J. Bruland, Andrew Hooper
  • Patent number: 8524611
    Abstract: In manufacturing a semiconductor device, a first chamber is provided. An opening couples the first chamber to a first environment through which at least one substrate can pass. A first seal environmentally isolates the first chamber from the first environment. A process chamber is coupled to the first chamber. Another seal environmental isolates the first and the process chambers. The substrate is placed within the first chamber, and the first chamber and the outside environment are isolated. The second opening is opened, and the substrate moves into the semiconductor process chamber. The first chamber is again environmentally isolated from the second volume. A semiconductor processing step is performed on the substrate within the processing chamber. While the substrate is processed, the substrate is rotated and translated through the processing chamber.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: September 3, 2013
    Assignee: Solyndra LLC
    Inventor: Ratson Morad
  • Patent number: 8524599
    Abstract: Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: September 3, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Scott E. Sills, Whitney L. West, Rob B. Goodwin, Nishant Sinha
  • Publication number: 20130224967
    Abstract: A capacitor, a coil, a flash lamp, and a switching element such as an IGBT are connected in series. A controller outputs a pulse signal to the gate of the switching element. A waveform setter sets the waveform of the pulse signal, based on the contents of input from an input unit. With electrical charge accumulated in the capacitor, a pulse signal is output to the gate of the switching element so that the flash lamp emits light intermittently. A change in the waveform of the pulse signal applied to the switching element will change the waveform of current flowing through the flash lamp and, accordingly, the form of light emission, thereby resulting in a change in the temperature profile for a semiconductor wafer.
    Type: Application
    Filed: March 21, 2013
    Publication date: August 29, 2013
    Inventor: Tatsufumi Kusuda
  • Patent number: 8518838
    Abstract: Methods used to perform an annealing process on desired regions of a substrate are disclosed. In one embodiment, an amount of energy is delivered to the surface of the substrate to preferentially melt certain desired regions of the substrate to remove unwanted damage created from prior processing steps (e.g., crystal damage from implant processes), more evenly distribute dopants in various regions of the substrate, and/or activate various regions of the substrate. The preferential melting processes will allow more uniform distribution of the dopants in the melted region, due to the increased diffusion rate and solubility of the dopant atoms in the molten region of the substrate. The creation of a melted region thus allows: 1) the dopant atoms to redistribute more uniformly, 2) defects created in prior processing steps to be removed, and 3) regions that have hyper-abrupt dopant concentrations to be formed.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: August 27, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Paul Carey, Aaron Muir Hunter, Dean Jennings, Abhilash J. Mayur, Stephen Moffatt, William Schaffer, Timothy N. Thomas, Mark Yam
  • Patent number: 8518763
    Abstract: A thin-film transistor device manufacturing method of forming a crystalline silicon film of stable crystallinity using a laser of a wavelength in a visible region is provided. The thin-film transistor device manufacturing method forms a plurality of gate electrodes above a substrate. A gate insulation layer is formed on the plurality of gate electrodes. An amorphous silicon layer is formed on the gate insulation layer. The amorphous silicon layer is crystallized using predetermined laser light to produce a crystalline silicon layer. A source electrode and a drain electrode are formed on the crystalline silicon layer in a region that corresponds to each of the plurality of gate electrodes. A film thickness of the gate insulation layer and a film thickness of the amorphous silicon layer satisfy predetermined conditional expressions.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: August 27, 2013
    Assignee: Panasonic Corporation
    Inventor: Yuta Sugawara
  • Publication number: 20130217236
    Abstract: A semiconductor device is provided with a porous structure layer formed by silicone resin between a substrate and a semiconductor element. Alternatively, a porous layer having a density of 0.7 g/cm3 or less, formed by a compound obtained by hydrolyzing and condensing at least one type of alkoxysilane selected from a group consisting of monoalkoxysilane, dialkoxysilane, and trialkoxysilane, and tetraalkoxysilane is provided between the substrate and the semiconductor element. As a further alternative, an adhesion layer formed by a compound obtained by hydrolyzing and condensing an alkoxysilane is provided on a resin substrate, and a porous layer having a density of 0.7 g/cm3 or less, formed by a compound obtained by hydrolyzing and condensing an alkoxysilane, is provided on the adhesion layer.
    Type: Application
    Filed: March 15, 2013
    Publication date: August 22, 2013
    Applicant: FUJIFILM CORPORATION
    Inventor: Fujifilm Corporation
  • Patent number: 8513065
    Abstract: A method of manufacturing a display device is disclosed. In one embodiment, the method includes: i) forming a semiconductor layer where a plurality of crystallized areas and a plurality of noncrystallized areas are alternately arranged on a substrate, ii) aligning the substrate based on a difference in contrast ratio between the crystallized and noncrystallized areas and iii) performing a photo process or a photolithography process.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: August 20, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seong-Hyun Jin, Jae-Beom Choi, Won-Kyu Lee, Young-Jin Chang, Jae-Hwan Oh
  • Publication number: 20130210242
    Abstract: Provided is a laser annealing treatment including a laser light source that outputs pulse laser light, an optical system that shapes the pulse laser light, and leads the shaped pulse laser light to a semiconductor film subject to treatment, and a stage that carries the semiconductor film to be irradiated by the pulse laser light, wherein the pulse laser light irradiating the semiconductor film presents a rising time equal to or less than 35 nanoseconds from 10% of the maximum height to the maximum height in the pulse energy density, and a falling time equal to or more than 80 nanoseconds from the maximum height to 10% of the maximum height, thereby increasing, while an energy density suitable for crystallization and the like is not particularly increased, a margin quantity thereof, and carrying out high quality annealing treatment without decreasing a throughput.
    Type: Application
    Filed: September 17, 2010
    Publication date: August 15, 2013
    Applicant: The Japan Steel Works, Ltd.
    Inventors: Junichi Shida, Suk-Hwan Chung, Masashi Machida
  • Patent number: 8507296
    Abstract: A substrate processing method in a processing chamber, has: accommodating a substrate into a processing chamber; and processing the substrate in the processing chamber on the basis of a correlation of a preset temperature of a heating device, a flow rate of fluid supplied by a cooling device and a temperature deviation between the center side of the substrate accommodated in the processing chamber and the outer peripheral side of the substrate while the substrate accommodated in the processing chamber is optically heated from an outer periphery side of the substrate at a corrected preset temperature by the heating device and the fluid is supplied to the outside of the processing chamber at the flow rate based on the correlation concerned to cool the outer peripheral side of the substrate by the cooling device.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: August 13, 2013
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Masaaki Ueno, Masakazu Shimada, Takeo Hanashima, Haruo Morikawa, Akira Hayashida
  • Patent number: 8507334
    Abstract: If an optical path length of an optical system is reduced and a length of a laser light on an irradiation surface is increased, there occurs curvature of field which is a phenomenon that a convergent position deviates depending on an incident angle or incident position of a laser light with respect to a lens. To avoid this phenomenon, an optical element having a negative power such as a concave lens or a concave cylindrical lens is inserted to regulate the optical path length of the laser light and a convergent position is made coincident with a irradiation surface to form an image on the irradiation surface.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: August 13, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koichiro Tanaka, Tomoaki Moriwaka
  • Publication number: 20130203269
    Abstract: A first flash heating is performed in which a lower flash lamp irradiates a back surface of a semiconductor wafer with flashes of light, so that heat conduction from the back surface to a surface of the semiconductor wafer raises the temperature of the surface from the room temperature to an intermediate temperature. Then, a second flash heating is performed in which an upper flash lamp irradiates the surface of the semiconductor wafer with flashes of light, to raise the temperature of the surface of the semiconductor wafer from the intermediate temperature to a target temperature. Since only the irradiation with flashes of light emitted from the lower flash lamp and the upper flash lamp is used to cause the semiconductor wafer having the room temperature to reach the target temperature, all heat treatments can be completed in an extremely short time of one second or less.
    Type: Application
    Filed: January 29, 2013
    Publication date: August 8, 2013
    Applicant: DAINIPPON SCREEN MFG. CO., LTD.
    Inventor: DAINIPPON SCREEN MFG. CO., LTD.
  • Patent number: 8501605
    Abstract: Methods and apparatus for processing a substrate are provided herein. In some embodiments, a method of doping a substrate may include forming a dopant region on a substrate by implanting one or more dopant elements into the dopant region of the substrate using a plasma doping process; forming a cap layer atop the dopant region; annealing the dopant region after forming the cap layer; and removing the cap layer after annealing the dopant region.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: August 6, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Kartik Santhanam, Martin A. Hilkene, Manoj Vellaikal, Mark R. Lee, Matthew D. Scotney-Castle, Peter I. Porshnev
  • Patent number: 8501568
    Abstract: A methods of forming a flash memory device are provided. The flash memory device comprises a silicon dioxide layer on a substrate and a silicon nitride layer that is formed on the silicon dioxide layer. The properties of the silicon nitride layer can be modified by any of: exposing the silicon nitride layer to ultraviolet radiation, exposing the silicon nitride layer to an electron beam, and by plasma treating the silicon nitride layer. A dielectric material is deposited on the silicon nitride layer and a conductive date is formed over the dielectric material. The flash memory device with modified silicon nitride layer provides an increase in charge holding capacity and charge retention time of the unit cell of a non-volatile memory device.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: August 6, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Mihaela Balseanu, Vladimir Zubkov, Li-Qun Xia, Atif Noori, Reza Arghavani, Derek R. Witty, Amir Al-Bayati
  • Publication number: 20130196517
    Abstract: A charged particle beam drawing apparatus draws a plurality of cut patterns on a plurality of first linear patterns arranged to extend in a first direction and align themselves at a predetermined pitch P in a second direction perpendicular to the first direction. The plurality of cut patterns are drawn so that an interval Ai in the second direction between the centers of each pair of cut patterns adjacent to each other in the second direction (i is a number which specifies the pair) satisfies a relation: Ai=m1X (m1=1, 2, 3, . . . ) where X is a dimension defined by the pitch P.
    Type: Application
    Filed: January 25, 2013
    Publication date: August 1, 2013
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: CANON KABUSHIKI KAISHA
  • Publication number: 20130196455
    Abstract: Systems and methods are disclosed for performing laser annealing in a manner that reduces or minimizes wafer surface temperature variations during the laser annealing process. The systems and methods include annealing the wafer surface with first and second laser beams that represent preheat and anneal laser beams having respective first and second intensities. The preheat laser beam brings the wafer surface temperate close to the annealing temperature and the anneal laser beam brings the wafer surface temperature up to the annealing temperature. The anneal laser beam can have a different wavelength, or the same wavelength but different orientation relative to the wafer surface. Reflectivity maps of the wafer surface at the preheat and anneal wavelengths are measured and used to select first and second intensities that ensure good anneal temperature uniformity as a function of wafer position.
    Type: Application
    Filed: January 27, 2012
    Publication date: August 1, 2013
    Inventors: Xiaohua Shen, Yun Wang, Xiaoru Wang
  • Patent number: 8492294
    Abstract: A semiconductor-on-insulator substrate and a related semiconductor structure, as well as a method for fabricating the semiconductor-on-insulator substrate and the related semiconductor structure, provide for a multiple order radio frequency harmonic suppressing region located and formed within a base semiconductor substrate at a location beneath an interface of a buried dielectric layer with the base semiconductor substrate within the semiconductor-on-insulator substrate. The multiple order radio frequency harmonic suppressing region may comprise an ion implanted atom, such as but not limited to a noble gas atom, to provide a suppressed multiple order radio frequency harmonic when powering a radio frequency device, such as but not limited to a radio frequency complementary metal oxide semiconductor device (or alternatively a passive device), located and formed within and upon a surface semiconductor layer within the semiconductor structure.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Joseph R. Greco, Kevin Munger, Richard A. Phelps, Jennifer C. Robbins, William Savaria, James A. Slinkman, Randy L. Wolf
  • Patent number: 8492292
    Abstract: Methods for processing substrates are provided herein. In some embodiments, a method for processing a substrate includes providing a substrate having an oxide layer disposed thereon, the oxide layer including one or more defects; and exposing the oxide layer to a plasma formed from a process gas comprising an oxygen-containing gas to repair the one or more defects. In some embodiments, the oxide layer may be formed on the substrate. In some embodiments, forming the oxide layer further comprises depositing the oxide layer atop the substrate. In some embodiments, forming the oxide layer further comprises thermally oxidizing the surface of the substrate to form the oxide layer. In some embodiments, a processing temperature is maintained at about 700 degrees Celsius or below during the thermal oxidation of the surface.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: July 23, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Yoshitaka Yokota, Christopher S. Olsen, Agus Sofian Tjandra, Yonah Cho, Matthew S. Rogers
  • Patent number: 8492170
    Abstract: Methods for the repair of damaged low k films are provided. Damage to the low k films occurs during processing of the film such as during etching, ashing, and planarization. The processing of the low k film causes water to store in the pores of the film and further causes hydrophilic compounds to form in the low k film structure. Repair processes incorporating ultraviolet (UV) radiation and silylation compounds remove the water from the pores and further remove the hydrophilic compounds from the low k film structure.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: July 23, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Bo Xie, Alexandros T. Demos, Kang Sub Yim, Thomas Nowak, Kelvin Chan
  • Patent number: 8492295
    Abstract: A semiconductor structure fabrication method. A provided structure includes: a semiconductor substrate, a transistor on the semiconductor substrate, N interconnect layers on the semiconductor substrate, and a temporary filling region within the N layers. N is at least 2. The temporary filling region is heated at a high temperature sufficiently high to result in the temporary filling material being replaced by a cooling pipes system that does not include any solid or liquid material. A first portion and a second portion of the cooling pipes system are each in direct physical contact with a surrounding ambient at a first interface and a second interface respectively such that a first direction perpendicular to the first interface is perpendicular to a second direction perpendicular to the second interface. A totality of interfaces between the cooling pipes system and the ambient consists of the first interface and the second interface.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kaushik A. Kumar, Andres Fernando Munoz, Michael Ray Sievers, Richard Stephen Wise
  • Patent number: 8492736
    Abstract: A quartz window with an interior plenum is operable as a shutter or UV filter in a degas chamber by supplying the plenum with an ozone-containing gas. Pressure in the plenum can be adjusted to block UV light transmission into the degas chamber or adjust transmittance of UV light through the window. When the plenum is evacuated, the plenum allows maximum transmission of UV light into the degas chamber.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: July 23, 2013
    Assignee: Lam Research Corporation
    Inventors: Yen-Kun Victor Wang, Shang-I Chou, Jason Augustino
  • Publication number: 20130183837
    Abstract: Examples of methods and systems for laser processing of materials are disclosed. Methods and systems for singulation of a wafer comprising a coated substrate can utilize a laser outputting light that has a wavelength that is transparent to the wafer substrate but which may not be transparent to the coating layer(s). Using techniques for managing fluence and focal condition of the laser beam, the coating layer(s) and the substrate material can be processed through ablation and internal modification, respectively. The internal modification can result in die separation.
    Type: Application
    Filed: December 14, 2012
    Publication date: July 18, 2013
    Applicant: IMRA AMERICA, INC.
    Inventor: IMRA America, Inc.
  • Publication number: 20130183836
    Abstract: Methods of forming through-silicon vias by using laser ablation. A method includes, laser drilling to form a plurality of grooves by irradiating a laser beam onto an upper surface of a silicon wafer, and grinding a lower surface of the silicon wafer to form a plurality of through-silicon vias by exposing the grooves on the lower surface of the silicon wafer.
    Type: Application
    Filed: December 4, 2012
    Publication date: July 18, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Samsung Electronics Co., Ltd.
  • Patent number: 8486737
    Abstract: A thin film deposition apparatus and a method of manufacturing an organic light-emitting display device by using the same, and more particularly, to a thin film deposition apparatus that can remove a deposition material deposited on a patterning slit sheet without performing an additional cleaning process, and a method of manufacturing an organic light-emitting display device by using the thin film deposition apparatus.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: July 16, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yun-Mi Lee, Yong-Sup Choi, Hyun-Sook Park, Jong-Heon Kim, Jae-Kwang Ryu, Young-Mook Choi
  • Patent number: 8486813
    Abstract: A silicon wafer and fabrication method thereof are provided. The silicon wafer includes a first denuded zone formed with a predetermined depth from a top surface of the silicon wafer, the first denuded zone being formed with a depth ranging from approximately 20 ?m to approximately 80 ?m from the top surface, and a bulk area formed between the first denuded zone and a backside of the silicon wafer, the bulk area having a concentration of oxygen uniformly distributed within a variation of 10% over the bulk area.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: July 16, 2013
    Assignee: Magnachip Semiconductor, Ltd.
    Inventor: Jung-Goo Park
  • Publication number: 20130178072
    Abstract: A method of cleaning a chamber used for annealing doped wafer substrates. In one embodiment the method provides removing dopants deposited in an annealing chamber after an annealing process of a doped substrate by flowing one or more volatilizing gases into the annealing chamber, applying heat to volatilize the deposited dopants in the annealing chamber, and exhausting the chamber to remove volatilized dopants from the annealing chamber.
    Type: Application
    Filed: November 12, 2012
    Publication date: July 11, 2013
    Inventors: BALASUBRAMANIAN RAMACHANDRAN, Tae Jung Kim, Jung Hoon Sun, Joung Woo Lee, Hwa Joong Lim, Sang Phil Lee, Joseph M. Ranish
  • Patent number: 8481123
    Abstract: Novel methods and apparatuses for annealing semiconductor devices in a high pressure gas environment. According to an embodiment, the annealing vessel has a dual chamber structure, and potentially toxic, flammable, or otherwise reactive gas is confined in an inner chamber which is protected by pressures of inert gas contained in the outer chamber. The incoming gas delivery system and exhaust gas venting system are likewise protected by various methods. Embodiments of the present invention can be used, for example, for high-K gate dielectric anneal, post metallization sintering anneal, and forming gas anneal in the semiconductor manufacturing process.
    Type: Grant
    Filed: February 4, 2009
    Date of Patent: July 9, 2013
    Assignee: Poongsan Microtec Corporation
    Inventors: Sang-Shin Kim, Manuel Scott Rivera, Suk-Dong Hong
  • Patent number: 8483248
    Abstract: A method for preparing a surface of a YAG crystal for thermal bonding includes performing an ion implantation process to introduce nitrogen into a surface layer of the YAG crystal to replace depleted oxygen therein, to change surface energy of the surface layer of the YAG crystal and to provide desired bonding characteristics for the surface layer; and joining the ion implanted surface layer with a thermal management device configured to dissipate heat from the YAG crystal. Also, a micro-chip device having a YAG crystal whose surface is prepared with the above disclosed method is provided and a device for forming a metallization pattern on a surface of the YAG crystal is provided.
    Type: Grant
    Filed: September 14, 2010
    Date of Patent: July 9, 2013
    Assignee: Raytheon Company
    Inventor: Michael Ushinsky
  • Publication number: 20130171744
    Abstract: A method of thermally treating a wafer includes loading a wafer into a process chamber having one or more regions of uniform temperature gradient and one or more regions of non-uniform temperature gradient. A defect is detected in the wafer. The wafer is aligned to position the defect within one of the one or more regions of uniform temperature gradient. A rapid thermal process is performed on the wafer in the process chamber while the defect is positioned within one of the one or more regions of uniform temperature gradient.
    Type: Application
    Filed: December 14, 2012
    Publication date: July 4, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: SAMSUNG ELECTRONICS CO., LTD.
  • Publication number: 20130164939
    Abstract: Some embodiments discussed relates to an apparatus for holding a substrate, comprising a body with a surface for a semiconductor wafer to rest on, with the surface having a first surface area on which a first area of the semiconductor wafer can rest, and a second surface area on which a second area of the semiconductor wafer can rest, wherein the second surface area protrudes with respect to the first surface area.
    Type: Application
    Filed: February 22, 2013
    Publication date: June 27, 2013
    Applicant: Infineon Technologies AG
    Inventor: Infineon Technologies AG
  • Publication number: 20130164948
    Abstract: A method of improving temperature uniformity across a wafer or substrate is provided. The inventors have discovered that thermal radiation reflected from the showerhead injector affects the temperature uniformity across the wafer. Temperature uniformity across the wafer, particularly from the center to edge of the wafer, is improved by controlling the reflected energy from the showerhead. Control of the reflected energy from the showerhead is achieved by a variety of means, including changing the emissivity of the showerhead, creating different zones of emissivity of the showerhead, selectively heating the showerhead, varying the distance between the showerhead and the wafer, and increasing reflectivity of the showerhead in selected regions by employing an ring configured to emit thermal radiation to the showerhead which is then reflected back to the wafer.
    Type: Application
    Filed: December 22, 2011
    Publication date: June 27, 2013
    Applicant: Intermolecular, Inc.
    Inventors: Martin Romero, Jason Wright
  • Patent number: 8470697
    Abstract: A method of forming a p-type compound semiconductor layer includes increasing a temperature of a substrate loaded into a reaction chamber to a first temperature. A source gas of a Group III element, a source gas of a p-type impurity, and a source gas of nitrogen containing hydrogen are supplied into the reaction chamber to grow the p-type compound semiconductor layer. Then, the supply of the source gas of the Group III element and the source gas of the p-type impurity is stopped and the temperature of the substrate is lowered to a second temperature. The supply of the source gas of nitrogen containing hydrogen is stopped and drawn out at the second temperature, and the temperature of the substrate is lowered to room temperature using a cooling gas. Accordingly, hydrogen is prevented from bonding to the p-type impurity in the p-type compound semiconductor layer.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: June 25, 2013
    Assignee: Seoul Opto Device Co., Ltd.
    Inventors: Ki Bum Nam, Hwa Mok Kim, James S. Speck
  • Patent number: 8470678
    Abstract: A method for inducing a tensile stress in a channel of a field effect transistor (FET) includes forming a nitride film over the FET; forming a contact hole to the FET through the nitride film; and performing ultraviolet (UV) curing of the nitride film after forming the contact hole to the FET through the nitride film, wherein the UV cured nitride film induces the tensile stress in the channel of the FET.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: June 25, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ming Cai, Dechao Guo, Chun-chen Yeh, Pranita Kulkarni
  • Patent number: 8466074
    Abstract: A method for processing a substrate includes generating a first laser beam, splitting the first laser beam into a plurality of second laser beams, focusing the split second laser beams on a plane in the substrate parallel to a main surface of the substrate, and performing surface separation of the substrate along the plane.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: June 18, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-il Cho, Ho-tae Jin, Heui-seog Kim, Seon-ju Oh
  • Patent number: 8465991
    Abstract: A method for the ultraviolet (UV) treatment of carbon-containing low-k dielectric and associated apparatus enables process induced damage repair. The methods of the invention are particularly applicable in the context of damascene processing to recover lost low-k property of a dielectric damaged during processing, either pre-metallization, post-planarization, or both. UV treatments can include an exposure of the subject low-k dielectric to a constrained UV spectral profile and/or chemical silylating agent, or both.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: June 18, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Bhadri N. Varadarajan, Kevin M. McLaughlin, Bart van Schravendijk
  • Publication number: 20130146949
    Abstract: The embodiments of processes and structures described above provide mechanisms for improving mobility of carriers. The dislocations in the source and drain regions and the strain created by the doped epitaxial materials next to the channel region of a transistor both contribute to the strain in the channel region. As a result, the device performance is improved.
    Type: Application
    Filed: December 13, 2011
    Publication date: June 13, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Hsiung TSAI, Tsan-Chun WANG, Su-Hao LIU, Tsz-Mei KWOK, Chii-Meng WU
  • Patent number: 8461061
    Abstract: A method of supporting a plurality of planar substrates in a tube shaped furnace for conducting a thermal treatment process is disclosed. The method uses a boat fixture having a base frame including two length portions and a first width portion, a second width portion, and one or more middle members connected between the two length portions. Additionally, the method includes mounting a removable first grooved rod respectively on the first width portion, the second width portion, and each of the one or more middle members, each first grooved rod having a first plurality of grooves characterized by a first spatial configuration. The method further includes inserting one or two substrates of a plurality of planar substrates into each groove in the boat fixture separated by a distance.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: June 11, 2013
    Assignee: Stion Corporation
    Inventors: Paul Alexander, Jurg Schmitzberger, Ashish Tandon, Robert D. Wieting
  • Patent number: 8461033
    Abstract: A light-emission output of a flash lamp for performing a light-irradiation heat treatment on a substrate in which impurities are implanted is increased up to a target value L1 over a period of time from 1 to 100 milliseconds, is kept for 5 to 100 milliseconds within a fluctuation range of plus or minus 30% from the target value L1, and is then attenuated from the target value L1 to zero over a period of time from 1 to 100 milliseconds. That is, compared with conventional flash lamp annealing, the light-emission output of the flash lamp is increased more gradually, is kept to be constant for a certain period of time, and is then decreased more gradually. As a result, a total heat amount of a surface of the substrate increases compared with the conventional case, but a surface temperature thereof rises more gradually and then drops more gradually compared with the conventional case.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: June 11, 2013
    Assignee: Dainippon Screen Mfg. Co., Ltd.
    Inventor: Shinichi Kato
  • Patent number: 8461553
    Abstract: An improved method of producing solar cells utilizes a mask which is fixed relative to an ion beam in an ion implanter. The ion beam is directed through a plurality of apertures in the mask toward a substrate. The substrate is moved at different speeds such that the substrate is exposed to an ion dose rate when the substrate is moved at a first scan rate and to a second ion dose rate when the substrate is moved at a second scan rate. By modifying the scan rate, various dose rates may be implanted on the substrate at corresponding substrate locations. This allows ion implantation to be used to provide precise doping profiles advantageous for manufacturing solar cells.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: June 11, 2013
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Nicholas P. T. Bateman, Steven M. Anella, Benjamin B. Riordon, Atul Gupta