Compound Semiconductor Patents (Class 438/93)
  • Publication number: 20040195518
    Abstract: The present invention relates to an ultraviolet detector and manufacture method thereof, in which a buffer layer is formed on a baseplate and a P-type GaN layer is formed on the baseplate by using epitaxial method. By availing ion-distribution-and-vegetation technology, a first N-type GaN layer is vegetated and invested in the P-type GaN layer by distributing and vegetating Si+ ions in that layer, and a second N-type GaN layer having a thicker ion concentration is invested in the N-type GaN layer. Finally, an annular and a circular metallic layer are formed between the P-type GaN layer and the first N-type GaN layer as well as inside the second N-type GaN layer, respectively, to serve for respective ohmic contact layers. The present invention is characterized in that an incident light can project upon a depletion layer of the GaN planar structure to have the detection efficiency significantly improved.
    Type: Application
    Filed: July 19, 2003
    Publication date: October 7, 2004
    Inventors: Gou-Chung Chi, Iinn-Kong Sheu, Meng-Che Chen, Min-Lum Lee
  • Patent number: 6800499
    Abstract: A high-sensitivity Pd/InP hydrogen sensor was made by a) forming an n-type or p-type semiconductor film on a semiconductor substrate; b) forming a patterned first metal electrode on the semiconductor film, wherein the first metal electrode forms an Ohmic contact with the semiconductor film; and c) forming a second metal electrode on the semiconductor film, the second metal electrode being isolated from the first metal electrode, wherein the second metal electrode forms a Schottky contact with the semiconductor film, wherein a thickness of the second metal electrode and a material of which the second metal electrode is made enable a Schottky barrier height of the Schottky contact to decrease when hydrogen contacts the second metal electrode. The second metal electrode can be physical vapor deposited or electroless plated.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: October 5, 2004
    Assignee: National Science Council
    Inventors: Huey-Ing Chen, Wen-Chau Liu, Yen-I Chou, Chin-Yi Chu, Hsi-Jen Pan
  • Publication number: 20040185599
    Abstract: A method for fabricating a semiconductor component is based on a nitride compound semiconductor. In a first step of the method, provision is made of a semiconductor body containing at least one nitride compound semiconductor. In a second step, a metal layer is applied to the surface of the semiconductor body. Afterward, in a third step, the semiconductor body is patterned, a part of the metal layer and parts of the underlying semiconductor body are removed.
    Type: Application
    Filed: March 29, 2004
    Publication date: September 23, 2004
    Inventors: Volker Harle, Alfred Lell, Andreas Weimer
  • Patent number: 6790701
    Abstract: A multi-wavelength semiconductor image sensor comprises a p-type Hg0.7Cd0.3Te photo-absorbing layer formed on a single crystal CdZnTe substrate, a CdTe isolation layer deposited on the photo-absorbing layer, a p-type Hg0.77Cd0.23Te photo-absorbing layer deposited on the CdTe isolation layer, n+ regions which are formed in these photo-absorbing layers and form a pn-junction with each of these photo-absorbing layers, an indium electrode connected to each of these n+ regions and a ground electrode connected to the photo-absorbing layer, the semiconductor isolation layer being electrically isolated from the photo-absorbing layer.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: September 14, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keitaro Shigenaka, Fumio Nakata
  • Patent number: 6787385
    Abstract: A method of combining group III elements with group V elements that incorporates at least nitrogen from a nitrogen halide for use in semiconductors and in particular semiconductors in photovoltaic cells.
    Type: Grant
    Filed: February 5, 2003
    Date of Patent: September 7, 2004
    Assignee: Midwest Research Institute
    Inventors: Greg D. Barber, Sarah R. Kurtz
  • Publication number: 20040157358
    Abstract: A group III nitride semiconductor film involving few lattice defects and having a large thickness, and a process for making the film are disclosed. Dry-etching is conducted while a quartz substrate and a group III nitride semiconductor are placed on the top of a lower electrode. Nano-pillars (50) are formed on the top of the group III nitride semiconductor (101). Another group III nitride semiconductor film (51) is deposited on the nano-pillars (50).
    Type: Application
    Filed: April 1, 2004
    Publication date: August 12, 2004
    Inventors: Kazumasa Hiramatsu, Hideto Miyake, Harumasa Yoshida, Tatsuhiro Urushido, Yusuke Terada
  • Patent number: 6770508
    Abstract: An ohmic electrode for an SiC semiconductor includes a p-type Si layer formed on the surface of a p-type SiC semiconductor, and a metal silicide layer formed on the surface of the Si layer, the metal silicide layer being formed from a metal silicide such as PtSi. The p-type Si layer is preferably formed from p-type Si having a carrier concentration equal to or higher than that of the aforementioned p-type SiC. Preferably, the ohmic electrode is formed as follows: deposition of Si is performed; deposition of a metal silicide is performed by means of laser ablation; laser irradiation is performed to thereby improve ohmic properties and enhance adhesion between the result deposition layer and the p-type SiC semiconductor, and then further deposition of the metal silicide is performed by means of laser ablation.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: August 3, 2004
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Kenshiro Nakashima, Yasuo Okuyama, Hitoshi Yokoi, Takafumi Oshima
  • Patent number: 6768048
    Abstract: Methods for formulating and depositing a sol-gel coating onto a surface of a solar cell to provide improved radiation damage resistance. The sol-gel contains a solvent, alkoxyzirconium and an organosilane, with an organic acid catalyst and optionally a surfactant. The sol-gel coating can be deposited by spraying and the sol-gel coating is cured. The invention reduces manufacturing steps and overall weight of the solar cell array.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: July 27, 2004
    Assignee: The Boeing Company
    Inventors: Suzanne L. B. Woll, Kay Y. Blohowiak, David E. Harden, Harold G. Pippin, Larry K. Olli
  • Publication number: 20040142504
    Abstract: The subject invention comprises a type-II superlattice photon detector and focal planes array and method for making. The device may be either a binary or tertiary system with a type-II band alignment.
    Type: Application
    Filed: January 21, 2003
    Publication date: July 22, 2004
    Applicant: MP Technologies, LLC
    Inventor: Manijeh Razeghi
  • Patent number: 6756325
    Abstract: Several methods for producing an active region for a long wavelength light emitting device are disclosed. In one embodiment, the method comprises placing a substrate in an organometallic vapor phase epitaxy (OMVPE) reactor, the substrate for supporting growth of an indium gallium arsenide nitride (InGaAsN) film, supplying to the reactor a group-III-V precursor mixture comprising arsine, dimethylhydrazine, alkyl-gallium, alkyl-indium and a carrier gas, where the arsine and the dimethylhydrazine are the group-V precursor materials and where the percentage of dimethylhydrazine substantially exceeds the percentage of arsine, and pressurizing the reactor to a pressure at which a concentration of nitrogen commensurate with light emission at a wavelength longer than 1.2 um is extracted from the dimethylhydrazine and deposited on the substrate.
    Type: Grant
    Filed: May 7, 2002
    Date of Patent: June 29, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: David P. Bour, Tetsuya Takeuchi, Ashish Tandon, Ying-Lan Chang, Michael R. T. Tan, Scott Corzine
  • Publication number: 20040121507
    Abstract: A method of making a semiconductor device having a predetermined epitaxial region, such as an active region, with reduced defect density includes the steps of: (a) forming a dielectric cladding region on a major surface of a single crystal body of a first material; (b) forming a first opening that extends to a first depth into the cladding region; (c) forming a smaller second opening, within the first opening, that extends to a second depth greater than the first depth and that exposes an underlying portion of the major surface of the single crystal body; (d) epitaxially growing regions of a second semiconductor material in each of the openings and on the top of the cladding region; (e) controlling the dimensions of the second opening so that defects are confined to the epitaxial regions grown within the second opening and on top of the cladding region, a first predetermined region being located within the first opening and being essentially free of defects; (D planarizing the top of the device to remove all
    Type: Application
    Filed: June 3, 2003
    Publication date: June 24, 2004
    Inventors: Jeffrey Devin Bude, Malcolm Carroll, Clifford Alan King
  • Publication number: 20040118448
    Abstract: Nanocomposite photovoltaic devices are provided that generally include semiconductor nanocrystals as at least a portion of a photoactive layer. Photovoltaic devices and other layered devices that comprise core-shell nanostructures and/or two populations of nanostructures, where the nanostructures are not necessarily part of a nanocomposite, are also features of the invention. Varied architectures for such devices are also provided including flexible and rigid architectures, planar and non-planar architectures and the like, as are systems incorporating such devices, and methods and systems for fabricating such devices. Compositions comprising two populations of nanostructures of different materials are also a feature of the invention.
    Type: Application
    Filed: September 4, 2003
    Publication date: June 24, 2004
    Applicant: NANOSYS, INC.
    Inventors: Erik Scher, Mihai A. Buretea, Calvin Chow, Stephen Empedocles, Andreas Meisel, J. Wallace Parce
  • Publication number: 20040118451
    Abstract: An alloy having a large band gap range is used in a multijunction solar cell to enhance utilization of the solar energy spectrum. In one embodiment, the alloy is In1-xGaxN having an energy bandgap range of approximately 0.7 eV to 3.4 eV, providing a good match to the solar energy spectrum. Multiple junctions having different bandgaps are stacked to form a solar cell. Each junction may have different bandgaps (realized by varying the alloy composition), and therefore be responsive to different parts of the spectrum. The junctions are stacked in such a manner that some bands of light pass through upper junctions to lower junctions that are responsive to such bands.
    Type: Application
    Filed: May 27, 2003
    Publication date: June 24, 2004
    Inventors: Wladyslaw Walukiewicz, Kin Man Yu, Junqiao Wu, William J. Schaff
  • Patent number: 6750486
    Abstract: A semiconductor device with p-channel and n-channel field effect devices formed on a common substrate, where the drain and source regions of the n-channel field effect device are formed within a silicon epitaxial layer formed on a silicon layer germanium relax which is formed on a silicon germanium buffer layer with a graduated germanium concentration. Additionally, drain and source regions of the p-channel field effect device are formed within a silicon-germanium compound layer formed on the substrate and the silicon epitaxial cap layer formed on the silicon-germanium compound layer.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: June 15, 2004
    Assignee: Sony Corporation
    Inventors: Minoru Sugawara, Takashi Noguchi
  • Patent number: 6750075
    Abstract: A heterostructure or multilayer semiconductor structure having lattice matched layers with different bandgaps is grown by MOCVD. More specifically, a wide bandgap material such as AlInSb or GaInSb is grown on a substrate to form a lower-contact layer. An n-type active layer is lattice matched to the lower contact layer. The active layer should be of a narrow bandgap material, such as InAsSb, InTlSb, InBiSb, or InBiAsSb. A p-type upper contact layer is then grown on the active layer and a multi-color infrared photodetector has been fabricated.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: June 15, 2004
    Inventor: Manijeh Razeghi
  • Publication number: 20040103936
    Abstract: A metal chalcogenide composite nano-particle comprising a metal capable of forming p-type semiconducting chalcogenide nano-particles and a metal capable of forming n-type semiconducting chalcogenide nano-particles, wherein at least one of the metal chalcogenides has a band-gap between 1.0 and 2.9 eV and the concentration of the metal capable of forming p-type semiconducting chalcogenide nano-particles is at least 5 atomic percent of the metal and is less than 50 atomic percent of the metal; a dispersion thereof; a layer comprising the nano-particles; and a photovoltaic device comprising the layer.
    Type: Application
    Filed: September 11, 2003
    Publication date: June 3, 2004
    Applicant: AGFA-GEVAERT
    Inventor: Hieronymus Andriessen
  • Publication number: 20040087056
    Abstract: A thin-film opto-electronic device on a conductive silicon-containing substrate includes a sequence of layers. The layers include a layer of a porous medium preferably a porous silicon, on a substrate. The porous layer has both light diffusing and light reflecting properties. In addition, a non-porous layer is located on said porous silicon layer, with at least one first region and at least one second region being in said non-porous layer. The first region is of a first conductivity type acting as a light absorber and the second region has a conductivity of a second type, different from said first conductivity type. The sequence of layers is such that optical confinement is realised in the device.
    Type: Application
    Filed: August 19, 2003
    Publication date: May 6, 2004
    Inventors: Lieven Stalmans, Jef Poortmans, Matty Caymax, Khalid Said, Johan Nijs
  • Patent number: 6720200
    Abstract: Using a mask opening a gate region, an undoped GaAs layer is selectively etched with respect to an undoped Al0.2Ga0.8As layer by dry etching with introducing a mixture gas of a chloride gas containing only chlorine and a fluoride gas containing only fluorine (e.g. BCl3+SF6 or so forth). By about 100% over-etching is performed for the undoped GaAs layer, etching (side etching) propagates in transverse direction of the undoped GaAs layer. With using the mask, a gate electrode of WSi is formed. Thus, a gap in a width of about 20 nm is formed by etching in the transverse direction on the drain side of the gate electrode. By this, a hetero junction FET having reduced fluctuation of characteristics of an FET, such as a threshold value, lower a rising voltage and higher breakdown characteristics.
    Type: Grant
    Filed: May 22, 2001
    Date of Patent: April 13, 2004
    Assignee: NEC Corporation
    Inventors: Keiko Yamaguchi, Naotaka Iwata
  • Publication number: 20040065363
    Abstract: A method of disordering a layer of an optoelectronic device including; growing a plurality of lower layers; introducing an isoelectronic surfactant; growing a layer; allowing the surfactant to desorb; and growing subsequent layers all performed at a low pressure of 25 torr.
    Type: Application
    Filed: October 2, 2002
    Publication date: April 8, 2004
    Applicant: The Boeing Company
    Inventors: Christopher M. Fetzer, James H. Ermer, Richard R. King, Peter C. Colter
  • Patent number: 6709883
    Abstract: A light emitting diode (LED) and method of making the same are disclosed. The present invention uses a layer of elastic transparent adhesive material to bond a transparent substrate and a LED epitaxial structure having a light-absorbing substrate. The light absorbing substrate is then removed to form a LED having a transparent substrate. By the use of the transparent substrate, the light emitting efficiency of the LED can be significantly improved.
    Type: Grant
    Filed: April 6, 2001
    Date of Patent: March 23, 2004
    Assignee: United Epitaxy Co., Ltd.
    Inventors: Kuang-Neng Yang, Tzer-Perng Chen, Chih-Sung Chang
  • Publication number: 20040053438
    Abstract: A method of epitaxially growing a SiC film on a Si substrate, including:
    Type: Application
    Filed: June 3, 2003
    Publication date: March 18, 2004
    Inventors: Yoshihisa Abe, Shunichi Suzuki, Hideo Nakanishi, Kazutaka Terashima, Juno Komiyama
  • Patent number: 6706959
    Abstract: A photoelectric conversion element is disposed in each of a plurality of recesses of a support. Light reflected by the inside surface of the recess shines on the photoelectric conversion element. The photoelectric conversion element has an approximately spherical shape and has the following structure. The outer surface of a center-side n-type amorphous silicon (a-Si) layer is covered with a p-type amorphous SiC (a-SiC) layer having a wider optical band gap than a-Si does, whereby a pn junction is formed. A first conductor of the support is connected to the p-type a-SiC layer of the photoelectric conversion element at the bottom or its neighborhood of the recess. A second conductor, which is insulated from the first conductor by an insulator, of the support is connected to the n-type a-Si layer of the photoelectric conversion element.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: March 16, 2004
    Assignee: Clean Venture 21 Corporation
    Inventors: Yoshihiro Hamakawa, Mikio Murozono, Hideyuki Takakura
  • Patent number: 6680495
    Abstract: A structure with an optically active layer embedded in a Si wafer, such that the outermost epitaxial layer exposed to the CMOS processing equipment is always Si or another CMOS-compatible material such as SiO2. Since the optoelectronic layer is completely surrounded by Si, the wafer is fully compatible with standard Si CMOS manufacturing. For wavelengths of light longer than the bandgap of Si (1.1 &mgr;m), Si is completely transparent and therefore optical signals can be transmitted between the embedded optoelectronic layer and an external waveguide using either normal incidence (through the Si substrate or top Si cap layer) or in-plane incidence (edge coupling).
    Type: Grant
    Filed: August 1, 2001
    Date of Patent: January 20, 2004
    Assignee: AmberWave Systems Corporation
    Inventor: Eugene A. Fitzergald
  • Publication number: 20040009626
    Abstract: A method of fabricating a Si1-XGeX film on a silicon substrate includes preparing a silicon substrate; epitaxially depositing a Si1-XGeX layer on the silicon substrate forming a Si1-XGeX/Si interface there between; amorphizing the Si1-XGeX layer at a temperature greater than Tc to form an amorphous, graded SiGe layer; and annealing the structure at a temperature of between about 650° C. to 1100° C. for between about ten seconds and sixty minutes to recrystallize the SiGe layer.
    Type: Application
    Filed: July 11, 2002
    Publication date: January 15, 2004
    Inventors: Douglas J. Tweet, Sheng Teng Hsu, Jer-shen Maa, Jong-Jan Lee
  • Publication number: 20030173602
    Abstract: The present invention discloses a light-emitting diode with enhanced brightness and a method for fabricating the same. The light-emitting diode comprises: an epitaxial LED structure having at least one lighting-emitting active layer with a plurality of spacers inside the lighting-emitting active layer; at least one conductive contact, formed on the bottom surface where no spacer is formed inside the lighting-emitting active layer; a transparent material layer formed in the spacers; an adhesion layer formed between the transparent material layer and a permanent substrate; a bottom electrode formed on the bottom surface of the permanent substrate; and an opposed electrode formed on the top surface of the epitaxial LED structure.
    Type: Application
    Filed: March 12, 2002
    Publication date: September 18, 2003
    Inventors: Jung-Kuei Hsu, Hsueh-Chih Yu, Chia-Liang Hsu, Hung-Yuan Lu, Yen-Hu Chu, Chui-Chuan Chang, Kwang-Ru Wang, Chang-Da Tsai, San Bao Lin, Yung-Chiang Hwang, Ming-Der Lin
  • Publication number: 20030155584
    Abstract: A method of combining group III elements with group V elements that incorporates at least nitrogen from a nitrogen halide for use in semiconductors and in particular semiconductors in photovoltaic cells.
    Type: Application
    Filed: February 5, 2003
    Publication date: August 21, 2003
    Inventors: Greg D. Barber, Sarah R. Kurtz
  • Publication number: 20030155586
    Abstract: A layer comprising silicon oxide (SiO2) is formed on (111) plane of a silicon (Si) substrate in a striped pattern which is longer in the [1-10] axis direction perpendicular to the [110] axis direction. Then a group III nitride compound semiconductor represented by a general formula AlxGayIn1−x−yN (0≦x≦1, 0≦y≦1, 0≦x+y≦1) is laminated thereon. The group III nitride compound semiconductor represented by a general formula AlxGayIn1−x−yN (0≦x≦1, 0≦y≦1, 0≦x+y≦1) grows epitaxially on the substrate-exposed regions B which are not covered by the SiO2 layer, and grows epitaxially on the SiO2 layer in lateral direction from the regions B. Consequently, a group III nitride compound semiconductor having no dislocations can be obtained.
    Type: Application
    Filed: March 7, 2003
    Publication date: August 21, 2003
    Applicant: Toyoda Gosei Co., Ltd.
    Inventors: Norikatsu Koide, Hisaki Kato
  • Patent number: 6607829
    Abstract: Tellurium-containing nanocrystallites are produced by injection of a precursor into a hot coordinating solvent, followed by controlled growth and annealing. Nanocrystallites may include CdTe, ZnTe, MgTe, HgTe, or alloys thereof. The nanocrystallites can photoluminesce with quantum efficiencies as high as 70%.
    Type: Grant
    Filed: July 26, 2000
    Date of Patent: August 19, 2003
    Assignee: Massachusetts Institute of Technology
    Inventors: Moungi G. Bawendi, Frederic V. Mikulec, Sungjee Kim
  • Publication number: 20030153117
    Abstract: The present invention relates to an optical integrated circuit device, a fabrication method of the same and a module of an optical communication transmission and receiving apparatus using the same. The optical integrated circuit device comprises a semiconductor substrate, an active layer formed on an upper surface of the semiconductor substrate, a first current disconnection layer formed on an upper surface of the semiconductor substrate at both sides of the active later, a second current disconnection layer formed on an upper surface of the first current disconnection layer, and a convex portion formed on an upper portion of the active layer and an upper surface of the second current disconnection layer.
    Type: Application
    Filed: January 14, 2003
    Publication date: August 14, 2003
    Applicant: ILJIN Corporation, Inc.
    Inventor: Ki Chul Shin
  • Publication number: 20030137018
    Abstract: A compound semiconductor structure is provided, which includes a GaAs-based supporting semiconductor structure having a surface on which a dielectric material is to be formed. A first layer of gallium oxide is located on the surface of the supporting semiconductor structure to form an interface therewith. A second layer of a Ga—Gd oxide is disposed on the first layer. The GaAs-based supporting semiconductor structure may be a GaAs-based heterostructure such as an at least partially completed semiconductor device (e.g., a metal-oxide field effect transistor, a heterojunction bipolar transistor, or a semiconductor laser). In this manner a dielectric layer structure is provided which has both a low defect density at the oxide-GaAs interface and a low oxide leakage current density because the dielectric structure is formed from a layer of Ga2O3 followed by a layer of Ga—Gd-oxide.
    Type: Application
    Filed: January 18, 2002
    Publication date: July 24, 2003
    Inventors: Matthias Passlack, Nicholas William Medendorp
  • Patent number: 6566595
    Abstract: A solar cell having a p-type semiconductor layer and an n-type semiconductor layer made of a first compound semiconductor material, and a semiconductor layer sandwiched between the p-type semiconductor layer and the n-type semiconductor layer. The semiconductor layer includes at least a quantum well layer which is made of a second compound semiconductor material and has a plurality of projections of at least two different sizes.
    Type: Grant
    Filed: October 29, 2001
    Date of Patent: May 20, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yoshiyuki Suzuki
  • Patent number: 6562702
    Abstract: Provided is a method and apparatus for the production of a semiconductor device, the method and the apparatus producing a high quality and highly functional semiconductor device efficiently at low temperatures in a short time and also a high quality and highly functional semiconductor device produced by the method and apparatus. The semiconductor device is produced by forming a film of a nitride compound on a substrate having heat resistance at 600° C. or less, wherein the nitride compound includes one or more elements selected from group IIIA elements of the periodic table and a nitrogen atom and produces photoluminescence at the band edges at room temperature.
    Type: Grant
    Filed: January 31, 2001
    Date of Patent: May 13, 2003
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Shigeru Yagi
  • Patent number: 6552259
    Abstract: In this bypass-function added solar cell, a plurality of island-like p+ regions, which is third regions, are formed at a boundary between a p-type region and an n-type region layer constituting a substrate so that the p+ regions project into the region and the region and are separated away from the surface of the substrate. Therefore, in this solar cell, unlike prior art counterparts, the insulating film for isolating the p+ regions and the n electrodes constituting the np+ diode from one another is no longer necessary, thus allowing a reduction in manufacturing cost. As a result, a bypass-function added solar cell with a bypass-diode function added thereto can be provided with low cost and by simple process.
    Type: Grant
    Filed: October 18, 2000
    Date of Patent: April 22, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shigeyuki Hosomi, Tadashi Hisamatsu
  • Patent number: 6548751
    Abstract: A thin-film flexible solar cell built on a plastic substrate comprises a cadmium telluride p-type layer and a cadmium sulfide n-type layer sputter deposited onto a plastic substrate at a temperature sufficiently low to avoid damaging or melting the plastic and to minimize crystallization of the cadmium telluride. A transparent conductive oxide layer overlaid by a bus bar network is deposited over the n-type layer. A back contact layer of conductive metal is deposited underneath the p-type layer and completes the current collection circuit. The semiconductor layers may be amorphous or polycrystalline in structure.
    Type: Grant
    Filed: June 25, 2001
    Date of Patent: April 15, 2003
    Assignee: SolarFlex Technologies, Inc.
    Inventors: Lawrence H. Sverdrup, Jr., Norman F. Dessel, Adrian Pelkus
  • Publication number: 20030059972
    Abstract: The light-emitting device 100 has an ITO electrode layer 8 for applying drive voltage for light emission to a light emitting layer section 24, where the light from the light emitting layer section 24 is extracted as being passed through the ITO electrode layer 8. Between the light emitting layer section 24 and the ITO electrode layer 8, an electrode contact layer 7 composed of In-containing GaAs is located so as to contact with such ITO electrode layer 8, where occupied areas and unoccupied areas for the electrode contact layer 7 are arranged in a mixed manner on the contact interface with the transparent electrode layer 8. The electrode contact layer 7 can be obtained by annealing a stack 13, which comprises a GaAs layer 7″ formed on the light emitting layer section 24 and the ITO electrode layer 8 formed so as to contact with the GaAs layer 7″, to thereby allow In to diffuse from the ITO electrode layer to the GaAs layer 7″.
    Type: Application
    Filed: September 26, 2002
    Publication date: March 27, 2003
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Shunichi Ikeda, Masato Yamada, Nobuhiko Noto, Shinji Nozaki, Kazuo Uchida, Hiroshi Morisaki
  • Patent number: 6537845
    Abstract: A chemical surface deposition process for forming an ultra-thin semiconducting film of Group IIB-VIA compounds onto a substrate. This process eliminates particulates formed by homogeneous reactions in bath, dramatically increases the utilization of Group IIB species, and results in the formation of a dense, adherent film for thin film solar cells. The process involves applying a pre-mixed liquid coating composition containing Group IIB and Group VIA ionic species onto a preheated substrate. Heat from the substrate causes a heterogeneous reaction between the Group IIB and VIA ionic species of the liquid coating composition, thus forming a solid reaction product film on the substrate surface.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: March 25, 2003
    Inventors: Brian E. McCandless, William N. Shafarman
  • Publication number: 20030051752
    Abstract: In a photovoltaic cell having a photovoltaically active semiconductor material constituted by a plurality of metals or metal oxides, the photovoltaically active material is selected from a
    Type: Application
    Filed: August 27, 2002
    Publication date: March 20, 2003
    Inventors: Hans-Josef Sterzel, Klaus Kuhling
  • Patent number: 6524882
    Abstract: A nitride based III-V compound semiconductor doped with a p-type impurity is formed on a substrate made from sapphire. The substrate is then placed between a pair of RF electrodes, and a radio frequency field is applied between the RF electrodes. With this operation, electrons present in the compound semiconductor attack the bonding between the p-type impurity and hydrogen, to cut the bonding. The hydrogen atoms thus dissociated are released from the compound semiconductor, to thereby activate the p-type impurity. In this case, it is not required to heat the compound semiconductor by a heater or the like.
    Type: Grant
    Filed: April 3, 2001
    Date of Patent: February 25, 2003
    Assignee: Sony Corporation
    Inventors: Motonobu Takeya, Satoshi Taniguchi
  • Patent number: 6509203
    Abstract: In a semiconductor imaging device, the distance between the edge of a substrate and an edge-most charge collection contact is made as small as possible, preferably less than 500 &mgr;m and/or less than ⅓ of the substrate thickness. Additionally or alternatively, a passivation layer is placed between the edge-most portion of the contact and the substrate surface and/or a field shaping conductor adjacent to the surface. A field shaping region may also be arranged outside the edge of the substrate and may encircle each detector device, or it may encircle an arrangement of several devices. In such an arrangement, the spacing between adjacent detectors should be less than 500 &mgr;m. A shield may also be used to shield the edge of each detector, or the edge region of the arrangement of several detectors, from incident radiation. Such arrangements can reduce the effect of edge image deterioration caused by strong field non-uniformities at the detector edges.
    Type: Grant
    Filed: October 14, 1997
    Date of Patent: January 21, 2003
    Assignee: Simage, Oy
    Inventors: Konstantinos Evangelos Spartiotis, Miltiadis Evangelos Sarakinos, Tom Gunnar Schulman
  • Publication number: 20020189665
    Abstract: A photovoltaic cell exhibiting an overall conversion efficiency of at least 9.0% is prepared from a copper-indium-gallium-diselenide thin film. The thin film is prepared by simultaneously electroplating copper, indium, gallium, and selenium onto a substrate using a buffered electro-deposition bath. The electrodeposition is followed by adding indium to adjust the final stoichiometry of the thin film.
    Type: Application
    Filed: April 10, 2001
    Publication date: December 19, 2002
    Applicant: DAVIS, JOSEPH & NEGLEY
    Inventor: Raghu Nath Bhattacharya
  • Patent number: 6492239
    Abstract: An avalanche photodiode fabricating method with a simplified fabrication process and an improved reproducibility is disclosed.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: December 10, 2002
    Assignee: Samsung Electronic Co, LTD
    Inventors: Seung-Kee Yang, Dong-Soo Bang
  • Patent number: 6482672
    Abstract: A method for growing InxGa1−xAs epitaxial layer on a lattice mismatched InP substrate calls for depositing by organo-metallic vapor phase epitaxy, or other epitaxial layer growth technique, a plurality of discreet layers of InAsyP1−y over an InP substrate. These layers provide a buffer. Each succeeding buffer layer has a distinct composition which produces less than a critical amount of lattice mismatch relative to the preceding layer. An InxGa1−xAs epitaxial layer is grown over the buffer wherein 0.53≦x≦0.76. A resulting InGaAs structure comprises an InP substrate with at least one InAsP buffer layer sandwiched between the substrate and the InGaAs epitaxial layer. The buffer layer has a critical lattice mismatch of less than 1.3% relative to the substrate. Additional buffer layers will likewise have a lattice mismatch of no more than 1.3% relative to the preceding layer.
    Type: Grant
    Filed: November 5, 1998
    Date of Patent: November 19, 2002
    Assignee: Essential Research, Inc.
    Inventors: Richard W. Hoffman, David M. Wilt
  • Patent number: 6479312
    Abstract: By providing a nitrogen-doped low carrier concentration layer 13 having both of a donor concentration and an acceptor concentration controlled below 1×1016/cm3 at a p-n junction portion between an n-type GaP layer 12 and a p-type GaP layer 14, the luminance of the GaP light emitting device can be improved by as much as 20 to 30% over the conventional one. Suppressing the donor concentration and the acceptor concentration in the low carrier concentration layer 13 below 1×1016/cm3 inevitably gives a carrier concentration, which is expressed as a difference between both concentrations, lower than 1×1016/cm3 accordingly. The emission efficiency upon injection of electrons or holes can be improved by suppressing the concentration of the donor which serves as non-emissive center below 1×1016/cm3 to thereby extend the carrier lifetime; and by concomitantly suppressing the carrier concentration at a level significantly lower than that in the adjacent layers 12 and 14.
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: November 12, 2002
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Masato Yamada, Susumu Higuchi, Kousei Yumoto, Makoto Kawasaki, Ken Aihara
  • Patent number: 6476429
    Abstract: A power MOSFET includes an n−-drain layer, a drain contact layer disposed on a first side of the drain layer, a p-type base layer disposed on a second side of the drain layer, and an n-source layer disposed on the base layer. A gate electrode faces, through a gate insulating film, a channel region, which is part of the base layer between the drain and source layers. Source and drain electrodes are electrically connected to the source and drain contact layers, respectively. A plurality of hetero regions having a dielectric constant higher than that of the drain layer is disposed in the drain layer between the source and drain electrodes.
    Type: Grant
    Filed: April 11, 2001
    Date of Patent: November 5, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiro Baba
  • Patent number: 6465803
    Abstract: By using wafer fusion, various structures for photodetectors and photodetectors integrated with other electronics can be achieved. The use of silicon as a multiplication region and III—V compounds as an absorption region create photodetectors that are highly efficient and tailored to specific applications. Devices responsive to different regions of the optical spectrum, or that have higher efficiencies are created.
    Type: Grant
    Filed: June 20, 2000
    Date of Patent: October 15, 2002
    Assignee: The Regents of the University of California
    Inventors: John E. Bowers, Aaron R. Hawkins
  • Publication number: 20020135034
    Abstract: A multi-wavelength semiconductor image sensor comprises a p-type Hg0.7Cd0.3Te photo-absorbing layer formed on a single crystal CdZnTe substrate, a CdTe isolation layer deposited on the photo-absorbing layer, a p-type Hg0.77Cd0.23Te photo-absorbing layer deposited on the CdTe isolation layer, n+ regions which are formed in these photo-absorbing layers and form a pn-junction with each of these photo-absorbing layers, an indium electrode connected to each of these n+ regions and a ground electrode connected to the photo-absorbing layer, the semiconductor isolation layer being electrically isolated from the photo-absorbing layer.
    Type: Application
    Filed: August 31, 1999
    Publication date: September 26, 2002
    Inventors: KEITARO SHIGENAKA, FUMIO NAKATA
  • Patent number: 6441301
    Abstract: A solar cell with good characteristics and high reliability is provided that includes a semiconductor comprising at least one element from each of groups Ib, IIIb, and VIb. A method of manufacturing the same also is provided. The solar cell includes a conductive base, a first insulating layer formed on one principal plane of the base, a second insulating layer formed on a second principal plane of the base, and a light-absorption layer disposed above the first insulating layer. The light-absorption layer is formed of a semiconductor comprising at least one element from each of groups Ib, IIIb, and VIb.
    Type: Grant
    Filed: March 12, 2001
    Date of Patent: August 27, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takuya Satoh, Takayuki Negami, Shigeo Hayashi, Yasuhiro Hashimoto, Shinichi Shimakawa
  • Patent number: 6414340
    Abstract: The field effect device consisting of a substrate, a conducting backplane formed in the substrate, a source and a drain disposed above the conductive backplane, a gate insultatively disposed above the substrate between the source and drain, and a backgate contact electrically coupled to the conducting backplane.
    Type: Grant
    Filed: November 4, 1999
    Date of Patent: July 2, 2002
    Assignee: Raytheon Company
    Inventor: Berinder Brar
  • Publication number: 20020062858
    Abstract: A solar energy device comprising: a substrate; a photovoltaic layer on said substrate; a back conductor in contact with said substrate; a grid conductor in contact with said substrate; said photovoltaic layer being of a material selected from the class consisting of: monoclinic zinc diphosphide (also referred to as beta zinc diphosphide and indicated by &bgr;-ZnP2); copper diphosphide (CuP2); magnesium tetraphosphide (MgP4); &ggr;-iron tetraphosphide (&ggr;-FeP4) and mixed crystals formed from these four materials.
    Type: Application
    Filed: October 29, 2001
    Publication date: May 30, 2002
    Inventor: Thomas Mowles
  • Patent number: 6395573
    Abstract: Provided with a laser diode and its fabricating method including the steps of: sequentially forming a first conductivity type clad layer, an active layer, a second conductivity type first clad layer, an etch stop layer, a second conductivity type second clad layer, a second conductivity type InGaP layer, and a second conductivity type GaAs layer, on a first conductivity type substrate; forming an insulating layer on the second conductivity type GaAs layer and patterning it, exposing a defined region of the second conductivity type GaAs layer; performing a reactive ion etching using the patterned insulating layer as a mask, etching the second conductivity type GaAs layer, the second conductivity type InGaP layer, and the second conductivity type second clad layer to a specified depth and remaining part of the second conductivity type second clad layer; forming a photoresist on the whole surface including the insulating layer and patterning it, exposing the residual second conductivity type second clad layer; p
    Type: Grant
    Filed: July 26, 2000
    Date of Patent: May 28, 2002
    Assignee: LG Electronics Inc.
    Inventors: Jun Ho Jang, Kang Hyun Sung