Compound Semiconductor Patents (Class 438/93)
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Patent number: 7485512Abstract: A method of compensating resistivity of a near-surface region of a substrate includes epitaxially growing a buffer layer on the substrate, wherein the buffer is grown as having a dopant concentration as dependent on resistivity and conductivity of the substrate, so as to deplete residual or excess charge within the near-surface region of the substrate. The dopant profile of the buffer layer be smoothly graded, or may consist of sub-layers of different dopant concentration, to also provide a highly resistive upper portion of the buffer layer ideal for subsequent device growth. Also, the buffer layer may be doped with carbon, and aluminum may be used to getter the carbon during epitaxial growth.Type: GrantFiled: June 26, 2006Date of Patent: February 3, 2009Assignee: Cree, Inc.Inventors: Christopher Harris, Thomas Gehrke, T. Warren Weeks, Jr., Cem Basceri, Elif Berkman
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Publication number: 20090014764Abstract: An embodiment of an image sensor comprising photosensitive cells, each photosensitive cell comprising at least one charge storage means formed at least partly in a substrate of a semiconductor material. The substrate comprises, for at least one first photosensitive cell, a portion of a first silicon and germanium alloy having a first germanium concentration, possibly zero, and for at least one second photosensitive cell, a portion of a second silicon and germanium alloy having a second germanium concentration, non-zero, greater than the first germanium concentration.Type: ApplicationFiled: July 10, 2008Publication date: January 15, 2009Applicants: STMICROELECTRONICS SA, STMICROELECTRONICS CROLLES 2 SASInventors: Perceval COUDRAIN, Philippe CORONEL, Xavier BELREDON
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Publication number: 20080315342Abstract: Device and method of forming a device in which a substrate (10) is fabricated with at least part of an electronic circuit for processing signals. A bulk single crystal material (14) is formed on the substrate, either directly on the substrate (10) or with an intervening thin film layer or transition region (12). A particular application of the device is for a radiation detector.Type: ApplicationFiled: December 21, 2006Publication date: December 25, 2008Applicant: DURHAM SCIENTIFIC CRYSTALS LIMITEDInventors: Arnab Basu, Max Robinson, Ben Cantwell, Andy Brinkman
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Publication number: 20080254566Abstract: A surface-emitting semiconductor laser device includes a semi-insulating substrate, a layer structure with a bottom multilayer reflector, an n-type cladding layer, an active layer structure for emitting laser, a p-type cladding layer and a top multilayer reflector with a dielectric material, consecutively formed on the semi-insulating substrate, the active layer structure, the p-type cladding layer and the top multilayer reflector, configuring a mesa post formed on a portion of the n-type cladding layer, the p-type cladding layer or the p-type multilayer reflector. The surface-emitting semiconductor laser includes a p-side electrode formed on another portion of the p-type cladding layer, and an n-side electrode formed on another portion of the n-type cladding layer. The n-side electrode includes a substantially uniform Au film and AuGeNi film or AuGe film consecutively formed on the n-type cladding layer, and an alloy is formed between said Au film and said AuGeNi film or AuGe film.Type: ApplicationFiled: April 15, 2008Publication date: October 16, 2008Applicant: THE FURUKAWA ELECTRIC CO., LTD.Inventors: Noriyuki YOKOUCHI, Norihiro Iwai
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Publication number: 20080241987Abstract: Devices, solar cell structures, and methods of fabrication thereof, are disclosed.Type: ApplicationFiled: June 12, 2008Publication date: October 2, 2008Applicant: Georgia Tech Research CorporationInventors: Ajeet Rohatgi, Abasifreke Ebong, Vijay Yelundur
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Publication number: 20080241988Abstract: Devices, solar cell structures, and methods of fabrication thereof, are disclosed.Type: ApplicationFiled: June 12, 2008Publication date: October 2, 2008Applicant: Georgia Tech Research CorporationInventors: Ajeet Rohatgi, Abasifreke Ebong, Vijay Yelundur
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Patent number: 7422927Abstract: The invention includes methods of depositing silver onto a metal selenide-comprising surface, and methods of forming a resistance variable device. In one implementation, a method of depositing silver onto a metal selenide-comprising surface includes providing a deposition chamber comprising a sputtering target and a substrate to be depositing upon. The target comprises silver, and the substrate comprises an exposed surface comprising metal selenide. Gaseous cesium is flowed to the target and a bombarding inert sputtering species is flowed to the target effective to sputter negative silver ions from the target. The sputtered negative silver ions are flowed to the exposed metal selenide-comprising surface effective to deposit a continuous and completely covering silver film on the exposed metal selenide of the substrate.Type: GrantFiled: June 23, 2006Date of Patent: September 9, 2008Assignee: Micron Technology, Inc.Inventor: Allen McTeer
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High Performance CdxZn1-xTe X-Ray and Gamma Ray Radiation Detector and Method of Manufacture Thereof
Publication number: 20080203514Abstract: The present invention is a radiation detector that includes a crystalline substrate formed of a II-VI compound and a first electrode covering a substantial portion of one surface of the substrate. A plurality of second, segmented electrodes is provided in spaced relation on a surface of the substrate opposite the first electrode. A passivation layer is disposed between the second electrodes on the surface of the substrate opposite the first electrode. The passivation layer can also be positioned between the substrate and one or both of the first electrode and each second electrode. The present invention is also a method of forming the radiation detector.Type: ApplicationFiled: May 16, 2006Publication date: August 28, 2008Applicant: II-VI INCORPORATEDInventor: Csaba Szeles -
Publication number: 20080202577Abstract: Photovoltaic modules can be formed with a plurality of solar cells having different sized structures to improve module performance. The sized can be determined dynamically based on estimated properties of the semiconductor so that the current outputs of the cells in the module are more similar to each other. The modules can produce higher power relative to modules with similar equal sized cells that do not produce matched currents. Appropriate dynamic processing methods are described that include processing steps that provide adjustments of the processing according to the dynamic adjustments in cell designs.Type: ApplicationFiled: February 15, 2008Publication date: August 28, 2008Inventor: Henry Hieslmair
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Patent number: 7416909Abstract: Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be formed with little or no consumption of surface silicon. These oxides, such as screening oxide and pad oxide, are formed by deposition onto, rather than reaction with and consumption of the surface layer. Alternatively, oxide deposition is preceded by a thermal oxidation step of short duration, e.g., rapid thermal oxidation. Here, the short thermal oxidation consumes little surface Si, and the Si/oxide interface is of high quality. The oxide may then be thickened to a desired final thickness by deposition. Furthermore, the thin thermal oxide may act as a barrier layer to prevent contamination associated with subsequent oxide deposition.Type: GrantFiled: February 6, 2007Date of Patent: August 26, 2008Assignee: AmberWave Systems CorporationInventors: Matthew T. Currie, Anthony J. Lochtefeld
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Publication number: 20080196659Abstract: A deposition method which deposits a CdS buffer layer on a surface of a solar cell from a process solution including all chemical components of the CdS buffer layer material. CdS is deposited in a deposition chamber by heating the surface of the solar cell absorber to cause the transfer of heat from the solar cell absorber layer to at least a portion of the process solution that is in contact with the surface. Used solution is cooled, and replenished in a solution container and redirected into the deposition chamber.Type: ApplicationFiled: February 25, 2008Publication date: August 21, 2008Inventor: Bulent M. Basol
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Publication number: 20080113467Abstract: The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer.Type: ApplicationFiled: November 6, 2006Publication date: May 15, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jack O. Chu, Gabriel K. Dehlinger, Alfred Grill, Steven J. Koester, Qiqing Ouyang, Jeremy D. Schaub
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Patent number: 7368309Abstract: The present invention relates to nitride semiconductor, and more particularly, to GaN-based nitride semiconductor and fabrication method thereof. The nitride semiconductor according to the present invention comprises a substrate; a GaN-based buffer layer formed in any one of a group of three-layered structure AlyInxGa1?(x+y)N/InxGa1?xN/GaN where 0?x?1 and 0?y?1, two-layered structure InxGa1?xN/GaN where 0?x?1 and superlattice structure of InxGa1?xN/GaN where 0?x?1; and a GaN-based single crystalline layer.Type: GrantFiled: August 19, 2003Date of Patent: May 6, 2008Assignee: LG Innotek Co., Ltd.Inventor: Suk Hun Lee
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Patent number: 7368067Abstract: A p-type ZnO semiconductor film comprised mainly of Zn and O elements is disclosed. The film is characterized as containing an alkali metal and nitrogen. Preferably, the alkali metal is contained such that its concentration is distributed to increase toward an end or toward both ends in the thickness direction of the film. More preferably, the alkali metal is contained in the concentration range of 1×1018-5×1021 cm?3 and the nitrogen in the concentration range of 2×1017-5×1020 cm?3.Type: GrantFiled: January 26, 2005Date of Patent: May 6, 2008Assignee: Sanyo Electric Co., Ltd.Inventors: Shigeo Yata, Kenichiro Wakisaka, Takeshi Kobayashi
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Patent number: 7358112Abstract: A method of growing a p-type nitride semiconductor material having magnesium as a p-type dopant by molecular beam epitaxy (MBE), comprises supplying ammonia gas, gallium and magnesium to an MBE growth chamber containing a substrate so as to grow a p-type nitride semiconductor material over the substrate. Magnesium is supplied to the growth chamber at a beam equivalent pressure of at least 1 10-9 mbar, and preferably in the range from 1 10-9 mbar to 1 10-7 mbar during the growth process. This provides p-type GaN that has a high concentration of free charge carriers and eliminates the need to activate the magnesium dopant atoms by annealing or irradiating the material.Type: GrantFiled: June 13, 2002Date of Patent: April 15, 2008Assignee: Sharp Kabushiki KaishaInventors: Jennifer Mary Barnes, Valerie Bousquet, Stewart Edward Hooper, Jonathan Heffernan
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Patent number: 7317202Abstract: A technique for fabricating an epitaxial component layer sequence based on a first III/V compound semiconductor material system with a first group V element on a substrate or a buffer layer, which comprises a material based on a second III/V compound semiconductor material system with a second group V element, which is different from the first group V element. At least one layer sequence with a first and a second III/V compound semiconductor material layer is applied to the substrate or to the buffer layer before the application of the epitaxial component layer sequence, the first and second III/V compound semiconductor material layers having different compositions from one another and containing both the first and the second group V elements.Type: GrantFiled: September 28, 2004Date of Patent: January 8, 2008Assignee: Osram Opto Semiconductors, GmbHInventors: Alexander Behres, Norbert Linder, Bernd Mayer
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Patent number: 7294200Abstract: A method for producing a nitride semiconductor crystal comprising steps (a), (b) and (c), which steps follow in sequence as follows: a step (a) for forming fine crystal particles made of a nitride semiconductor on a substrate; a step (b) for forming a nitride semiconductor island structure having a plurality of facets inclined relative to a surface of the substrate using the fine crystal particles as nuclei; and a step (c) for causing the nitride semiconductor island structure to grow in a direction parallel with a surface of the substrate to merge a plurality of the nitride semiconductor island structures with each other, thereby forming a nitride semiconductor crystal layer having a flat surface; the steps (a)-(c) being continuously conducted in the same growing apparatus.Type: GrantFiled: March 26, 2003Date of Patent: November 13, 2007Assignee: Hitachi Cable, Ltd.Inventors: Hajime Fujikura, Kazuyuki Iizuka
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Patent number: 7253355Abstract: The invention relates to a method for constructing a layer structure on an especially fragile flat substrate. In order for thin, fragile flat substrates to be able to be subjected to refinement or construction of semiconductor components, a process is proposed with the steps: Applying an inorganic ceramic phase to the fragile substrate and subsequent heat treatment for hardening and sintering the inorganic ceramic material.Type: GrantFiled: December 19, 2002Date of Patent: August 7, 2007Assignee: RWE Schott Solar GmbHInventors: Ingo Schwirtlich, Wilfried Schmidt, Hilmar von Campe
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Patent number: 7238545Abstract: A method of manufacturing a tandem-type thin film photoelectric conversion device includes the steps of forming at least one photoelectric conversion unit (3) on a substrate (1) in a deposition apparatus, taking out the substrate (1) having the photoelectric conversion unit (3) from the deposition apparatus to the air, introducing the substrate (1) into a deposition apparatus and carrying out plasma exposure processing on the substrate (1) in an atmosphere of a gas mixture containing an impurity for determining the conductivity type of the same conductivity type as that of the uppermost conductivity type layer (33) and hydrogen, forming a conductivity type intermediate layer (5) by additionally supplying semiconductor raw gas to the deposition apparatus, and then forming a subsequent photoelectric conversion unit (4).Type: GrantFiled: April 2, 2003Date of Patent: July 3, 2007Assignee: Kaneka CorporationInventors: Masashi Yoshimi, Takashi Suezaki, Kenji Yamamoto
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Patent number: 7211462Abstract: A process for large-scale production of CdTe/CdS thin film solar cells, films of the cells being deposited, in sequence, on a transparent substrate, the sequence comprising the steps of: depositing a film of a transparent conductive oxide (TCO) on the substrate; depositing a film of CdS on the TCO film; depositing a film of CdTe on the CdS film; treating the CdTe film with CdCl2; depositing a back-contact film on the treated CdTe film. Treatment of the CdTe film with CdCl2 comprises the steps of: forming a layer of CdCl2 on the CdTe film by evaporation, while maintaining the substrate at room temperature; annealing the CdCl2 layer in a vacuum chamber at a temperature generally within a range of 380° C. and 420° C. and a pressure generally within a range of 300 mbar and 1000 mbar in an inert gas atmosphere; removing the inert gas from the chamber so as to produce a vacuum condition, while the substrate is kept at a temperature generally within a range of 350° C. and 420° C.Type: GrantFiled: October 4, 2002Date of Patent: May 1, 2007Assignee: Solar Systems & Equipments S.r.l.Inventors: Nicola Romeo, Alessio Bosio, Alessandro Romeo
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Patent number: 7202104Abstract: The present invention is related to methods and apparatus that allow a chalcogenide glass such as germanium selenide (GexSe1-x) to be doped with a metal such as silver, copper, or zinc without utilizing an ultraviolet (UV) photodoping step to dope the chalcogenide glass with the metal. The chalcogenide glass doped with the metal can be used to store data in a memory device. Advantageously, the systems and methods co-sputter the metal and the chalcogenide glass and allow for relatively precise and efficient control of a constituent ratio between the doping metal and the chalcogenide glass. Further advantageously, the systems and methods enable the doping of the chalcogenide glass with a relatively high degree of uniformity over the depth of the formed layer of chalcogenide glass and the metal. Also, the systems and methods allow a metal concentration to be varied in a controlled manner along the thin film depth.Type: GrantFiled: June 29, 2004Date of Patent: April 10, 2007Assignee: Micron Technology, Inc.Inventors: Jiutao Li, Allen McTeer, Gregory Herdt, Trung T. Doan
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Patent number: 7192850Abstract: A doping method for forming quantum dots is disclosed, which includes following steps: providing a first precursor solution for a group II element and a second precursor solution for a group VI element; heating and mixing the first precursor solution and the second precursor solution for forming a plurality of II–VI compound cores of the quantum dots dispersing in a melting mixed solution; and injecting a third precursor solution for a group VI element and a forth precursor solution with at least one dopant to the mixed solution in turn at a fixed time interval in order to form quantum dots with multi-shell dopant; wherein the dopant described here is selected from a group consisting of transitional metal and halogen elements. This method of the invention can dope the dopants in the inner quantum dot and enhance the emission intensity efficiently.Type: GrantFiled: December 30, 2004Date of Patent: March 20, 2007Assignee: Industrial Technology Research InstituteInventors: Hsueh-Shih Chen, Dai-Luon Lo, Chien-Ming Chen, Gwo-Yang Chang
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Patent number: 7189588Abstract: The present invention provides a group III nitride semiconductor substrate with low defect density as well as small warp and a process for producing the same; for instance, the process according to the present invention comprises the following series of steps of: forming a metallic Ti film 63 on a sapphire substrate 61, followed by treatment of nitration to convert it into a TiN film 64 having fine pores; thereafter growing a HVPE-GaN layer 66 thereon; forming voids 65 in the HVPE-GaN layer 66 by means of effects of the metallic Ti film 63 and the TiN film 64; and peeling the sapphire substrate 61 from the region of the voids 65 to remove it therefrom.Type: GrantFiled: July 1, 2003Date of Patent: March 13, 2007Assignees: NEC Corporation, Hitachi Cable, Ltd.Inventors: Akira Usui, Masatomo Shibata, Yuichi Oshima
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Patent number: 7179677Abstract: A process for making a thin film ZnO/Cu(InGa)Se2 solar cell without depositing a buffer layer and by Zn doping from a vapor phase, comprising: depositing Cu(InGa)Se2 layer on a metal back contact deposited on a glass substrate; heating the Cu(InGa)Se2 layer on the metal back contact on the glass substrate to a temperature range between about 100° C. to about 250° C.; subjecting the heated layer of Cu(InGa)Se2 to an evaporant species from a Zn compound; and sputter depositing ZnO on the Zn compound evaporant species treated layer of Cu(InGa)Se2.Type: GrantFiled: September 3, 2003Date of Patent: February 20, 2007Assignee: Midwest Research InstituteInventors: Kannan Ramanathan, Falah S. Hasoon, Sarah E. Asher, James Dolan, James C. Keane
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Patent number: 7157300Abstract: A method of fabricating a thin film germanium photodetector includes preparing a silicon substrate; fabricating a CMOS device on the silicon substrate; preparing a germanium substrate; preparing surfaces of each substrate for bonding; bonding the germanium substrate to the CMOS-bearing silicon substrate to form a bonded structure; removing a portion of the germanium substrate from the bonded structure; forming a PIN diode in the germanium substrate; removing a portion of the germanium layer by etching; and completing the germanium photo detector.Type: GrantFiled: November 19, 2004Date of Patent: January 2, 2007Assignee: Sharp Laboratories of America, Inc.Inventors: Jong-Jan Lee, Jer-Shen Maa, Sheng Teng Hsu, Douglas J. Tweet
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Patent number: 7153715Abstract: A spacer layer is formed on a single-crystal substrate and an epitaxially grown layer composed of a group III-V compound semiconductor layer containing a nitride or the like is further formed on the spacer layer. The epitaxially grown layer is adhered to a recipient substrate. The back surface of the single-crystal substrate is irradiated with a light beam such as a laser beam or a bright line spectrum from a mercury vapor lamp such that the epitaxially grown layer and the single-crystal substrate are separated from each other. Since the forbidden band of the spacer layer is smaller than that of the single-crystal substrate, it is possible to separate the thin semiconductor layer from the substrate by decomposing or fusing the spacer layer, while suppressing the occurrence of a crystal defect or a crack in the epitaxially grown layer.Type: GrantFiled: February 10, 2005Date of Patent: December 26, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Tetsuzo Ueda
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Patent number: 7151008Abstract: A method of forming a diode structure for a phase-change data storage array, having multiple thin film layers adapted to form a plurality of data storage cell diodes is disclosed. The method includes depositing a first diode layer of CuInSe material on a substrate and depositing a second diode layer of phase-change material on the first diode layer.Type: GrantFiled: October 17, 2005Date of Patent: December 19, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Gary R. Ashton, Gary A. Gibson, Robert N. Bicknell-Tassius
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Patent number: 7138290Abstract: The invention includes methods of depositing silver onto a metal selenide-comprising surface, and methods of forming a resistance variable device. In one implementation, a method of depositing silver onto a metal selenide-comprising surface includes providing a deposition chamber comprising a sputtering target and a substrate to be depositing upon. The target comprises silver, and the substrate comprises an exposed surface comprising metal selenide. Gaseous cesium is flowed to the target and a bombarding inert sputtering species is flowed to the target effective to sputter negative silver ions from the target. The sputtered negative silver ions are flowed to the exposed metal selenide-comprising surface effective to deposit a continuous and completely covering silver film on the exposed metal selenide of the substrate.Type: GrantFiled: December 3, 2004Date of Patent: November 21, 2006Assignee: Micron Technology, Inc.Inventor: Allen McTeer
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Patent number: 7135347Abstract: A method for manufacturing a nitride film including a high-resistivity GaN layer includes a step of allowing a Group-III source gas containing an organic metal compound, a Group-V source gas containing ammonia, a carrier gas for the Group-III source gas, and a carrier gas for the Group-V source gas to flow over a predetermined monocrystalline wafer maintained at 1,000° C. or more and also includes a step of epitaxially growing a nitride film, including a GaN layer, on the monocrystalline wafer by a vapor phase reaction of the source gases. At least one of the carrier gases contains nitrogen while the wafer temperature is being increased before the reaction is carried out. At least one of the carrier gases contains hydrogen and nitrogen and has a total hydrogen and nitrogen content of 90 percent by volume or more in at least one part of the epitaxially growing step.Type: GrantFiled: June 22, 2004Date of Patent: November 14, 2006Assignee: NGK Insulators, Ltd.Inventors: Makoto Miyoshi, Masahiro Sakai, Mitsuhiro Tanaka, Takashi Egawa, Hiroyasu Ishikawa
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Patent number: 7122392Abstract: A method of forming a high germanium concentration, low defect density silicon germanium film and its associated structures is described, comprising forming a dielectric layer on a substrate, patterning the dielectric layer to form a silicon region and at least one dielectric region, and forming a low defect silicon germanium layer on at least one dielectric region.Type: GrantFiled: June 30, 2003Date of Patent: October 17, 2006Assignee: Intel CorporationInventor: Mike Morse
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Patent number: 7122734Abstract: A method of reducing propagation of threading dislocations into active areas of an optoelectronic device having a III–V material system includes growing a metamorphic buffer region in the presence of an isoelectronic surfactant. A first buffer layer may be lattice matched to an adjacent substrate and a second buffer layer may be lattice matched to device layers disposed upon the second buffer layer. Moreover, multiple metamorphic buffer layers fabricated in this manner may be used in a single given device allowing multiple layers to have their band gaps and lattice constants independently selected from those of the rest of the device.Type: GrantFiled: October 23, 2002Date of Patent: October 17, 2006Assignee: The Boeing CompanyInventors: Christopher M. Fetzer, James H. Ermer, Richard R. King, Peter C. Cotler
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Patent number: 7041529Abstract: In a light-emitting device, a light-emitting layer portion composed of a compound semiconductor is bonded on one main surface of a transparent conductive semiconductor substrate while placing a substrate-bonding conductive oxide layer composed of a conductive oxide in between. Between the light-emitting layer portion and the substrate-bonding conductive oxide layer, a contact layer for reducing junction resistance with the substrate-bonding conductive oxide layer so as to contact with the substrate-bonding conductive oxide layer. This is successful in providing the light-emitting device which is producible at low costs, has a low series resistance, and can attain a sufficient emission efficiency despite it has a thick current-spreading layer.Type: GrantFiled: October 22, 2003Date of Patent: May 9, 2006Assignees: Shin-Etsu Handotai Co., Ltd., Nanoteco CorporationInventors: Masato Yamada, Jun-ya Ishizaki, Nobuhiko Noto, Kazunori Hagimoto, Shinji Nozaki, Kazuo Uchida, Hiroshi Morisaki
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Patent number: 7029943Abstract: A photovoltaic component with at least one silicon wafer that has a certain basic doping, a light-receiving side, and electric bonding side opposite the light-receiving side, and at least one interdigital semiconductor structure arranged on the electric bonding side with at least one n-type semiconductor part-structure and at least one p-type semiconductor part-structure arranged at a certain interval to the n-type semiconductor part-structure. One of the semiconductor part-structures and the silicon wafer thus forms a p-n junction. The silicon wafer may be a tri-crystalline wafer.Type: GrantFiled: September 13, 2001Date of Patent: April 18, 2006Assignee: Shell Oil CompanyInventor: Wolfgang Krühler
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Patent number: 7026228Abstract: The invention relates to a method of depositing Hg1-xCdxTe onto a substrate, in a MOVPE technique, where 0?x?1; comprising the step of reacting together a volatile organotellurium compound, and one or both of (i) a volatile organocadmium compound and (ii) mercury vapour; characterised in that the organotellurium compound is isopropylallyltelluride. The invention also relates to devices, such as infrared sensors and solar cells, that comprise Hg1-xCdxTe materials.Type: GrantFiled: August 22, 2000Date of Patent: April 11, 2006Assignee: QinetiQ LimitedInventors: Janet E. Hails, Saamara N. Turney, legal representative, David J. Cole-Hamilton, William Bell, Douglas F. Foster, John Stevenson, deceased
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Patent number: 7009185Abstract: The present invention relates to an ultraviolet detector and manufacture method thereof, in which a buffer layer is formed on a baseplate and a P-type GaN layer is formed on the baseplate by using epitaxial method. By availing ion-distribution-and-vegetation technology, a first N-type GaN layer is vegetated and invested in the P-type GaN layer by distributing and vegetating Si+ ions in that layer, and a second N-type GaN layer having a thicker ion concentration is invested in the N-type GaN layer. Finally, an annular and a circular metallic layer are formed between the P-type GaN layer and the first N-type GaN layer as well as inside the second N-type GaN layer, respectively, to serve for respective ohmic contact layers. The present invention is characterized in that an incident light can project upon a depletion layer of the GaN planar structure to have the detection efficiency significantly improved.Type: GrantFiled: July 19, 2003Date of Patent: March 7, 2006Assignee: National Central UniversityInventors: Gou-Chung Chi, Iinn-Kong Sheu, Meng-Che Chen, Min-Lum Lee
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Patent number: 7001791Abstract: A method for forming group III-N articles includes the steps of providing a single crystal silicon substrate, depositing a zinc oxide (ZnO) layer on the substrate, and depositing a single crystal group III-N layer on the ZnO layer. At least a portion of the group III-N layer is deposited at a temperature of less than 600° C.Type: GrantFiled: October 22, 2003Date of Patent: February 21, 2006Assignee: University of FloridaInventors: Olga Kryliouk, Tim Anderson, Kee Chan Kim
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Patent number: 6995388Abstract: A phase changeable memory device includes a substrate having a lower electrode disposed thereon. A phase changeable pattern is disposed on the lower electrode and an upper electrode is disposed on the phase changeable pattern that has a tip that extends therefrom and is directed toward the lower electrode.Type: GrantFiled: October 28, 2003Date of Patent: February 7, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Nam Hwang, Se-Ho Lee
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Patent number: 6991956Abstract: A method for transferring a layer of semiconductor material from a wafer is described. The wafer includes a support substrate and an upper surface that includes a buffer layer of a material having a first lattice parameter. In an embodiment, the technique includes growing a strained layer on the buffer layer. The strained layer is made of a semiconductor material having a nominal lattice parameter that is substantially different from the first lattice parameter, and it is grown to a thickness that is sufficiently thin to avoid relaxation of the strain therein. The method also includes growing a relaxed layer on the strained layer. The relaxed layer is made of silicon and has a concentration of at least one other semiconductor material that has a nominal lattice parameter that is substantially identical to the first lattice parameter. The technique also includes providing a weakened zone in the buffer layer, and supplying energy to detach a structure at the weakened zone.Type: GrantFiled: January 10, 2005Date of Patent: January 31, 2006Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.Inventors: Bruno Ghyselen, Cécile Aulnette, Bénédite Osternaud, Nicolas Daval
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Patent number: 6967119Abstract: There is provided a semiconductor laser device having on a single substrate a plurality of laser portions each oscillating laser light of a different wavelength, the plurality of laser portions containing different types, respectively, of dopant. There is also provided a method of fabricating a semiconductor laser device, forming on a single substrate a plurality of laser portions each oscillating laser light of a different wavelength, initially forming a laser portion in a crystal growth method and subsequently forming another laser portion in a different crystal growth method.Type: GrantFiled: October 31, 2003Date of Patent: November 22, 2005Assignee: Sharp Kabushiki KaishaInventors: Taiji Morimoto, Keisuke Miyazaki, Masaki Tatsumi, Kazuhiko Wada, Yoshiaki Ueda
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Patent number: 6967122Abstract: A sapphire substrate 1 is etched so that each trench has a width of 10 ?m and a depth of 10 ?m were formed at 10 ?m of intervals in a stripe pattern. Next, an AlN buffer layer 2 having a thickness of approximately 40 nm is formed mainly on the upper surface and the bottom surface of the trenches of the substrate 1. Then a GaN layer 3 is formed through vertical and lateral epitaxial growth. At this time, lateral epitaxial growth of the buffer layer 21, which was mainly formed on the upper surface of the trenches, filled the trenches and thus establishing a flat top surface. The portions of the GaN layer 3 formed above the top surfaces of the mesas having a depth of 10 ?m exhibited significant suppression of threading dislocation in contrast to the portions formed above the bottoms of the trenches.Type: GrantFiled: February 23, 2001Date of Patent: November 22, 2005Assignee: Toyoda Gosei Co., Ltd.Inventor: Yuta Tezen
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Patent number: 6936490Abstract: A method of epitaxially growing a SiC film on a Si substrate, including: (a) supplying a raw material gas containing a gas having P (phosphorus) element and a gas having B (boron) element on a Si substrate, and thereby synthesizing an amorphous BP thin film having a thickness of 5 nm or more and 100 nm or less on the Si substrate; (b) further supplying a raw material gas containing a gas having P element and a gas having B element on the Si substrate, and thereby synthesizing a cubic boron phosphide single crystal film having a thickness of 5 nm or more and 1000 nm or less on the Si substrate; and (c) supplying a gas having carbon element and a gas having silicon element on the Si substrate thereon the BP single crystal film is formed, and thereby synthesizing a beta-SiC single crystal film or an amorphous SiC film having a thickness of 1 nm or more and several hundreds nanometers or less on the cubic boron phosphide single crystal film on the Si substrate.Type: GrantFiled: September 5, 2002Date of Patent: August 30, 2005Assignee: Toshiba Ceramics Co, Ltd.Inventors: Yoshihisa Abe, Shunichi Suzuki, Hideo Nakanishi, Kazutaka Terashima, Jun Komiyama
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Patent number: 6924159Abstract: To provide a semiconductor substrate of a group III nitride with low defect density and little warp, this invention provides a process comprising such steps of: forming a GaN layer 2 on a sapphire substrate 1 of the C face ((0001) face); forming a titanium film 3 thereon; heat-treating the substrate in an atmosphere containing hydrogen gas or a gas of a compound containing hydrogen to form voids in the GaN layer 2; and thereafter forming a GaN layer 4 on the GaN layer 2?.Type: GrantFiled: March 26, 2002Date of Patent: August 2, 2005Assignees: NEC Corporation, Hitachi Cable, Ltd.Inventors: Akira Usui, Masatomo Shibata, Yuichi Oshima
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Patent number: 6890790Abstract: The present invention is related to methods and apparatus that allow a chalcogenide glass such as germanium selenide (GexSe1-x) to be doped with a metal such as silver, copper, or zinc without utilizing an ultraviolet (UV) photodoping step to dope the chalcogenide glass with the metal. The chalcogenide glass doped with the metal can be used to store data in a memory device. Advantageously, the systems and methods co-sputter the metal and the chalcogenide glass and allow for relatively precise and efficient control of a constituent ratio between the doping metal and the chalcogenide glass. Further advantageously, the systems and methods enable the doping of the chalcogenide glass with a relatively high degree of uniformity over the depth of the formed layer of chalcogenide glass and the metal. Also, the systems and methods allow a metal concentration to be varied in a controlled manner along the thin film depth.Type: GrantFiled: June 6, 2002Date of Patent: May 10, 2005Assignee: Micron Technology, Inc.Inventors: Jiutao Li, Allen McTeer, Gregory Herdt, Trung T. Doan
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Patent number: 6885021Abstract: Briefly, in accordance with one embodiment of the invention, a device, such as a memory cell, includes a dielectric layer and a layer of phase-change material with an adhesion layer between the dielectric layer and the layer of phase-change material.Type: GrantFiled: December 31, 2001Date of Patent: April 26, 2005Assignee: Ovonyx, Inc.Inventors: Mac Apodaca, Jon-Won S. Lee, Kuo-Wei Chang
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Patent number: 6864414Abstract: A solar cell having a multijunction solar cell structure with a bypass diode is disclosed. The bypass diode provides a reverse bias protection for the multijunction solar cell structure. In one embodiment, the multifunction solar cell structure includes a substrate, a bottom cell, a middle cell, a top cell, a bypass diode, a lateral conduction layer, and a shunt. The lateral conduction layer is deposited over the top cell. The bypass diode is deposited over the lateral conduction layer. One side of the shunt is connected to the substrate and another side of the shunt is connected to the lateral conduction layer. In another embodiment, the bypass diode contains an i-layer to enhance the diode performance.Type: GrantFiled: October 24, 2002Date of Patent: March 8, 2005Assignee: Emcore CorporationInventors: Paul R. Sharps, Daniel J. Aiken, Doug Collins, Mark A. Stan
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Patent number: 6861281Abstract: A reflective layer 10 is formed on a back surface 11b of a sapphire substrate 11. The reflective layer 10 includes an extension portion 10a which extends so as to cover almost all the sidewalls 21a of a light-emitting device in the vicinity of the sapphire substrate. Thus, since adhesion between the reflective layer 10 and the substrate is greatly enhanced in the vicinity of the periphery of the surface on which the reflective layer is formed (the substrate back surface 11b) by virtue of formation of the aforementioned extension portion 10a, exfoliation of the reflective layer 10 from the substrate is prevented. Therefore, even when a process in which the reflective layer 10 is attached onto an adhesive sheet to thereby secure the light-emitting device 100 on the sheet is employed, generation of a defective product having an exfoliated reflective layer can be prevented.Type: GrantFiled: December 25, 2000Date of Patent: March 1, 2005Assignee: Toyoda Gosei Co., Ltd.Inventors: Toshiya Uemura, Naohisa Nagasaka
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Publication number: 20040259287Abstract: A semiconductor light receiving device is disclosed which is capable of receiving a first wavelength band light beam and a second wavelength band light beam having a shorter wavelength than that of the first wavelength band light beam. The device has a light absorbing layer of a first conductivity type formed on a semiconductor surface region of the semiconductor substrate the light absorbing layer absorbs the first and second wavelength band light beams. A cap layer of the first conductivity type is formed on the light absorbing layer. In the cap layer, a region of a second conductivity type is formed which transmits the second wavelength band light beam. A light collecting layer is formed on the semiconductor surface region and adjacently to the cap layer and the light absorbing layer. The light collecting layer has a convex shape with curvature to collect the second wavelength band light beam.Type: ApplicationFiled: April 15, 2004Publication date: December 23, 2004Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Hajime Suhara
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Patent number: 6830949Abstract: A preferred condition for forming a Group III nitride compound semiconductor layer on a substrate by a sputtering method is proposed. When a first Group III nitride compound semiconductor layer is formed on a substrate by a sputtering method, an initial voltage of a sputtering apparatus is selected to be not higher than 110% of a sputtering voltage.Type: GrantFiled: October 21, 2002Date of Patent: December 14, 2004Assignee: Toyoda Gosei Co., Ltd.Inventors: Masanobu Senda, Jun Ito, Toshiaki Chiyo, Naoki Shibata, Shizuyo Asami
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Patent number: 6812059Abstract: Disclosed is a photodiode with improved light-receiving efficiency and coupling effect with an optical fiber, whose capacitance may be decreased. The inventive photodiode includes a substrate; a buffer layer and a light-absorbing layer laminated in sequence on the substrate; an epitaxial layer formed on the upper surface of the light absorbing layer and having an active region with a surface in a convex lens shape so that it has greater surface area and more effective light-receiving area than an active region defined in a two-dimensional plane, the active region further having a convex surface can harvest light with its convex-lens characteristics; a dielectric layer formed on the upper surface of the epitaxial layer; a first metal electrode formed on an upper surface of the dielectric layer; and, a second metal electrode formed on an under surface of the substrate.Type: GrantFiled: October 9, 2003Date of Patent: November 2, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Hwa-Young Kang, Jung-Kee Lee
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Publication number: 20040206389Abstract: On a surface of a GaAs substrate, layers to be a top cell are formed by epitaxial growth. On the top cell, layers to be a bottom cell are formed. Thereafter, on a surface of the bottom cell, a back surface electrode is formed. Thereafter, a glass plate is adhered to the back surface electrode by wax. Then, the GaAs substrate supported by the glass plate is dipped in an alkali solution, whereby the GaAs substrate is removed. Thereafter, a surface electrode is formed on the top cell. Finally the glass plate is separated from the back surface electrode. In this manner, a compound solar battery that improves efficiency of conversion to electric energy can be obtained.Type: ApplicationFiled: March 22, 2004Publication date: October 21, 2004Applicant: Sharp Kabushiki KaishaInventors: Tatsuya Takamoto, Takaaki Agui