Compound Semiconductor Patents (Class 438/93)
  • Publication number: 20100151618
    Abstract: A method of manufacturing a solar cell by providing a gallium arsenide carrier with a prepared bonding surface; providing a sapphire substrate; bonding the gallium arsenide carrier and the sapphire substrate to produce a composite structure; detaching the bulk of the gallium arsenide carrier from the composite structure, leaving a gallium arsenide growth substrate on the sapphire substrate; and depositing a sequence of layers of semiconductor material forming a solar cell on the growth substrate. For some solar cells, the method further includes mounting a surrogate second substrate on top of the sequence of layers of semiconductor material forming a solar cell; and removing the growth substrate.
    Type: Application
    Filed: December 17, 2008
    Publication date: June 17, 2010
    Applicant: Emcore Solar Power, Inc.
    Inventors: Paul R. Sharps, Arthur Cornfeld, Tansen Varghese, Fred Newman, Jacqueline Diaz
  • Publication number: 20100151619
    Abstract: A photodiode is formed in a recessed germanium (Ge) region in a silicon (Si) substrate. The Ge region may be fabricated by etching a hole through a passivation layer on the Si substrate and into the Si substrate and then growing Ge in the hole by a selective epitaxial process. The Ge appears to grow better selectively in the hole than on a Si or oxide surface. The Ge may grow up some or all of the passivation sidewall of the hole to conformally fill the hole and produce a recessed Ge region that is approximately flush with the surface of the substrate, without characteristic slanted sides of a mesa. The hole may be etched deep enough so the photodiode is thick enough to obtain good coupling efficiencies to vertical, free-space light entering the photodiode.
    Type: Application
    Filed: February 25, 2010
    Publication date: June 17, 2010
    Applicant: ANALOG DEVICES, INC.
    Inventors: John A. Yasaitis, Lawrence Jay Lowell
  • Patent number: 7736913
    Abstract: The present invention relates to methods and apparatus for providing composition control to thin compound semiconductor films for radiation detector and photovoltaic applications. In one aspect of the invention, there is provided a method in which the molar ratio of the elements in a plurality of layers are detected so that tuning of the multi-element layer can occur to obtain the multi-element layer that has a predetermined molar ratio range. In another aspect of the invention, there is provided a method in which the thickness of a sub-layer and layers thereover of Cu, In and/or Ga are detected and tuned in order to provide tuned thicknesses that are substantially the same as pre-determined thicknesses.
    Type: Grant
    Filed: April 4, 2007
    Date of Patent: June 15, 2010
    Assignee: SoloPower, Inc.
    Inventors: Bulent M. Basol, Serdar Aksu
  • Patent number: 7732706
    Abstract: The invention is a novel manufacturing method for making multi-junction solar cell circuits that addresses current problems associated with such circuits by allowing the formation of integral diodes in the cells and allows for a large number of circuits to readily be placed on a single silicon wafer substrate. The standard Ge wafer used as the base for multi-junction solar cells is replaced with a thinner layer of Ge or a II-V semiconductor material on a silicon/silicon dioxide substrate. This allows high-voltage cells with multiple multi-junction circuits to be manufactured on a single wafer, resulting in less array assembly mass and simplified power management.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: June 8, 2010
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventor: Nick Mardesich
  • Publication number: 20100129956
    Abstract: The method is disclosed that Si+ is implanted on Si substrate to enhance strain relaxation at the interface between the metamorphic GexSi1?x buffer layers and Si substrate, in order to facilitate the growth of a high quality Ge on Si substrate. And several GexSi1?x buffer layers (Si/Ge0.8Si0.2/Ge0.9Si0.1/Ge) are grown on top of Si substrate by UHVCVD. Then grow pure Ge layer of low dislocation density on GexSi1?x buffer layer. Finally, grow up high efficiency III-V solar cell on GexSi1?x buffer layer.
    Type: Application
    Filed: August 4, 2009
    Publication date: May 27, 2010
    Applicant: National Chiao Tung University
    Inventors: Edward Yi Chang, Shih-Hsuan Tang, Yue-Cin Lin
  • Patent number: 7717987
    Abstract: The copper-indium-gallium (CuInGa) alloy is in particular to be used for the production of sputter targets, tubular cathodes and similar coating material sources. It has a phase corresponding to a Cu5Zn8 prototype phase in which the lattice sites of the zinc atoms (Zn) are occupied by gallium atoms (gallium-substituted Cu5Zn8 phase) and in which indium is simultaneously introduced into the elementary cell or phase, making up a proportion of up to 26 wt %.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: May 18, 2010
    Assignee: GfE Metalle und Materialien GmbH
    Inventors: Karl-Uwe van Osten, Stefan Britting
  • Publication number: 20100120192
    Abstract: A method for preparing III-VI2 nanoparticles and a thin film of polycrystalline light absorber layers. The method for preparing I-III-VI2 nanoparticles comprises the steps of: (a1) preparing a mixed solution by mixing each element from groups I, III and VI in the periodic table with a solvent; (a2) sonicating the mixed solution; (a3) separating the solvent from the sonicated mixed solution; and (a4) drying the product resulted from the above step (a3) to obtain nanoparticles.
    Type: Application
    Filed: June 17, 2008
    Publication date: May 13, 2010
    Applicant: SUNGKYUNKWAN UNIVERSITY
    Inventors: Duk-Young Jung, Jae Eok Han, Juyeon Chang
  • Publication number: 20100116316
    Abstract: The present disclosure presents a partially-transparent (see-through) three-dimensional thin film solar cell (3-D TFSC) substrate. The substrate includes a plurality of unit cells. Each unit cell structure has the shape of a truncated pyramid, and its parameters may be varied to allow a desired portion of sunlight to pass through.
    Type: Application
    Filed: November 27, 2009
    Publication date: May 13, 2010
    Applicant: SOLEXEL, INC.
    Inventors: Mehrdad M. Moslehi, David Xuan-Qi Wang
  • Publication number: 20100116329
    Abstract: Methods for forming solar cells include forming, over a substrate, a first junction comprising at least one III-V material and having a threading dislocation density of less than approximately 107 cm?2, and forming, over the first junction, a cap layer comprising silicon, wherein the substrate consists essentially of silicon.
    Type: Application
    Filed: May 29, 2009
    Publication date: May 13, 2010
    Inventors: Eugene A. Fitzgerald, Arthur J. Pitera, Steven A. Ringel
  • Publication number: 20100116327
    Abstract: A method of manufacturing a solar cell by providing a first semiconductor substrate and depositing a first sequence of layers of semiconductor material to form a first solar subcell, including a first bond layer disposed on the top of the first sequence of layers. A second semiconductor substrate is provided, and on the top surface of the second substrate a second sequence of layers of semiconductor material is deposited forming at least a second solar subcell. A second bond layer is disposed on the top of said second sequence of layers. The first solar subcell is mounted on top of the second solar subcell by joining the first bond layer to the second bond layer in an ultra high vacuum chamber, and the first semiconductor substrate is removed.
    Type: Application
    Filed: November 10, 2008
    Publication date: May 13, 2010
    Applicant: EMCORE CORPORATION
    Inventor: Arthur Cornfeld
  • Patent number: 7709287
    Abstract: A method of forming a multijunction solar cell includes providing a substrate, forming a first subcell by depositing a nucleation layer over the substrate and a buffer layer including gallium arsenide (GaAs) over the nucleation layer, forming a middle second subcell having a heterojunction base and emitter disposed over the first subcell and forming first and second tunnel junction layers between the first and second subcells. The first tunnel junction layer includes GaAs over the first subcell and the second tunnel junction layer includes aluminum gallium arsenide (AlGaAs) over the first tunnel junction layer. The method further includes forming a third subcell having a homojunction base and emitter disposed over the middle subcell.
    Type: Grant
    Filed: April 10, 2006
    Date of Patent: May 4, 2010
    Assignee: Emcore Solar Power, Inc.
    Inventors: Navid Fatemi, Daniel J. Aiken, Mark A. Stan
  • Publication number: 20100096015
    Abstract: A compound film may be formed by formulating a mixture of elemental nanoparticles composed of the Ib, the IIIa, and, optionally, the VIa group of elements having a controlled overall composition. The nanoparticle mixture is combined with a suspension of nanoglobules of gallium to form a dispersion. The dispersion may be deposited onto a substrate to form a layer on the substrate. The layer may then be reacted in a suitable atmosphere to form the compound film. The compound film may be used as a light-absorbing layer in a photovoltaic device.
    Type: Application
    Filed: October 19, 2009
    Publication date: April 22, 2010
    Inventors: Matthew R. Robinson, Martin R. Roscheisen
  • Patent number: 7696533
    Abstract: The invention relates to a structure usable in electronic, optical or optoelectronic engineering which comprises a substantially crystalline layer made of an alloy consisting of at least one element of the column II of the periodic elements system and/or at least one element of the column IV of the periodic elements system and of N2 (said alloy being noted N-IV-N2), wherein said structure also comprises an InN layer. A method for producing an indium nitride layer, a substrate forming plate and the use thereof for indium nitride growth are also disclosed.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: April 13, 2010
    Assignees: Centre National de la Recherche Scientifique (CNRS), Universite Montpellier II
    Inventors: Bernard Gil, Olivier Gérard Serge Briot, Sandra Ruffenach, Bénédicte Maleyre, Thierry Joseph Roland Cloitre, Roger-Louis Aulombard
  • Publication number: 20100075457
    Abstract: A method of manufacturing a stacked-layered thin film solar cell with a light-absorbing layer having a band gradient is provided. The stacked-layered thin film solar cell includes a substrate, a back electrode layer, a light-absorbing layer, a buffer layer, a window layer, and a top electrode layer stacked up sequentially. The light-absorbing layer has a band gradient structure and is essentially a group I-III-VI compound, wherein the group III elements at least include indium (In) and aluminum (Al). Moreover, the Al/In ratio in the upper half portion of the light-absorbing layer is greater than that in the lower half portion of the light-absorbing layer, wherein the upper half portion is proximate to a light incident surface.
    Type: Application
    Filed: September 10, 2009
    Publication date: March 25, 2010
    Inventor: Feng-Chien HSIEH
  • Patent number: 7682865
    Abstract: The subject invention comprises the realization of a superlattice photodiode with polyimide surface passivation. Effective surface passivation of type-II InAs/GaSb superlattice photodiodes with cutoff wavelengths in the long-wavelength infrared is presented. A stable passivation layer, the electrical properties of which do not change as a function of the ambient environment, nor time, can be realized by a solvent-based surface preparation, vacuum desorption, and the application of an insulating polyimide layer.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: March 23, 2010
    Assignee: MP Technologies, LLC
    Inventor: Manijeh Razeghi
  • Publication number: 20100059843
    Abstract: A method for making a solid-state imaging device includes forming a pinning layer, which is a P-type semiconductor layer or an N-type semiconductor layer, on a first substrate by deposition; forming a semiconductor layer on the pinning layer; forming a photoelectric conversion unit in the semiconductor layer, the photoelectric conversion unit being configured to convert incident light into an electrical signal; forming, on the semiconductor layer, a transistor of a pixel unit and a transistor of a peripheral circuit unit disposed in the periphery of the pixel unit, and then forming a wiring section on the semiconductor layer; bonding a second substrate on the wiring section; and removing the first substrate after the second substrate is bonded.
    Type: Application
    Filed: August 31, 2009
    Publication date: March 11, 2010
    Applicant: Sony Corporation
    Inventors: Tetsuya IKUTA, Yuki Miyanami
  • Publication number: 20100041558
    Abstract: The electromagnetic radiation detection device comprises at least one absorption membrane for absorbing said radiation. The absorption membrane is formed by an absorption layer made of tungsten nitride (W2N) and having a stoichiometric ratio tungsten to nitride equal to two.
    Type: Application
    Filed: August 6, 2009
    Publication date: February 18, 2010
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE
    Inventors: Abdelkader Aliane, Thierry Farjot, Claude Pigot
  • Publication number: 20100041178
    Abstract: A method of forming a multifunction solar cell including an upper subcell, a middle subcell, and a lower subcell by providing a first substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a graded interlayer over the second subcell, the graded interlayer having a third band gap greater than the second band gap; forming a third solar subcell over the graded interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell; attaching a surrogate second substrate over the third solar subcell and removing the first substrate; and etching a first trough around the periphery of the solar cell to the surrogate second substrate so as to form a mesa structure on the surrogate second substrate and facilitate the removal of said so
    Type: Application
    Filed: August 12, 2008
    Publication date: February 18, 2010
    Applicant: Emcore Solar Power, Inc.
    Inventors: Arthur Cornfeld, Tansen Varghese, Jacqueline Diaz
  • Publication number: 20100035418
    Abstract: The present invention provides, in part, methods producing multilayer semiconductor structures having one or more at least partially relaxed strained layers, where the strained layer is at least partially relaxed by annealing. In particular, the invention forms diffusion barriers that prevent diffusion of contaminants during annealing. The invention also includes embodiments where the at least partially relaxed strained layer is patterned into islands by etching trenches and the like. The invention also provides semiconductor structures resulting from these methods, and further, provides such structures where the semiconductor materials are suitable for application to LED devices, laser devices, photovoltaic devices, and other optoelectronic devices.
    Type: Application
    Filed: December 22, 2008
    Publication date: February 11, 2010
    Inventors: Bruce FAURE, Pascal Guenard
  • Patent number: 7659137
    Abstract: A fabrication method of fabricating a structure capable of being used for generation or detection of electromagnetic radiation includes a forming step of forming a layer containing a compound semiconductor on a substrate at a substrate temperature below about 300° C., a first heating step of heating the substrate with the layer in an ambience containing arsenic, and a second heating step of heating the substrate with the layer at the substrate temperature above about 600° C. in a gas ambience incapable of chemically reacting on the compound semiconductor. Structures of the present invention capable of being used for generation or detection of electromagnetic radiation can be fabricated using the fabrication method by appropriately regulating the substrate temperature, the heating time, the gas ambience and the like in the second heating step.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: February 9, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shintaro Kasai, Toshihiko Ouchi, Masatoshi Watanabe, Mitsuru Ohtsuka, Taihei Mukaide
  • Publication number: 20100029036
    Abstract: Methods and devices are provided for forming thin-films from solid group IIIA-based particles. In one embodiment of the present invention, a method is described comprising of providing a first material comprising an alloy of a) a group IIIA-based material and b) at least one other material. The material may be included in an amount sufficient so that no liquid phase of the alloy is present within the first material in a temperature range between room temperature and a deposition or pre-deposition temperature higher than room temperature, wherein the group IIIA-based material is otherwise liquid in that temperature range. The other material may be a group IA material. A precursor material may be formulated comprising a) particles of the first material and b) particles containing at least one element from the group consisting of: group IB, IIIA, VIA element, alloys containing any of the foregoing elements, or combinations thereof. The temperature range described above may be between about 20° C.
    Type: Application
    Filed: June 12, 2007
    Publication date: February 4, 2010
    Inventors: Matthew R. Robinson, Chris Eberspacher, Jeroen K. J. Van Duren
  • Publication number: 20100015754
    Abstract: A method and a system are provide for forming planar precursor structures which are subsequently converted into thin film solar cell absorber layers. A precursor structure is first formed on the front surface of the foil substrate and then planarized through application of force or pressure by a smooth surface to obtain a planar precursor structure. The precursor structure includes at least one of a Group IB material, Group IIIA material and Group VIA material. The planar precursor structures are reacted to form planar and compositionally uniform thin film absorber layers for solar cells.
    Type: Application
    Filed: July 21, 2008
    Publication date: January 21, 2010
    Inventor: Bulent M. Basol
  • Publication number: 20100009492
    Abstract: The invention relates to the formation of thin-film crystalline silicon using a zone-melting recrystallization process in which the substrate is a ceramic material. Integrated circuits and solar cells are fabricated in the recrystallized silicon thin film and lifted off the substrate. Following lift-off, these circuits and devices are self-sustained, lightweight and flexible and the released ceramic substrate can be reused making the device fabrication process cost effective.
    Type: Application
    Filed: July 10, 2009
    Publication date: January 14, 2010
    Inventors: Duy-Phach Vu, Quoc-Bao Vu
  • Publication number: 20100006961
    Abstract: A photodiode is formed in a recessed germanium (Ge) region in a silicon (Si) substrate. The Ge region may be fabricated by etching a hole through a passivation layer on the Si substrate and into the Si substrate and then growing Ge in the hole by a selective epitaxial process. The Ge appears to grow better selectively in the hole than on a Si or oxide surface. The Ge may grow up some or all of the passivation sidewall of the hole to conformally fill the hole and produce a recessed Ge region that is approximately flush with the surface of the substrate, without characteristic slanted sides of a mesa. The hole may be etched deep enough so the photodiode is thick enough to obtain good coupling efficiencies to vertical, free-space light entering the photodiode.
    Type: Application
    Filed: July 9, 2008
    Publication date: January 14, 2010
    Applicant: ANALOG DEVICES, INC.
    Inventors: John A. Yasaitis, Lawrence Jay Lowell
  • Publication number: 20100001358
    Abstract: A photodetector 1 according to an embodiment of the present invention includes: an n-type InAs substrate 12; an n-type InAs buffer layer 14 formed on the n-type InAs substrate 12; an n-type InAs light absorbing layer 16 formed on the n-type InAs buffer layer 14; an InAsXPYSb1-X-Y cap layer 18 (X?0, Y>0) formed on the n-type InAs light absorbing layer 16; a first inorganic insulating film 20 formed on the cap layer 18, and having an opening portion 20h in a deposition direction; a p-type impurity semiconductor region 24 formed by diffusing a p-type impurity from the opening portion 20h of the first inorganic insulating film 20, and reaching from the cap layer 18 to an upper layer of the n-type InAs light absorbing layer 16; and a second inorganic insulating film 22 formed on the first inorganic insulating film 20 and on the p-type impurity semiconductor region 24.
    Type: Application
    Filed: August 27, 2007
    Publication date: January 7, 2010
    Applicant: HAMAMATSU PHOTONICS K.K.
    Inventor: Akihito Yokoi
  • Patent number: 7638357
    Abstract: A programmable resistance memory element and method of forming the same. The memory element includes a first electrode, a dielectric layer over the first electrode and a second electrode over the dielectric layer. The dielectric layer and the second electrode each have sidewalls. A layer of programmable resistance material, e.g., a phase change material, is in contact with the first electrode and at least a portion of the sidewalls of the dielectric layer and the second electrode. Memory devices including memory elements and systems incorporating such memory devices are also disclosed.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: December 29, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Jun Liu
  • Publication number: 20090315148
    Abstract: An electrochemical deposition method to form uniform and continuous Group IIIA material rich thin films with repeatability is provided. Such thin films are used in fabrication of semiconductor and electronic devices such as thin film solar cells. In one embodiment, the Group IIIA material rich thin film is deposited on an interlayer that includes 20-90 molar percent of at least one of In and Ga and at least 10 molar percent of an additive material including one of Cu, Se, Te, Ag and S. The thickness of the interlayer is adapted to be less than or equal to about 20% of the thickness of the Group IIIA material rich thin film.
    Type: Application
    Filed: June 20, 2008
    Publication date: December 24, 2009
    Inventors: Serdar Aksu, Jiaxiong Wang, Bulent M. Basol
  • Patent number: 7632702
    Abstract: The invention includes methods of depositing silver onto a metal selenide-comprising surface, and methods of forming a resistance variable device. In one implementation, a method of depositing silver onto a metal selenide-comprising surface includes providing a deposition chamber comprising a sputtering target and a substrate to be depositing upon. The target comprises silver, and the substrate comprises an exposed surface comprising metal selenide. Gaseous cesium is flowed to the target and a bombarding inert sputtering species is flowed to the target effective to sputter negative silver ions from the target. The sputtered negative silver ions are flowed to the exposed metal selenide-comprising surface effective to deposit a continuous and completely covering silver film on the exposed metal selenide of the substrate.
    Type: Grant
    Filed: August 11, 2008
    Date of Patent: December 15, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Allen McTeer
  • Publication number: 20090261442
    Abstract: A photosensitive diode has an active region defining a majority carrier of a first conductivity type and a minority carrier of a second conductivity type. An extraction region is disposed on a first side of the active region and extracts minority carriers from the active region. It also has majority carriers within the extraction region flowing toward the active region in a condition of reverse bias. An exclusion region is disposed on a second side of the active region and has minority carriers within the exclusion region flowing toward the active region. It receives majority carriers from the active region. At least one of the extraction and exclusion region provides a barrier for substantially reducing flow of one of the majority carriers or the minority carriers, whichever is flowing toward the active region, while permitting flow of the other minority carriers or majority carriers flowing out of the active region.
    Type: Application
    Filed: April 17, 2008
    Publication date: October 22, 2009
    Applicant: EPIR TECHNOLOGIES, INC.
    Inventors: Christoph H. Grein, Silviu Velicu, Sivalingam Sivananthan
  • Patent number: 7605017
    Abstract: Methods of manufacturing a semiconductor device and resulting products. The semiconductor device includes a semiconductor substrate, a hetero semiconductor region hetero-adjoined with the semiconductor substrate, a gate insulation layer contacting the semiconductor substrate and a heterojunction of the hetero semiconductor region, a gate electrode formed on the gate insulation layer, an electric field alleviation region spaced apart from a heterojunction driving end of the heterojunction that contacts the gate insulation layer by a predetermined distance and contacting the semiconductor substrate and the gate insulation layer, a source electrode contacting the hetero semiconductor region and a drain electrode contacting the semiconductor substrate. A mask layer is formed on the hetero semiconductor region, and the electric field alleviation region and the heterojunction driving end are formed by using at least a portion of the first mask layer.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: October 20, 2009
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Tetsuya Hayashi, Masakatsu Hoshi, Hideaki Tanaka, Shigeharu Yamagami
  • Publication number: 20090255578
    Abstract: A method of manufacturing a thin film photovoltaic device includes depositing a first compound semiconductor layer on a substrate and exposing the device to plasma, the plasma treating the layer.
    Type: Application
    Filed: January 15, 2009
    Publication date: October 15, 2009
    Applicant: First Solar, Inc.
    Inventors: David Eaglesham, Anke Abken
  • Publication number: 20090246906
    Abstract: Methods and devices are provided for high-throughput printing of semiconductor precursor layer from microflake particles. In one embodiment, the method comprises of transforming non-planar or planar precursor materials in an appropriate vehicle under the appropriate conditions to create dispersions of planar particles with stoichiometric ratios of elements equal to that of the feedstock or precursor materials, even after settling. In particular, planar particles disperse more easily, form much denser coatings (or form coatings with more interparticle contact area), and anneal into fused, dense films at a lower temperature and/or time than their counterparts made from spherical nanoparticles. These planar particles may be microflakes that have a high aspect ratio. The resulting dense film formed from microflakes are particularly useful in forming photovoltaic devices.
    Type: Application
    Filed: January 30, 2009
    Publication date: October 1, 2009
    Inventors: Matthew R. Robinson, Jeroen K.J. Van Duren, Craig Leidholm
  • Patent number: 7553690
    Abstract: This disclosure is concerned with starved source diffusion methods for forming avalanche photodiodes are provided for controlling an edge effect. In one example, a method for manufacturing an avalanche photodiode includes forming an absorber layer and an avalanche layer over a substrate. Next, a patterned mask defining one or more openings is formed over a surface of the avalanche layer. Finally, a dopant is deposited over the patterned mask and the avalanche layer such that the dopant is blocked by the patterned mask but diffuses into the avalanche layer in areas where the patterned mask defines an opening. The patterned mask is configured such that the depth to which the dopant diffuses into the avalanche layer varies so as to form a sloped diffusion front in the avalanche layer.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: June 30, 2009
    Assignee: Finisar Corporation
    Inventors: Daniel Francis, Rashit Nabiev, Richard P. Ratowsky, David Bruce Young, Sunil Thomas, Roman Dimitrov
  • Patent number: 7550309
    Abstract: The present invention is a method for producing a semiconductor wafer, comprising at least steps of, epitaxially growing a Si1-XGeX layer (0<X<1) on an SOI wafer, forming a Si1-YGeY layer (0?Y<X) on the epitaxially grown Si1-XGeX layer, and then enriching Ge in the epitaxially grown Si1-XGeX layer by an oxidation heat treatment so that the Si1-XGeX layer becomes an enriched SiGe layer, wherein, at least, the oxidation heat treatment is initiated from 950° C. or less under an oxidizing atmosphere, and the oxidation is performed so that the formed Si1-YGeY layer remains during a temperature rise to 950° C. Thereby, there can be provided a method for producing a semiconductor wafer by which the lattice relaxation of the SiGe layer in an SGOI wafer can be sufficiently performed by a heat treatment for a short time and its production cost can be reduced.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: June 23, 2009
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Isao Yokokawa, Nobuhiko Noto, Kiyoshi Mitani
  • Patent number: 7550305
    Abstract: An object of the present invention is to provide a method of forming a light-emitting element at a lower cost than a conventional cost with suppressing the deterioration of the substrate due to thermal distortion in comparison with a conventional method of recycling a substrate and further having an effect equal to that of the method of recycling a substrate.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: June 23, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kenji Yamagata, Takao Yonehara, Yoshinobu Sekiguchi, Kojiro Nishi
  • Patent number: 7544532
    Abstract: InSb infrared photodiodes and sensor arrays with improved passivation layers and methods for making same are disclosed. In the method, a passivation layer of AlInSb is deposited on an n-type InSb substrate using molecular beam epitaxy before photodiode detector regions are formed in the n-type substrate. Then, a suitable P+ dopant is implanted directly through the AlInSb passivation layer to form photodiode detector regions. Next, the AlInSb passivation layer is selectively removed, exposing first regions of the InSb substrate, and gate contacts are formed in the first regions of the InSb substrate. Then, additional portions of the AlInSb passivation layer are selectively removed above the photodiode detectors exposing second regions. Next, metal contacts are formed in the second regions, and bump contacts are formed atop the metal contacts. Then, an antireflection coating is applied to a side of the substrate opposite from the side having the metal and bump contacts.
    Type: Grant
    Filed: October 17, 2006
    Date of Patent: June 9, 2009
    Assignee: Raytheon Company
    Inventors: Robert P. Ginn, Kenneth A. Gerber, Andreas Hampp, Alexander C. Childs
  • Patent number: 7544535
    Abstract: The method for manufacturing a semiconductor laser element according to the present invention has the steps of: forming a semiconductor laminated structure having an active layer composed of a semiconductor material containing Al; etching the semiconductor laminated structure to form a mesa; forming a first burying layer at a first growing temperature so as to coat the side of the mesa; and forming a second burying layer at a second growing temperature higher than the first growing temperature on the first burying layer to bury the circumference of the mesa.
    Type: Grant
    Filed: January 22, 2007
    Date of Patent: June 9, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventors: Chikara Watatani, Toru Ota, Takashi Nagira
  • Patent number: 7541208
    Abstract: Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be formed with little or no consumption of surface silicon. These oxides, such as screening oxide and pad oxide, are formed by deposition onto, rather than reaction with and consumption of the surface layer. Alternatively, oxide deposition is preceded by a thermal oxidation step of short duration, e.g., rapid thermal oxidation. Here, the short thermal oxidation consumes little surface Si, and the Si/oxide interface is of high quality. The oxide may then be thickened to a desired final thickness by deposition. Furthermore, the thin thermal oxide may act as a barrier layer to prevent contamination associated with subsequent oxide deposition.
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: June 2, 2009
    Assignee: AmberWave Systems Corporation
    Inventors: Matthew T. Currie, Anthony J. Lochtefeld
  • Publication number: 20090120501
    Abstract: The present application discloses a method and system of depositing a lead selenide film onto another material. The lead selenide film may used in a photoconductive application or a photovoltaic application. Furthermore, the applications may be responsive to infrared radiation at ambient temperature. In one embodiment, a method includes sputtering the lead selenide film, performing a sensitization process, and applying a passivation film. In one exemplary embodiment, a p-n junction is formed by directly adhering a lead selenide film to a silicon substrate.
    Type: Application
    Filed: November 6, 2008
    Publication date: May 14, 2009
    Inventor: George Engle
  • Patent number: 7531440
    Abstract: A semiconductor laser device includes an n-type cladding layer 103 made of n?type (Al0.3Ga0.7)0.5In0.5P, an undoped active layer 104 and a first p-type cladding layer 105 made of p?type (Al0.3Ga0.7)0.5In0.5P. These layers are successively stacked in bottom-to-top order. The active layer 104 has a multi-quantum well structure composed of a first optical guide layer of undoped Al0.4Ga0.6As, a layered structure in which well layers of undoped GaAs and barrier layers of undoped Al0.4Ga0.6As are alternately formed, and a second optical guide layer of undoped Al0.4Ga0.6As. The first optical guide layer, the layered structure and the second optical guide layer are successively stacked in bottom-to-top order.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: May 12, 2009
    Assignee: Panasonic Corporation
    Inventor: Tsutomu Ukai
  • Publication number: 20090117679
    Abstract: Methods for forming semiconductor devices include providing a textured template, forming a buffer layer over the textured template, forming a substrate layer over the buffer layer, removing the textured template, thereby exposing a surface of the buffer layer, and forming a semiconductor layer over the exposed surface of the buffer layer.
    Type: Application
    Filed: October 31, 2008
    Publication date: May 7, 2009
    Inventor: Leslie G. Fritzemeier
  • Patent number: 7517718
    Abstract: An inorganic nanocomposite is prepared by obtaining a solution of a soluble hydrazine-based metal chalcogenide precursor; dispersing a nanoentity in the precursor solution; applying a solution of the precursor containing the nanoentity onto a substrate to produce a film of the precursor containing the nanoentity; and annealing the film of the precursor containing the nanoentity to produce the metal chalcogenide nanocomposite film comprising at least one metal chalcogenide and at least one molecularly-intermixed nanoentity on the substrate. The process can be used to prepare field-effect transistors and photovoltaic devices.
    Type: Grant
    Filed: January 12, 2006
    Date of Patent: April 14, 2009
    Assignee: International Business Machines Corporation
    Inventors: David B. Mitzi, Christopher B. Murray, Dmitri V. Talapin
  • Publication number: 20090078308
    Abstract: A multijunction solar cell including a first solar subcell having a first band gap; a second solar subcell disposed over the first subcell and having a second band gap smaller than the first band gap; a grading interlayer disposed over the second subcell and having a third band gap greater than the second band gap; a third solar subcell disposed over the interlayer that is lattice mismatched with respect to the middle subcell and having a fourth band gap smaller than the second band gap; and either a thin (approximately 2-6 mil) substrate and/or a rigid coverglass supporting the first, second, and third solar subcells.
    Type: Application
    Filed: September 24, 2007
    Publication date: March 26, 2009
    Applicant: Emcore Corporation
    Inventors: Tansen Varghese, Arthur Cornfeld, Jacqueline Diaz
  • Publication number: 20090078309
    Abstract: A method of forming a multijunction solar cell including an upper subcell, a middle subcell, and a lower subcell, the method including: providing first substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a barrier layer over the second subcell to reduce threading dislocations; forming a grading interlayer over the barrier layer, the grading interlayer having a third band gap greater than the second band gap; and forming a third solar subcell over the grading interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell.
    Type: Application
    Filed: September 24, 2007
    Publication date: March 26, 2009
    Applicant: Emcore Corporation
    Inventors: Arthur Cornfeld, Mark A. Stan, Tansen Varghese, Fred Newman
  • Patent number: 7498645
    Abstract: Disclosed are detector devices and related methods. In an AlN EUV detector a low temperature AlN layer is deposed above an AlN buffer layer. In one embodiment, the low temperature AlN layer is deposed at about 800° C. Pulsed NH3 is used when growing an AlN epilayer above the low temperature layer. Numerous embodiments are disclosed.
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: March 3, 2009
    Assignee: III-N Technology, Inc.
    Inventors: Jing Li, Zhaoyang Fan, Jingyu Lin, Hongxing Jiang
  • Publication number: 20090050205
    Abstract: The present invention relates to a semiconductor compound having the general formula AxB1-xCy, to a method of optimizing positions of a conduction band and a valence band of a semiconductor material using said semiconductor compound, and to a photoactive device comprising said semiconductor compound.
    Type: Application
    Filed: December 20, 2006
    Publication date: February 26, 2009
    Applicant: Sony Deutschland GMBH
    Inventors: Michael Duerr, Silvia Rosselli, Gabriele Nelles, Akio Yasuda
  • Patent number: 7494936
    Abstract: A method for electrochemical etching of a semiconductor material using positive potential dissolution (PPD) in solutions that do not contain hydrofluoric acid (HF-free solutions). The method includes immersing an as-cut semiconductor material in an etching solution, and positive biasing at atypically highly positive (anodic) potentials, thereby significantly increasing the value of the anodic current density (measured as A/cm2) of the semiconductor material. The application of positive biasing at atypically highly positive (anodic) potentials, is combined with specifically controlling and directing illumination on the semiconductor material surface contacted and wetted by the etching solution. This is done for a necessary and sufficient period of time to enable a positive synergistic effect on the rate and extent of etching of the semiconductor material therefrom.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: February 24, 2009
    Assignee: Technion Research & Development Foundation Ltd.
    Inventors: Yair Ein-Eli, David Starosvetsky, Joseph Yahalom
  • Publication number: 20090044862
    Abstract: A solar cell comprises a substrate; an n-type barium silicide layer being arranged on the substrate and containing Ba atoms and Si atoms; an n+-type barium silicide layer being arranged on the n-type barium silicide layer and containing impurity atoms which are at least one of atoms belonging to Groups 13 to 15 of the periodic table, Ba atoms, and Si atoms; an upper electrode arranged on the n+-type barium silicide layer; and a lower electrode arranged on the substrate.
    Type: Application
    Filed: July 25, 2008
    Publication date: February 19, 2009
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventor: Takashi Suemasu
  • Publication number: 20090038677
    Abstract: The present invention discloses a solar cell having a multi-layered structure that is used to generate, transport, and collect electric charges. The multi-layered nanostructure comprises a cathode, a conducting metal layer, a photo-active layer, a hole-transport layer, and an anode. The photo-active layer comprises a tree-like nanostructure array and a conjugate polymer filler. The tree-like nanostructure array is used as an electron acceptor while the conjugate polymer filler is as an electron donor. The tree-like nanostructure array comprises a trunk part and a branch part. The trunk part is formed in-situ on the surface of the conducting metal layer and is used to provide a long straight transport pathway to transport electrons. The large contact area between the branch part and the conjugate polymer filler provides electron-hole separation.
    Type: Application
    Filed: April 21, 2008
    Publication date: February 12, 2009
    Applicant: NATIONAL TAIWAN UNIVERSITY
    Inventors: Wei-Fang Su, Chun-Wei Chen, Jih-Jen Wu, Yun-Yue Lin
  • Patent number: 7488890
    Abstract: On a surface of a GaAs substrate, layers to be a top cell are formed by epitaxial growth. On the top cell, layers to be a bottom cell are formed. Thereafter, on a surface of the bottom cell, a back surface electrode is formed. Thereafter, a glass plate is adhered to the back surface electrode by wax. Then, the GaAs substrate supported by the glass plate is dipped in an alkali solution, whereby the GaAs substrate is removed. Thereafter, a surface electrode is formed on the top cell. Finally the glass plate is separated from the back surface electrode. In this manner, a compound solar battery that improves efficiency of conversion to electric energy can be obtained.
    Type: Grant
    Filed: March 22, 2004
    Date of Patent: February 10, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tatsuya Takamoto, Takaaki Agui