Heterojunction Patents (Class 438/94)
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Method for manufacturing gallium nitride based transparent conductive oxidized film ohmic electrodes
Patent number: 7022597Abstract: A method for manufacturing gallium nitride based transparent conductive oxidized film ohmic electrodes includes forming a transparent conductive film on a GaN layer, forming a transparent conductive hetero-junction of opposing electrical characteristics on a transparent conductive film on the surface of the GaN layer through an ion diffusion process, and laying a metallic thick film on the surface of the transparent conductive hetero-junction for wiring process in the later fabrication operation. Thus through the electron and hole tunneling effect in the ion diffusion process the Fermi level of the hetero-junction may be improved to form an ohmic contact electrode.Type: GrantFiled: July 16, 2004Date of Patent: April 4, 2006Assignee: Tekcore Co., Ltd.Inventors: Lung-Han Peng, Han-Ming Wu, Sung-Li Wang, Chia-Wei Chang, Chin-Yi Lin -
Patent number: 7015053Abstract: A nitride semiconductor laser device has an improved stability of the lateral mode under high output power and a longer lifetime, so that the device can be applied to write and read light sources for recording media with high capacity. The nitride semiconductor laser device includes an active layer, a p-side cladding layer, and a p-side contact layer laminated in turn. The device further includes a waveguide region of a stripe structure formed by etching from the p-side contact layer. The stripe width provided by etching is within the stripe range of 1 to 3 ?m and the etching depth is below the thickness of the p-side cladding layer of 0.1 ?m and above the active layer. Particularly, when a p-side optical waveguide layer includes a projection part of the stripe structure and a p-type nitride semiconductor layer on the projection part and the projection part of the p-side optical waveguide layer has a thickness of not more than 1 ?m, an aspect ratio is improved in far field image.Type: GrantFiled: November 4, 2003Date of Patent: March 21, 2006Assignee: Nichia CorporationInventors: Tokuya Kozaki, Masahiko Sano, Shuji Nakamura, Shinichi Nagahama
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Patent number: 7008806Abstract: Disclosed is a method of determining causes of intrinsic oscillations in a double-barrier quantum-well intrinsic oscillator comprising developing an emitter quantum-well (EQW) from a double-barrier quantum-well system (DBQWS); coupling the EQW to a main quantum-well (MQW), wherein the MQW is defined by double-barrier heterostructures of a resonant tunneling diode; using energy subband coupling to induce quantum-based fluctuations in the EQW; creating intrinsic oscillations in electron density and electron current in the DBQWS; forming a distinct subband structure based on the intrinsic oscillations; and identifying a THz-frequency signal source based on the quantum-based fluctuations, wherein the intrinsic oscillations comprise maximum subband coherence, partial subband coherence, and minimum subband coherence, wherein the energy subband is a quantum mechanical energy subband, wherein the intrinsic oscillations occur proximate to a bias voltage point in the range of 0.224 V and 0.Type: GrantFiled: August 24, 2004Date of Patent: March 7, 2006Assignee: The United States of America as represented by the Secretary of the ArmyInventors: Peiji Zhao, Dwight Woolard
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Patent number: 6989287Abstract: A method for producing a nitride semiconductor comprising growing at least first to third nitride semiconductor layers on a substrate; said first nitride semiconductor layer being grown at 400–600° C.; and said second and third nitride semiconductor layers being grown on said first nitride semiconductor layer at 700–1,300° C. after heat-treating said first nitride semiconductor layer at 700–1,300° C.; used as a carrier gas supplied near said substrate together with a starting material gas being a hydrogen/nitrogen mixture gas containing 63% or more by volume of hydrogen during growing said second nitride semiconductor layer, and a hydrogen/nitrogen mixture gas containing 50% or more by volume of nitrogen during growing said third nitride semiconductor layer; and said second nitride semiconductor layer being formed to a thickness of more than 1 ?m.Type: GrantFiled: June 24, 2004Date of Patent: January 24, 2006Assignee: Hitachi Cable, Ltd.Inventors: Hajime Fujikura, Kazuyuki Iizuka
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Patent number: 6974976Abstract: A method of manufacturing improved thin-film solar cells entirely by sputtering includes a high efficiency back contact/reflecting multi-layer containing at least one barrier layer consisting of a transition metal nitride. A copper indium gallium diselenide (Cu(InXGa1?X)Se2) absorber layer (X ranging from 1 to approximately 0.7) is co-sputtered from specially prepared electrically conductive targets using dual cylindrical rotary magnetron technology. The band gap of the absorber layer can be graded by varying the gallium content, and by replacing the gallium partially or totally with aluminum. Alternately the absorber layer is reactively sputtered from metal alloy targets in the presence of hydrogen selenide gas. RF sputtering is used to deposit a non-cadmium containing window layer of ZnS. The top transparent electrode is reactively sputtered aluminum doped ZnO. A unique modular vacuum roll-to-roll sputtering machine is described.Type: GrantFiled: September 24, 2003Date of Patent: December 13, 2005Assignee: MiasoleInventor: Dennis R. Hollars
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Patent number: 6969627Abstract: The specification discloses a light-emitting diode and the corresponding manufacturing method. A GaN thick film with a slant surface is formed on the surface of a substrate. An epitaxial slant surface is naturally formed using the properties of the GaN epitaxy. An LED structure is grown on the GaN thick film to form an LED device. This disclosed method and device can simplify the manufacturing process. The invention further uses the GaN thick film epitaxial property to make various kinds of LED chips with multiple slant surfaces and different structures. Since the surface area for emitting light on the chip increases and the multiple slant surfaces reduce the chances of total internal reflections, the light emission efficiency of the invention is much better than the prior art.Type: GrantFiled: May 13, 2003Date of Patent: November 29, 2005Assignee: Industrial Technology Research InstituteInventors: Shyi-Ming Pan, Jenq-Dar Tsay, Ru-Chin Tu, Jung-Tsung Hsu
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Patent number: 6967345Abstract: A quantum well infrared photodetector (QWIP) that provides two-color image sensing. Two different quantum wells are configured to absorb two different wavelengths. The QWIPs are arrayed in a focal plane array (FPA). The two-color QWIPs are selected for readout by selective electrical contact with the two different QWIPs or by the use of two different wavelength sensitive gratings.Type: GrantFiled: May 4, 1999Date of Patent: November 22, 2005Assignee: California Institute of TechnologyInventors: Sarath D. Gunapala, Kwong Kit Choi, Sumith V. Bandara
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Patent number: 6946317Abstract: An efficient method of fabricating a high-quality microstructure having a smooth surface. The method includes detaching a layer from a base structure to provide a carrier substrate having a detached surface, and then forming a microstructure on the detached surface of the carrier substrate by depositing an epitaxial layer on the detached surface of a carrier substrate. Also included is a microstructure fabricated from such method.Type: GrantFiled: November 3, 2003Date of Patent: September 20, 2005Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.Inventors: Bruce Faure, Fabrice Letertre
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Patent number: 6946318Abstract: A photodetector device includes a plurality of Ge epilayers that are grown on a substrate and annealed in a defined temperature range. The Ge epilayers form a tensile strained Ge layer that allows the photodetector device to operate efficiently in the C-band and L-band.Type: GrantFiled: September 28, 2004Date of Patent: September 20, 2005Assignee: Massachusetts Institute of TechnologyInventors: Kazumi Wada, Lionel C. Kimerling, Yasuhiko Ishikawa, Douglas D. Cannon, Jifeng Liu
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Patent number: 6890791Abstract: A semiconductor substrate for a light-emitting diode, heterojunction transistor or the like. Included is a buffer region of an aluminum-containing nitride or the like grown epitaxially on a baseplate of silicon or a silicon compound. A dislocation-refracting region of an indium-containing nitride is grown epitaxially on the buffer region in order to provide a major surface having a multiplicity of protuberances of pyramidal shape capable of refracting the dislocations created in the buffer region. A leveling region of a nitride, not containing indium, is formed on the major surface of the dislocation refracting region in order to provide a major surface of greater levelness than the transition refracting region. The leveling region is reduced in dislocation density owing to the interposition of the dislocation refracting region between buffer region and leveling region.Type: GrantFiled: March 30, 2004Date of Patent: May 10, 2005Assignee: Sanken Electric Co., Ltd.Inventors: Koji Ohtsuka, Junji Sato, Tetsuji Moku, Masahiro Sato
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Patent number: 6852602Abstract: A multi-layer film 10 is formed by stacking a Si1-x1-y1Gex1Cy1 layer (0?x1<1 and 0<y1<1) having a small Ge mole fraction, e.g., a Si0.785Ge0.2C0.015 layer 13, and a Si1-x2-y2Gex2Cy2 layer (0<x2?1 and 0?y2<1) (where x1<x2 and y1>y2) having a high Ge mole fraction, e.g., a Si0.2Ge0.8 layer 12. In this manner, the range in which the multi-layer film serves as a SiGeC layer with C atoms incorporated into lattice sites extends to high degrees in which a Ge mole fraction is high.Type: GrantFiled: January 30, 2002Date of Patent: February 8, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshihiko Kanzawa, Tohru Saitoh, Katsuya Nozawa, Minoru Kubo, Yoshihiro Hara, Takeshi Takagi, Takahiro Kawashima
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Patent number: 6841411Abstract: A method of forming an image sensor array uses a transparent top conductive layer first as an etch mask in forming inter-pixel trenches and then as an etch stop in a planarization step, whereafter the top conductive layer is integral to operation of the completed image sensor array. During fabrication, a stack of layers is formed to collectively define a continuous photosensitive structure over an array area. The operationally dependent transparent top conductive layer is then used in the patterning of the photosensitive structure to form trenches between adjacent pixels. An insulating material is deposited within the trenches and the top conductive layer is then used as the etch stop in planarizing the insulating material. The method includes providing a connectivity layer that provides electrical continuity along the patterned top conductive layer.Type: GrantFiled: June 30, 2003Date of Patent: January 11, 2005Assignee: Agilent Technologies, Inc.Inventor: Ronnie P. Varghese
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Publication number: 20040266053Abstract: A method of forming an image sensor array uses a transparent top conductive layer first as an etch mask in forming inter-pixel trenches and then as an etch stop in a planarization step, whereafter the top conductive layer is integral to operation of the completed image sensor array. During fabrication, a stack of layers is formed to collectively define a continuous photosensitive structure over an array area. The operationally dependent transparent top conductive layer is then used in the patterning of the photo-sensitive structure to form trenches between adjacent pixels. An insulating material is deposited within the trenches and the top conductive layer is then used as the etch stop in planarizing the insulating material. The method includes providing a connectivity layer that provides electrical continuity along the patterned top conductive layer.Type: ApplicationFiled: June 30, 2003Publication date: December 30, 2004Inventor: Ronnie P. Varghese
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Patent number: 6830945Abstract: A method for fabricating a non-planar heterostructure field effect transistor using group III-nitride materials with consistent repeatable results is disclosed. The method provides a substrate on which at least one layer of semiconductor material is deposited. An AlN layer is deposited on the at least one layer of semiconductor material. A portion of the AlN layer is removed using a solvent to create a non-planar region with consistent and repeatable results. The at least one layer beneath the AlN layer is insoluble in the solvent and therefore acts as an etch stop, preventing any damage to the at least one layer beneath the AlN layer. Furthermore, should the AlN layer incur any surface damage as a result of the reactive ion etching, the damage will be removed when exposed to the solvent to create the non-planar region.Type: GrantFiled: March 12, 2003Date of Patent: December 14, 2004Assignee: HRL Laboratories, LLCInventors: Jeong Sun Moon, Paul Hashimoto, Wah S. Wong, David E. Grider
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Patent number: 6821797Abstract: For manufacturing a semiconductor device, such as thin-film solar battery, comprising a base body made of an organic high polymer material, an oxide electrode film and semiconductor thin film each containing at least one kind of group IV elements on the oxide electrode film, one of the semiconductor thin films in contact with the oxide electrode film is stacked by sputtering in a non-reducing atmosphere such as atmosphere not containing hydrogen gas, for example. Thereby, it is ensured that granular products as large as and beyond 3 nm are not contained substantially at the interface between the oxide electrode film and that semiconductor thin film. Therefore, a semiconductor thin film such as amorphous semiconductor thin film can be stacked with enhanced adherence on a plastic substrate having an oxide electrode film like ITO film on its surface.Type: GrantFiled: September 26, 2003Date of Patent: November 23, 2004Assignee: Sony CorporationInventors: Akio Machida, Dharam Pal Gosain, Takashi Noguchi, Setsuo Usui
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Publication number: 20040221792Abstract: One aspect of this disclosure relates to a method for forming a strained silicon over silicon germanium (Si/SiGe) structure. In various embodiments, germanium ions are implanted into a silicon substrate with a desired dose and energy to be located beneath a surface silicon layer in the substrate. The implantation of germanium ions at least partially amorphizes the surface silicon layer. The substrate is heat treated to regrow a crystalline silicon layer over a resulting silicon germanium layer using a solid phase epitaxial (SPE) process. The crystalline silicon layer is strained by a lattice mismatch between the silicon germanium layer and the crystalline silicon layer. Other aspects are provided herein.Type: ApplicationFiled: May 7, 2003Publication date: November 11, 2004Applicant: Micron Technology, Inc.Inventor: Leonard Forbes
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Patent number: 6790701Abstract: A multi-wavelength semiconductor image sensor comprises a p-type Hg0.7Cd0.3Te photo-absorbing layer formed on a single crystal CdZnTe substrate, a CdTe isolation layer deposited on the photo-absorbing layer, a p-type Hg0.77Cd0.23Te photo-absorbing layer deposited on the CdTe isolation layer, n+ regions which are formed in these photo-absorbing layers and form a pn-junction with each of these photo-absorbing layers, an indium electrode connected to each of these n+ regions and a ground electrode connected to the photo-absorbing layer, the semiconductor isolation layer being electrically isolated from the photo-absorbing layer.Type: GrantFiled: September 6, 2002Date of Patent: September 14, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Keitaro Shigenaka, Fumio Nakata
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Patent number: 6777260Abstract: A method of forming sub-lithographic sized contact holes in semiconductor material, which includes forming layers of etch mask materials, and forming intersecting first and second trenches in the etch mask layers, where through-holes are formed completely through the etch mask layers only where the first and second trenches intersect. The first and second trenches are made by the formation and subsequent removal of very thin vertical layers of material. The width dimensions of the trenches, and therefore of the through-holes, are sub-lithographic because they are dictated by the thickness of the thin vertical layers of material, and not by conventional photo lithographic processes used to form those vertical layers of material. The sub-lithographic through-holes are then used to etch sub-lithographic sized contact holes in underlying semiconductor materials.Type: GrantFiled: August 14, 2003Date of Patent: August 17, 2004Assignee: Silicon Storage Technology, Inc.Inventor: Bomy Chen
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Publication number: 20040157358Abstract: A group III nitride semiconductor film involving few lattice defects and having a large thickness, and a process for making the film are disclosed. Dry-etching is conducted while a quartz substrate and a group III nitride semiconductor are placed on the top of a lower electrode. Nano-pillars (50) are formed on the top of the group III nitride semiconductor (101). Another group III nitride semiconductor film (51) is deposited on the nano-pillars (50).Type: ApplicationFiled: April 1, 2004Publication date: August 12, 2004Inventors: Kazumasa Hiramatsu, Hideto Miyake, Harumasa Yoshida, Tatsuhiro Urushido, Yusuke Terada
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Patent number: 6773940Abstract: A tunnel diode has a quantum well having at least one layer of semiconductor material. The tunnel diode also has a pair of injection layers on either side of the quantum well. The injection layers comprise a collector layer and an emitter layer. A barrier layer is positioned between each of the injection layers and the quantum well. The quantum well has an epitaxial relationship with the emitter layer. An amount of one element of the well layer is increased to increase the lattice constant a predetermined amount. The lattice constant may have a reduction in the conduction band energy. A second element is added to the well layer to increase the conduction band energy but not to change the lattice constant. By controlling the composition in this matter, the negative resistance, and thus the effective mass, may be controlled for various diode constructions.Type: GrantFiled: February 15, 2002Date of Patent: August 10, 2004Assignee: The Boeing CompanyInventor: Joel N. Schulman
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Publication number: 20040137735Abstract: On a Si substrate are formed successively a Ge interfacial layer as a dislocation controlling layer and a SiGe film. Then, at least at the region of the SiGe film near the Si substrate are formed 90 degrees dislocations.Type: ApplicationFiled: November 18, 2003Publication date: July 15, 2004Applicant: NAGOYA UNIVERSITYInventors: Akira Sakai, Osamu Nakatsuka, Shigeaki Zaima, Yukio Yasuda
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Patent number: 6756325Abstract: Several methods for producing an active region for a long wavelength light emitting device are disclosed. In one embodiment, the method comprises placing a substrate in an organometallic vapor phase epitaxy (OMVPE) reactor, the substrate for supporting growth of an indium gallium arsenide nitride (InGaAsN) film, supplying to the reactor a group-III-V precursor mixture comprising arsine, dimethylhydrazine, alkyl-gallium, alkyl-indium and a carrier gas, where the arsine and the dimethylhydrazine are the group-V precursor materials and where the percentage of dimethylhydrazine substantially exceeds the percentage of arsine, and pressurizing the reactor to a pressure at which a concentration of nitrogen commensurate with light emission at a wavelength longer than 1.2 um is extracted from the dimethylhydrazine and deposited on the substrate.Type: GrantFiled: May 7, 2002Date of Patent: June 29, 2004Assignee: Agilent Technologies, Inc.Inventors: David P. Bour, Tetsuya Takeuchi, Ashish Tandon, Ying-Lan Chang, Michael R. T. Tan, Scott Corzine
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Patent number: 6750075Abstract: A heterostructure or multilayer semiconductor structure having lattice matched layers with different bandgaps is grown by MOCVD. More specifically, a wide bandgap material such as AlInSb or GaInSb is grown on a substrate to form a lower-contact layer. An n-type active layer is lattice matched to the lower contact layer. The active layer should be of a narrow bandgap material, such as InAsSb, InTlSb, InBiSb, or InBiAsSb. A p-type upper contact layer is then grown on the active layer and a multi-color infrared photodetector has been fabricated.Type: GrantFiled: May 28, 2002Date of Patent: June 15, 2004Inventor: Manijeh Razeghi
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Patent number: 6746971Abstract: An organic memory cell made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer and passive layer. The controllably conductive media changes its impedance when an external stimuli such as an applied electric field is imposed thereon. Methods of making the organic memory devices/cells, methods of using the organic memory devices/cells, and devices such as computers containing the organic memory devices/cells are also disclosed.Type: GrantFiled: December 5, 2002Date of Patent: June 8, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Minh Van Ngo, Sergey D. Lopatin, Suzette K. Pangrle, Nicholas H. Tripsas, Hieu T. Pham
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Publication number: 20040103936Abstract: A metal chalcogenide composite nano-particle comprising a metal capable of forming p-type semiconducting chalcogenide nano-particles and a metal capable of forming n-type semiconducting chalcogenide nano-particles, wherein at least one of the metal chalcogenides has a band-gap between 1.0 and 2.9 eV and the concentration of the metal capable of forming p-type semiconducting chalcogenide nano-particles is at least 5 atomic percent of the metal and is less than 50 atomic percent of the metal; a dispersion thereof; a layer comprising the nano-particles; and a photovoltaic device comprising the layer.Type: ApplicationFiled: September 11, 2003Publication date: June 3, 2004Applicant: AGFA-GEVAERTInventor: Hieronymus Andriessen
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Publication number: 20040079408Abstract: A method of reducing propagation of threading dislocations into active areas of an optoelectronic device having a III-V material system includes growing a metamorphic buffer region in the presence of an isoelectronic surfactant. A first buffer layer may be lattice matched to an adjacent substrate and a second buffer layer may be lattice matched to device layers disposed upon the second buffer layer. Moreover, multiple metamorphic buffer layers fabricated in this manner may be used in a single given device allowing multiple layers to have their band gaps and lattice constants independently selected from those of the rest of the device.Type: ApplicationFiled: October 23, 2002Publication date: April 29, 2004Applicant: The Boeing CompanyInventors: Christopher M. Fetzer, James H. Ermer, Richard R. King, Peter C. Colter
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Patent number: 6720200Abstract: Using a mask opening a gate region, an undoped GaAs layer is selectively etched with respect to an undoped Al0.2Ga0.8As layer by dry etching with introducing a mixture gas of a chloride gas containing only chlorine and a fluoride gas containing only fluorine (e.g. BCl3+SF6 or so forth). By about 100% over-etching is performed for the undoped GaAs layer, etching (side etching) propagates in transverse direction of the undoped GaAs layer. With using the mask, a gate electrode of WSi is formed. Thus, a gap in a width of about 20 nm is formed by etching in the transverse direction on the drain side of the gate electrode. By this, a hetero junction FET having reduced fluctuation of characteristics of an FET, such as a threshold value, lower a rising voltage and higher breakdown characteristics.Type: GrantFiled: May 22, 2001Date of Patent: April 13, 2004Assignee: NEC CorporationInventors: Keiko Yamaguchi, Naotaka Iwata
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Patent number: 6709883Abstract: A light emitting diode (LED) and method of making the same are disclosed. The present invention uses a layer of elastic transparent adhesive material to bond a transparent substrate and a LED epitaxial structure having a light-absorbing substrate. The light absorbing substrate is then removed to form a LED having a transparent substrate. By the use of the transparent substrate, the light emitting efficiency of the LED can be significantly improved.Type: GrantFiled: April 6, 2001Date of Patent: March 23, 2004Assignee: United Epitaxy Co., Ltd.Inventors: Kuang-Neng Yang, Tzer-Perng Chen, Chih-Sung Chang
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Patent number: 6706574Abstract: The field effect device consisting of a substrate, a conducting backplane formed in the substrate, a source and a drain disposed above the conductive backplane, a gate insultatively disposed above the substrate between the source and drain, and a backgate contact electrically coupled to the conducting backplane.Type: GrantFiled: May 17, 2002Date of Patent: March 16, 2004Assignee: Raytheon CompanyInventor: Berinder Brar
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Patent number: 6706959Abstract: A photoelectric conversion element is disposed in each of a plurality of recesses of a support. Light reflected by the inside surface of the recess shines on the photoelectric conversion element. The photoelectric conversion element has an approximately spherical shape and has the following structure. The outer surface of a center-side n-type amorphous silicon (a-Si) layer is covered with a p-type amorphous SiC (a-SiC) layer having a wider optical band gap than a-Si does, whereby a pn junction is formed. A first conductor of the support is connected to the p-type a-SiC layer of the photoelectric conversion element at the bottom or its neighborhood of the recess. A second conductor, which is insulated from the first conductor by an insulator, of the support is connected to the n-type a-Si layer of the photoelectric conversion element.Type: GrantFiled: November 21, 2001Date of Patent: March 16, 2004Assignee: Clean Venture 21 CorporationInventors: Yoshihiro Hamakawa, Mikio Murozono, Hideyuki Takakura
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Publication number: 20040038443Abstract: An apparatus is directed to increasing the resolution of digital color imaging that includes a photosensing semiconductor structure. The apparatus provides a monocrystalline silicon substrate, a first buffer layer epitaxially formed and overlying the monocrystalline silicon substrate, and a first photodiode layer overlying the first buffer layer and operable to provide a first signal indicative of a color associated with a first wavelength of light. The apparatus may further provide a second buffer layer overlying the first photodiode layer and a second photodiode layer overlying the second buffer layer operable to provide a second signal indicative of a color associated with a second wavelength of light.Type: ApplicationFiled: October 15, 2002Publication date: February 26, 2004Inventor: Jinbao Jiao
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Patent number: 6682950Abstract: A light emitting diode (LED) and method of making the same are disclosed. The present invention uses a layer of transparent adhesive material to bond a transparent substrate and a LED epitaxial structure having a light-absorbing substrate. The light absorbing substrate is then removed to form a LED having a transparent substrate. By the use of the transparent substrate, the light emitting efficiency of the LED can be significantly improved.Type: GrantFiled: April 5, 2001Date of Patent: January 27, 2004Assignee: United Epitaxy Company, Ltd.Inventors: Kuang-Neng Yang, Tzer-Perng Chen, Chih-Sung Chang
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Publication number: 20030224549Abstract: A method of epitaxially growing backward diodes and diodes grown by the method are presented herein. More specifically, the invention utilizes epitaxial-growth techniques such as molecular beam epitaxy in order to produce a thin, highly doped layer at the p-n junction in order to steepen the voltage drop at the junction, and thereby increase the electric field. By tailoring the p and n doping levels as well as adjusting the thin, highly doped layer, backward diodes may be consistently produced and may be tailored in a relatively easy and controllable fashion for a variety of applications. The use of the thin, highly doped layer provided by the present invention is discussed particularly in the context of InGaAs backward diode structures, but may be tailored to many diode types.Type: ApplicationFiled: January 8, 2003Publication date: December 4, 2003Inventors: Joel N. Schulman, David H. Chow
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Publication number: 20030203533Abstract: A single mask process is described for making a trench type fast recovery process. The single mask defines slots in a photoresist for locally removing strips of nitride and oxide from atop silicon and for subsequently etching trenches in the silicon. A boron implant is carried out in the bottoms of the trenches to form local P/N junctions. The oxide beneath the nitride is then fully stripped in the active area and only partly stripped in the termination area in which the trenches are wider spaced than in the active area. Aluminum is then deposited atop the active area and in the trenches, but is blocked from contact with silicon in the active area by the remaining nitride layer.Type: ApplicationFiled: April 25, 2002Publication date: October 30, 2003Applicant: International Rectifier Corp.Inventor: Igor Bol
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Patent number: 6632684Abstract: There is disclosed an improved method of manufacturing of an optical device (40), particularly semiconductor optoelectronic devices such as laser diodes, optical modulators, optical amplifiers, optical switches, and optical detectors. The invention provides a method of manufacturing optical device (40), a device body portion (15) from which the device (40) is to be made including a Quantum Well (QW) structure (30), the method including the step of: processing the device body portion (15) so as to create extended defects at least in a portion (53) of the device portion (5). Each extended defect is a structural defect comprising a plurality of adjacent “point” defects.Type: GrantFiled: February 20, 2001Date of Patent: October 14, 2003Assignee: The University Court of The University of GlasgowInventors: John Haig Marsh, Craig James Hamilton, Stuart Duncan McDougall, Olek Peter Kowalski
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Publication number: 20030136909Abstract: A special infrared photodetector is operable at high temperatures. The detector is a very wideband detector which may be operated in a direct detection mode or in a heterodyne mode. A multiple quantum well photodetector includes a plurality of wells and a plurality of barriers formed of alternating layers of gallium-arsenide and aluminum-gallium-arsenide material respectively. The gallium-arsenide layers are highly doped with an n-type dopant such as silicon atoms. The high doping produces an unexpected result of improved operational efficiency at elevated temperatures. Photodetectors of these inventions have a large number of quantum well structures to improve absorption or interaction cross section. In all versions, the middle portion of wells include a special region of a highly doped gallium arsenide material in a density of about one to three trillion silicon atoms per square centimeter.Type: ApplicationFiled: January 23, 2002Publication date: July 24, 2003Inventor: James Plante
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Publication number: 20030138984Abstract: A method is provided for etching quaternary interface layers of InxGa1−xAsyP1−y which are formed between layers of GaAs and InGaP in heterojunction bipolar transistors (HBTs). In accordance with the method, the interface is exposed by etching the GaAs layer with an etchant that is selective to InGaP. The interface is then etched with a dilute aqueous solution of HCl and H2O2 that is selective to InGaP. The controlled etching provided by this methodology allows HBTs to be manufactured with more sophisticated, near ideal designs which may contain multiple GaAs/InGaP interfaces.Type: ApplicationFiled: December 21, 2001Publication date: July 24, 2003Inventors: Mariam G. Sadaka, Jonathan K. Abrokwah
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Patent number: 6586272Abstract: The present invention relates to the method for manufacturing an MSM photodetector using a HEMT structure incorporating a low-temperature grown semiconductor. The object of the present invention is to improve the speed characteristic of an MSM photodetector by using a HEMT structure incorporating a low-temperature grown semiconductor. The use of a HEMT structure incorporating a low-temperature grown semiconductor can reduce the number of holes reaching the metal electrode of MSM detectors, resulting in reduced hole current. As a result, the photocurrent response of the MSM detector using a HEMT structure incorporating a low-temperature grown semiconductor is dominated by electron current, resulting in a significant improvement in speed performance.Type: GrantFiled: April 3, 2002Date of Patent: July 1, 2003Assignee: Kwangju Institute of Science and TechnologyInventor: Jong In Song
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Publication number: 20030119223Abstract: The present invention relates to the method for manufacturing an MSM photodetector using a HEMT structure incorporating a low-temperature grown semiconductor. The object of the present invention is to improve the speed characteristic of an MSM photodetector by using a HEMT structure incorporating a low-temperature grown semiconductor.Type: ApplicationFiled: April 3, 2002Publication date: June 26, 2003Inventor: Jong-In Song
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Patent number: 6580027Abstract: Organic photosensitive optoelectronic devices are disclosed. The devises comprise photoconductive organic thin films in a heterostructure, which include an exciton blocking layer to enhance device efficiency. The use of fullerenes in the electron conducting layer has lead to devices with high efficiency. Single heterostructure, stacked and wave-guide type embodiments are disclosed. Devices having multilayer structures and an exciton blocking layer are also disclosed. Guidelines for selection of exciton blocking layers are provided.Type: GrantFiled: June 11, 2001Date of Patent: June 17, 2003Assignee: Trustees of Princeton UniversityInventors: Stephen R. Forrest, Peter Peumans
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Publication number: 20030102023Abstract: Sulfur is used to improve the performance of CIGS devices prepared by the evaporation of a single source ZIS type compound to form a buffer layer on the CIGS. The sulfur may be evaporated, or contained in the ZIS type material, or both. Vacuum evaporation apparatus of many types useful in the practice of the invention are known in the art. Other methods of delivery, such as sputtering, or application of a thiourea solution, may be substituted for evaporation.Type: ApplicationFiled: September 20, 2002Publication date: June 5, 2003Inventor: Alan E. Delahoy
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Publication number: 20030102469Abstract: A heteroepitaxial structure is made using nanocrystals that are formed closer together than normal lithography patterning would allow. The nanocrystals are oxidized and thus selectively etchable with respect to the substrate and surrounding material. In one case the oxidized nanocrystals are removed to expose the substrate at those locations and selective epitaxial germanium is then grown at those exposed substrate locations. The inevitable formation of the misfit dislocations does minimal harm because they are terminated at the surrounding material. In another case the surrounding material is removed and the germanium is epitaxially grown at the exposed substrate where the surrounding material is removed. The resulting misfit dislocations in the germanium terminate at the oxidized nanocrystals.Type: ApplicationFiled: November 30, 2001Publication date: June 5, 2003Inventors: Robert E. Jones, Bruce E. White
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Patent number: 6569704Abstract: An optical semiconductor device having a plurality of GaN-based semiconductor layers containing a strained quantum well layer in which the strained quantum well layer has a piezoelectric field that depends on the orientation of the strained quantum well layer when the quantum layer is grown. In the present invention, the strained quantum well layer is grown with an orientation at which the piezoelectric field is less than the maximum value of the piezoelectric field strength as a function of the orientation. In devices having GaN-based semiconductor layers with a wurtzite crystal structure, the growth orientation of the strained quantum well layer is tilted at least 1° from the {0001} direction of the wurtzite crystal structure. In devices having GaN-based semiconductor layers with a zincblende crystal structure, the growth orientation of the strained quantum well layer is tilted at least 1° from the {111} direction of the zincblende crystal structure.Type: GrantFiled: November 21, 2000Date of Patent: May 27, 2003Assignee: Lumileds Lighting U.S., LLCInventors: Tetsuya Takeuchi, Norihide Yamada, Hiroshi Amano, Isamu Akasaki
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Patent number: 6566595Abstract: A solar cell having a p-type semiconductor layer and an n-type semiconductor layer made of a first compound semiconductor material, and a semiconductor layer sandwiched between the p-type semiconductor layer and the n-type semiconductor layer. The semiconductor layer includes at least a quantum well layer which is made of a second compound semiconductor material and has a plurality of projections of at least two different sizes.Type: GrantFiled: October 29, 2001Date of Patent: May 20, 2003Assignee: Sharp Kabushiki KaishaInventor: Yoshiyuki Suzuki
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Patent number: 6562702Abstract: Provided is a method and apparatus for the production of a semiconductor device, the method and the apparatus producing a high quality and highly functional semiconductor device efficiently at low temperatures in a short time and also a high quality and highly functional semiconductor device produced by the method and apparatus. The semiconductor device is produced by forming a film of a nitride compound on a substrate having heat resistance at 600° C. or less, wherein the nitride compound includes one or more elements selected from group IIIA elements of the periodic table and a nitrogen atom and produces photoluminescence at the band edges at room temperature.Type: GrantFiled: January 31, 2001Date of Patent: May 13, 2003Assignee: Fuji Xerox Co., Ltd.Inventor: Shigeru Yagi
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Patent number: 6548751Abstract: A thin-film flexible solar cell built on a plastic substrate comprises a cadmium telluride p-type layer and a cadmium sulfide n-type layer sputter deposited onto a plastic substrate at a temperature sufficiently low to avoid damaging or melting the plastic and to minimize crystallization of the cadmium telluride. A transparent conductive oxide layer overlaid by a bus bar network is deposited over the n-type layer. A back contact layer of conductive metal is deposited underneath the p-type layer and completes the current collection circuit. The semiconductor layers may be amorphous or polycrystalline in structure.Type: GrantFiled: June 25, 2001Date of Patent: April 15, 2003Assignee: SolarFlex Technologies, Inc.Inventors: Lawrence H. Sverdrup, Jr., Norman F. Dessel, Adrian Pelkus
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Patent number: 6545258Abstract: Photo-sensors, such as photo-diodes, are formed using regions with cross-sections that increase the overall quantum efficiency of the resulting photo-sensor. The cross-sections have additional (e.g., interior) side-wall interfaces, and, in some embodiments, an additional, relatively shallow bottom interface. The increased total side-wall area and any additional shallow bottom area increase the total photo-junction volume located near the surface of the device. As a result, a greater fraction of photons having relatively small absorption lengths (e.g., blue light) will be absorbed within a photo-junction, thereby increasing the quantum efficiency for those photons. The present invention enables photo-sensors to be implemented with more uniform spectral response.Type: GrantFiled: March 30, 2001Date of Patent: April 8, 2003Assignee: Pixim, Inc.Inventors: Hui Tian, William R. Bidermann, David X. D. Yang, Yi-Hen Wei
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Patent number: 6524883Abstract: A method for fabricating a quantum dot, which can be used to fabricate a single electron memory device. The method includes forming a first insulation layer on a semiconductor layer, then forming a second insulation layer on the first insulation layer. Next, the second insulation layer is patterned to form an opening to partially expose the upper surface of the first insulation layer. Using the opening in the second insulation layer, a silicon ion is then implanted into the first insulation layer through the opening by using a tilt angle ion implantation method. Finally, the semiconductor layer is treated to re-crystallize the silicon ion implanted into the first insulation layer.Type: GrantFiled: August 15, 2001Date of Patent: February 25, 2003Assignee: Hynix Semiconductor Inc.Inventor: Il-Gweon Kim
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Patent number: 6521967Abstract: A three-color QWIP focal plane array is based on a GaAs/AlGaAs material system. Three-color QWIPs enable target recognition and discriminating systems to precisely obtain the temperature of two objects in the presence of a third unknown parameter. The QWIPs are designed to reduce the normal reflection over a significant wavelength range. One aspect of the present invention involves two photon absorptions per transition in a double quantum well structure which is different from typical QWIP structures. This design is expected to significantly reduce the dark current as a result of higher thermionic barriers and therefore allow the devices to operate at elevated temperatures. The device is expected to be fabricate using a GaAs/AlxGa1−xAs material system on a semi-insulating GaAs substrate by Molecular Beam Epitacy (MBE).Type: GrantFiled: August 1, 2000Date of Patent: February 18, 2003Assignee: California Institute of TechnologyInventors: Sumith V. Bandara, John K. Liu, Daniel Wilson, Sarath D. Gunapala, William Parrish
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Patent number: 6518080Abstract: A method of fabricating low dark current photodiodes is provided. A multi-layer epitaxial structure is provided, wherein a contact epilayer forms the top-most layer of the structure. A diffusion mask is deposited on top of the contact layer, and at least one hole formed therein. Dopant is diffused through the hole and into both the contact epilayer and the underlying epitaxial structure, forming a doped region. A contact mask is then deposited, covering both the diffusion mask and the holes formed therein. The contact mask and contact epilayer are selectively etched, forming contact mesas and exposing portions of the underlying layers. A passivation coating, also serving as an anti-reflective coating and having uniform thickness, is deposited on top of the contact mesa and the exposed portions. Contacts and bond pads are then deposited, forming a complete photodiode.Type: GrantFiled: November 14, 2001Date of Patent: February 11, 2003Assignee: Sensors Unlimited, Inc.Inventors: Jonas Bentell, Michael Lange