Heterojunction Patents (Class 438/94)
  • Publication number: 20090224228
    Abstract: An improved photodiode and method of producing an improved photodiode comprising doping an InAs layer of an InAs/GaSb region situated on top of an InAs/GaSb:Be superlattice and below an InAs:Si/GaSb regions such that the quantum efficiency of the photodiode increases and dominant dark current mechanisms change from diffusion to band-to-band tunneling as the InAs layer is doped with Beryllium.
    Type: Application
    Filed: March 5, 2008
    Publication date: September 10, 2009
    Inventor: Manijeh Razeghi
  • Publication number: 20090211637
    Abstract: A photovoltaic cell can include a heterojunction between semiconductor layers.
    Type: Application
    Filed: September 24, 2008
    Publication date: August 27, 2009
    Applicant: First Solar, Inc.
    Inventor: David Eaglesham
  • Patent number: 7575946
    Abstract: In a method for making a compound semiconductor including a substrate and a compound semiconductor layer having a lattice mismatch ratio of 2% or more relative to the substrate, the method includes a first epitaxial growth step of forming a buffer layer on the substrate, the buffer layer having a predetermined distribution of lattice mismatch ratios in the thickness direction so as to reduce strain; and a second epitaxial growth step of forming the compound semiconductor layer on the buffer layer. The first epitaxial growth step is carried out by metal organic chemical vapor deposition at a deposition temperature of 600° C. or less.
    Type: Grant
    Filed: March 14, 2005
    Date of Patent: August 18, 2009
    Assignee: Sony Corporation
    Inventors: Yasuo Sato, Tomonori Hino, Hironobu Narui
  • Publication number: 20090194152
    Abstract: A thin-film solar cell having a hetero-junction of semiconductor and the fabrication method thereof are provided. Instead of the conventional hetero-junction of III-V semiconductor or homo-structure of IV semiconductor, the thin-film solar cell according to the present invention adopts a novel hetero-junction structure of IV semiconductor to improve the cell efficiency thereof. By adjusting the amount of layer sequences and the thickness of the hetero-junction structure, the cell efficiency of the thin-film solar cell according to the present invention is also optimized.
    Type: Application
    Filed: February 4, 2008
    Publication date: August 6, 2009
    Applicant: NATIONAL TAIWAN UNIVERSITY
    Inventors: Chee-Wee Liu, Cheng-Yeh Yu, Wen-Yuan Chen, Chu-Hsuan Lin
  • Patent number: 7553691
    Abstract: A method and a multijunction solar device having a high band gap heterojunction middle solar cell are disclosed. In one embodiment, a triple-junction solar device includes bottom, middle, and top cells. The bottom cell has a germanium (Ge) substrate and a buffer layer, wherein the buffer layer is disposed over the Ge substrate. The middle cell contains a heterojunction structure, which further includes an emitter layer and a base layer that are disposed over the bottom cell. The top cell contains an emitter layer and a base layer disposed over the middle cell.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: June 30, 2009
    Assignee: Emcore Solar Power, Inc.
    Inventors: Navid Fatemi, Daniel J. Aiken, Mark A. Stan
  • Patent number: 7553690
    Abstract: This disclosure is concerned with starved source diffusion methods for forming avalanche photodiodes are provided for controlling an edge effect. In one example, a method for manufacturing an avalanche photodiode includes forming an absorber layer and an avalanche layer over a substrate. Next, a patterned mask defining one or more openings is formed over a surface of the avalanche layer. Finally, a dopant is deposited over the patterned mask and the avalanche layer such that the dopant is blocked by the patterned mask but diffuses into the avalanche layer in areas where the patterned mask defines an opening. The patterned mask is configured such that the depth to which the dopant diffuses into the avalanche layer varies so as to form a sloped diffusion front in the avalanche layer.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: June 30, 2009
    Assignee: Finisar Corporation
    Inventors: Daniel Francis, Rashit Nabiev, Richard P. Ratowsky, David Bruce Young, Sunil Thomas, Roman Dimitrov
  • Publication number: 20090151782
    Abstract: Disclosed are a hetero-junction silicon solar cell and a fabrication method thereof. The hetero-junction silicon solar cell according to the present invention forms a pn junction of a crystalline silicon substrate and a passivation layer doped with impurities so as to minimize a recombination of electrons and holes, making it possible to maximize efficiency of the hetero-junction silicon solar cell. The present invention provides a hetero-junction silicon solar cell comprising a crystalline silicon substrate and a passivation layer that is formed on the crystalline silicon substrate and is doped with impurities.
    Type: Application
    Filed: December 15, 2008
    Publication date: June 18, 2009
    Applicant: LG ELECTRONICS INC.
    Inventors: Ji Hoon Ko, Young Joo Eo, Jin Ah Kim, Ju Hwan Yun, Il Hyoung Jung, Jong Hwan Kim
  • Publication number: 20090151788
    Abstract: A P-type doped layer of a photoelectric conversion device is provided. The P-type doped layer is a double layer structure including a seeding layer and a wide band gap layer disposed thereon. The P-type doped layer with the double layer structure has both high conductivity and high photoelectric performance.
    Type: Application
    Filed: February 5, 2008
    Publication date: June 18, 2009
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventor: Chih-Jeng Huang
  • Publication number: 20090155952
    Abstract: A method of forming a multifunction solar cell including an upper subcell, a middle subcell, and a lower subcell, including providing first substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a grading interlayer over the second subcell, the grading interlayer having a third band gap greater than the second band gap; and forming a third solar subcell over the grading interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell, wherein at least one of the bases of a solar subcell has an exponentially doped profile.
    Type: Application
    Filed: December 13, 2007
    Publication date: June 18, 2009
    Applicant: Emcore Corporation
    Inventors: Mark A. Stan, Arthur Cornfeld, Vance Ley
  • Patent number: 7544535
    Abstract: The method for manufacturing a semiconductor laser element according to the present invention has the steps of: forming a semiconductor laminated structure having an active layer composed of a semiconductor material containing Al; etching the semiconductor laminated structure to form a mesa; forming a first burying layer at a first growing temperature so as to coat the side of the mesa; and forming a second burying layer at a second growing temperature higher than the first growing temperature on the first burying layer to bury the circumference of the mesa.
    Type: Grant
    Filed: January 22, 2007
    Date of Patent: June 9, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventors: Chikara Watatani, Toru Ota, Takashi Nagira
  • Publication number: 20090140291
    Abstract: A photo-detector, in which metal wiring for connecting electrodes is arranged on a planarized surface and thus the metal wiring arrangement is simplified, and a method of manufacturing the same are provided. The photo-detector includes a multi-layer compound semiconductor layer formed on a compound semiconductor substrate. A number of p-n junction diodes are arranged in a regular order in a selected region of the compound semiconductor layer, and an isolation region for individually isolating the p-n junction diodes is formed by implanting impurity ions in the multi-layer compound semiconductor layer. The isolation region and the surface of the compound semiconductor layer are positioned on the same level. The isolation region may be a Fe-impurity region.
    Type: Application
    Filed: December 7, 2006
    Publication date: June 4, 2009
    Inventors: Eun Soo Nam, Seon Eui Hong, Myoung Sook Oh, Yong Won Kim, Ho Young Kim, Bo Woo Kim
  • Patent number: 7541208
    Abstract: Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be formed with little or no consumption of surface silicon. These oxides, such as screening oxide and pad oxide, are formed by deposition onto, rather than reaction with and consumption of the surface layer. Alternatively, oxide deposition is preceded by a thermal oxidation step of short duration, e.g., rapid thermal oxidation. Here, the short thermal oxidation consumes little surface Si, and the Si/oxide interface is of high quality. The oxide may then be thickened to a desired final thickness by deposition. Furthermore, the thin thermal oxide may act as a barrier layer to prevent contamination associated with subsequent oxide deposition.
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: June 2, 2009
    Assignee: AmberWave Systems Corporation
    Inventors: Matthew T. Currie, Anthony J. Lochtefeld
  • Publication number: 20090130796
    Abstract: The invention relates to a method for production of thin layers of semiconductor alloys of the I-III-VI2 type, including sulphur, for photovoltaic applications, whereby a heterostructure is firstly deposited on a substrate comprising a thin layer of precursor I-III-VI2 which is essentially amorphous and a thin layer, including at least some sulphur, the heterostructure is then annealed to promote the diffusion of the sulphur into the precursor layer and the at least partial crystallization of the I-III-VI2 alloy of the precursor layer with a stoichiometry which hence includes sulphur. A layer of selenium may also be deposited to assist the recrystallization processes or annealing.
    Type: Application
    Filed: May 19, 2006
    Publication date: May 21, 2009
    Applicants: ELECTRICITE DE FRANCE, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE-CNRS
    Inventors: Stephane Taunier, Daniel Lincot, Jean-Francois Guillemoles, Negar Naghavi, Denis Guimard
  • Patent number: 7528002
    Abstract: A method for forming a nanowhisker of, e.g., a III-V semiconductor material on a silicon substrate, comprises: preparing a surface of the silicon substrate with measures including passivating the substrate surface by HF etching, so that the substrate surface is essentially atomically flat. Catalytic particles on the substrate surface are deposited from an aerosol; the substrate is annealed; and gases for a MOVPE process are introduced into the atmosphere surrounding the substrate, so that nanowhiskers are grown by the VLS mechanism. In the grown nanowhisker, the crystal directions of the substrate are transferred to the epitaxial crystal planes at the base of the nanowhisker and adjacent the substrate surface.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: May 5, 2009
    Assignee: QuNano AB
    Inventors: Lars Ivar Samuelson, Thomas M. I. Martensson
  • Publication number: 20090095349
    Abstract: A device comprises a plurality of fence layers of a semiconductor material and a plurality of alternating layers of quantum dots of a second semiconductor material embedded between and in direct contact with a third semiconductor material disposed in a stack between a p-type and n-type semiconductor material. Each quantum dot of the second semiconductor material and the third semiconductor material form a heterojunction having a type II band alignment. A method for fabricating such a device is also provided.
    Type: Application
    Filed: October 10, 2007
    Publication date: April 16, 2009
    Inventors: Stephen R. Forrest, Guodan Wei, Kuen-Ting Shiu
  • Publication number: 20090087941
    Abstract: There is provided a method for producing a multijunction solar cell having four-junctions, the method allowing the area of a device to be increased. On a nucleation site formed on a substrate 2, is grown a semiconductor 2a comprising the same material as the substrate 2 in the shape of a wire. On the semiconductor 2a, are successively grown semiconductors 3, 4, 5, and 6 with a narrower band gap in the shape of a wire. The semiconductor 3 may be directly grown in the shape of a wire on the nucleation site formed on the substrate 2. It is preferred to form the nucleation site by forming an amorphous SiO2 coating 8a on the substrate 2 and etching a part of the amorphous SiO2 coating 8a. Further, it is preferred to form an insulating film 8 in the region except the nucleation sites on the substrate 2 by allowing the amorphous SiO2 coating 8a to remain therein. The semiconductor 2a is GaP; the semiconductor 3 is Al0.3Ga0.7As; the semiconductor 4 is GaAs; the semiconductor 5 is In0.3Ga0.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 2, 2009
    Inventors: Hajime Goto, Junichi Motohisa, Takashi Fukui
  • Publication number: 20090087940
    Abstract: A high-resistance buffer layer and a window layer (transparent conductive film) are successively formed by the MOCVD method to obtain the same output characteristics as in conventional film deposition by the solution deposition method and to simplify a film deposition method and apparatus. Thus, the cost of raw materials and the cost of waste treatments are reduced to attain a considerable reduction in production cost. After a metallic base electrode layer 1B and a light absorption layer 1C are formed in this order on a glass substrate 1A, a high-resistance buffer layer 1D and a window layer 1E are successively formed in this order in a multi layer arrangement on the light absorption layer 1C of the resultant semifinished solar cell substrate by the MOCVD method. Consequently, a film deposition method and apparatus are simplified and the cost of raw materials and the cost of waste treatments can be reduced.
    Type: Application
    Filed: May 24, 2006
    Publication date: April 2, 2009
    Applicant: SHOWA SHELL SEKIYU K.K.
    Inventor: Katsumi Kushiya
  • Patent number: 7510904
    Abstract: The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer.
    Type: Grant
    Filed: November 6, 2006
    Date of Patent: March 31, 2009
    Assignee: International Business Machines Corporation
    Inventors: Jack O. Chu, Gabriel K. Dehlinger, Alfred Grill, Steven J. Koester, Qiqing Ouyang, Jeremy D. Schaub
  • Publication number: 20090078310
    Abstract: An inverted metamorphic multifunction solar cell, and its method of fabrication, including an upper subcell, a middle subcell, and a lower subcell, including providing a first substrate for the epitaxial growth of semiconductor material; forming an upper first solar subcell on the substrate having a first bandgap; forming a middle second solar subcell over the first solar subcell having a second bandgap smaller than the first bandgap; forming a graded interlayer over the second subcell, the graded interlayer having a third bandgap greater than the second bandgap; and forming a lower third solar subcell over the graded interlayer having a fourth bandgap smaller than the second bandgap such that the third subcell is lattice mismatched with respect to the second subcell, wherein at least one of the solar subcells has heterojunction base-emitter layers.
    Type: Application
    Filed: January 31, 2008
    Publication date: March 26, 2009
    Applicant: Emcore Corporation
    Inventors: Mark A. Stan, Arthur Cornfeld
  • Publication number: 20090061557
    Abstract: A silicon layer having a conductivity type opposite to that of a bulk is provided on the surface of a silicon substrate and hydrogen ions are implanted to a predetermined depth into the surface region of the silicon substrate through the silicon layer to form a hydrogen ion-implanted layer. Then, an n-type germanium-based crystal layer whose conductivity type is opposite to that of the silicon layer and a p-type germanium-based crystal layer whose conductivity type is opposite to that of the germanium-based crystal layer are successively vapor-phase grown to provide a germanium-based crystal. The surface of the germanium-based crystal layer and the surface of the supporting substrate are bonded together. In this state, impact is applied externally to separate a silicon crystal from the silicon substrate along the hydrogen ion-implanted layer, thereby transferring a laminated structure composed of the germanium-based crystal and the silicon crystal onto the supporting substrate.
    Type: Application
    Filed: March 12, 2007
    Publication date: March 5, 2009
    Applicant: Shin-Etsu Chemical Co., Ltd
    Inventors: Shoji Akiyama, Yoshihiro Kubota, Atsuo Ito, Makoto Kawai, Yuuji Tobisaka, Koichi Tanaka
  • Publication number: 20090045394
    Abstract: A method of manufacturing a semiconductor device comprises depositing a semiconductor layer over a semiconductor surface having at least one first region with a first (average surface lattice) parameter value and at least one second region having a second parameter value different from the first. The semiconductor layer is deposited to a thickness so self-organised islands form over both the first and second regions. The difference in the parameter value means the islands over the first region have a first average parameter value and the islands over the second region have a second average parameter value different from the first. A capping layer is deposited over islands and has a greater forbidden bandgap than the islands whereby the islands form quantum dots, which have different properties over the first and second regions due to difference(s) between the first and second region islands.
    Type: Application
    Filed: August 12, 2008
    Publication date: February 19, 2009
    Inventors: Tim Michael Smeeton, Katherine Louise Smith, Mathieu Xavier Senes, Stewart Edward Hooper
  • Publication number: 20090039340
    Abstract: Method and apparatus for acquiring physical information, method for manufacturing semiconductor device including array of a plurality of unit components for detecting physical quantity distribution, light-receiving device and manufacturing method therefor, and solid-state imaging device and manufacturing method therefore are provided. The method for acquiring physical information uses a device for detecting a physical distribution, the device including a detecting part for detecting an electromagnetic wave and a unit signal generating part for generating a corresponding unit signal on the basis of the quantity of the detected electromagnetic wave.
    Type: Application
    Filed: August 28, 2008
    Publication date: February 12, 2009
    Applicant: SONY CORPORATION
    Inventor: Atsushi Toda
  • Publication number: 20090039361
    Abstract: A method of forming a semiconductor structure includes forming an opening in a dielectric layer, forming a recess in an exposed part of a substrate, and forming a lattice-mismatched crystalline semiconductor material in the recess and opening.
    Type: Application
    Filed: July 25, 2008
    Publication date: February 12, 2009
    Applicant: Amberwave Systems Corporation
    Inventors: Jizhong Li, Anthony J. Lochtefeld
  • Publication number: 20090001412
    Abstract: The invention offers a photodetector that has an N-containing InGaAs-based absorption layer having a sensitivity in the near-infrared region and that suppresses the dark current and a production method thereof. The photodetector is provided with an InP substrate 1, an N-containing InGaAs-based absorption layer 3 positioned above the InP substrate 1, a window layer 5 positioned above the N-containing InGaAs-based absorption layer 3, and an InGaAs buffer layer 4 positioned between the N-containing InGaAs-based absorption layer 3 and the window layer 5.
    Type: Application
    Filed: June 27, 2008
    Publication date: January 1, 2009
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Youichi Nagai, Yasuhiro Iguchi, Kouhei Miura
  • Publication number: 20080315252
    Abstract: An image sensor provides enhanced integration of transistor circuitry and photo diodes. The image sensor simultaneously improves resolution and sensitivity. An image sensor an a method for manufacturing prevents defects in a photo diode by adopting a vertical photo diode structure. An image sensor includes a substrate which may include at least one circuit element. A bottom electrode and a first conductive layer may be sequentially formed over the substrate. A strained intrinsic layer may be formed over the first conductive layer. A second conductive layer may be formed over the strained intrinsic layer. An upper electrode may be formed over the second conductive layer.
    Type: Application
    Filed: December 31, 2007
    Publication date: December 25, 2008
    Inventor: Cheon Man Shim
  • Patent number: 7468287
    Abstract: Provided is a method of forming a heterojunction of contiguous layers of organic semiconducting polymers. The method comprises firstly forming a layer of a first organic semiconducting polymer on a substrate. A solution of a film-forming material is then deposited on the layer of the first organic semiconducting polymer. The first organic semiconducting polymer is insoluble in this solution and so is not disturbed by its deposition. The deposited solution is then dried to form a temporary film having a thickness of less then 20 nm formed from the film-forming material. Next a solution of a second organic semiconducting polymer dissolved in an organic solvent is deposited on the temporary film and this solution dried. The solubility of the material forming the temporary film in the organic solvent and the thickness of the temporary film are such that the organic solvent permeates through the thickness of the temporary film during drying of the solution of the second organic semiconducting polymer.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: December 23, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Christopher Newsome, Thomas Kugler, Shunpu Li, David Russell
  • Publication number: 20080264479
    Abstract: Embodiments of the present invention involve photovoltaic (PV) cells comprising a semiconducting nanorod-nanocrystal-polymer hybrid layer, as well as methods for fabricating the same. In PV cells according to this invention, the nanocrystals may serve both as the light-absorbing material and as the heterojunctions at which excited electron-hole pairs split.
    Type: Application
    Filed: April 24, 2008
    Publication date: October 30, 2008
    Inventors: James Harris, Nigel Pickett
  • Publication number: 20080223440
    Abstract: Embodiments of the present invention generally relate to solar cells and methods and apparatuses for forming the same. More particularly, embodiments of the present invention relate to thin film multi-junction solar cells and methods and apparatuses for forming the same.
    Type: Application
    Filed: April 25, 2008
    Publication date: September 18, 2008
    Inventors: SHURAN SHENG, Yong-Kee Chae, Soo Young Choi
  • Publication number: 20080216893
    Abstract: A process for making a photovoltaic cell comprising forming a first layer on a front surface of a semiconductor wafer, the wafer comprising a first dopant and the first layer comprising a dopant of a conductivity type opposite the first dopant; depositing a surface coating on the front surface over the first layer; forming grooves in the front surface after depositing the surface coating thereon; doping the grooves with a dopant having a conductivity opposite the first dopant; treating a back surface of the wafer to remove at least substantially all dopant having a conductivity type opposite the first dopant; forming a back surface field; forming a back electrical contact over the back surface; and adding an electrically conductive material to the grooves to form a front electrical contact.
    Type: Application
    Filed: December 4, 2007
    Publication date: September 11, 2008
    Applicant: BP Solar Espana, S.A. Unipersonal
    Inventors: Richard W.J. Russell, Ines Vincuenia, Rafael M. Bueno, Juan M. Fernandez, Srinivasamohan Narayanan
  • Publication number: 20080210304
    Abstract: The invention relates to a photovoltaic cell comprising a photovoltaically active semiconductor material, wherein the photovoltaically active semiconductor material is a material of the formula (I), of the formula (II) or of a combination thereof: (Zn1-xMgxTe)1-y(MnTem)y and ??(I) (ZnTe)1-y(MeaMb)y, where ??(II) MnTem and MeaMb are each a dopant in which M is at least one element selected from the group consisting of Si, Ge, Sn. Pb, Sb and Bi and Me is at least one element selected from the group consisting of mg and Zn, and x=0 to 0.5 y=0.0001 to 0.05 n=1 to 2 m=0.5 to 4 a=1 to 5 and b=1 to 3.
    Type: Application
    Filed: September 29, 2006
    Publication date: September 4, 2008
    Applicant: BASF SE
    Inventor: Hans-Josef Sterzel
  • Patent number: 7420207
    Abstract: A photo-detecting device includes a buried doping layer of a first conductivity type and disposed at an upper portion of a silicon substrate. A first silicon epitaxial layer of first conductivity type is disposed on the buried doping layer, and a second silicon epitaxial layer of second conductivity type is disposed on the first silicon epitaxial layer. An isolation doping layer doped of first conductivity type is disposed at a predetermined region of the second silicon epitaxial layer to define a body region of second conductivity type. A silicon germanium epitaxial layer of second conductivity type is disposed on the body region.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: September 2, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Jin Kim, Kwang-Joon Yoon, Phil-Jae Chang, Kye-Won Maeng, Young-Jun Park
  • Publication number: 20080203425
    Abstract: A phototransistor (400) comprises an emitter (43) comprising antimony, a base (42) comprising antimony, and a collector (41) comprising antimony. Preferably, the emitter, the base and the collector each comprises at least one of AlInGaAsSb, AlGaAsSb, AlGaSb, GaSb and InGaAsSb. The base comprises an emitter-contacting portion (41b) with a base-contacting portion (43a) of the emitter. The collector comprises a base-contacting portion (41b) which is in contact with a collector-contacting portion (421a) of the base. The phototransistor produces an internal gain upon being contacted with light within a receivable wavelength range, preferably greater than 1.7 micrometers. Also, a method of detecting light using such a phototransistor.
    Type: Application
    Filed: January 24, 2005
    Publication date: August 28, 2008
    Inventor: Oleg Sulima
  • Patent number: 7416909
    Abstract: Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be formed with little or no consumption of surface silicon. These oxides, such as screening oxide and pad oxide, are formed by deposition onto, rather than reaction with and consumption of the surface layer. Alternatively, oxide deposition is preceded by a thermal oxidation step of short duration, e.g., rapid thermal oxidation. Here, the short thermal oxidation consumes little surface Si, and the Si/oxide interface is of high quality. The oxide may then be thickened to a desired final thickness by deposition. Furthermore, the thin thermal oxide may act as a barrier layer to prevent contamination associated with subsequent oxide deposition.
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: August 26, 2008
    Assignee: AmberWave Systems Corporation
    Inventors: Matthew T. Currie, Anthony J. Lochtefeld
  • Publication number: 20080185038
    Abstract: A method of forming a multijunction solar cell comprising an upper subcell, a middle subcell, and a lower subcell by providing a first substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on said substrate having a first band gap; forming a second solar subcell over said first subcell having a second band gap smaller than said first band gap; forming a grading interlayer over said second subcell having a third band gap larger than said second band gap; forming a third solar subcell having a fourth band gap smaller than said second band gap such that said third subcell is lattice mismatched with respect to said second subcell; and etching a via from the top of the third subcell to the substrate to enable both anode and cathode contacts to be placed on the backside of the solar cell.
    Type: Application
    Filed: February 2, 2007
    Publication date: August 7, 2008
    Inventor: Paul R. Sharps
  • Patent number: 7407831
    Abstract: A method for the production of organic solar cells or photodetectors, particularly based on organic polymers, comprising the following steps:—a first organic n- or p-conductive semiconductor layer is applied to an electrode, to the solid first organic semiconductor layer is applied a second organic semiconductor layer of the respective other conductivity whose solvent partially dissolves the first organic semiconductor layer, such that the first semiconductor layer mixes with the second mixed layer;—a second electrode is applied opposite the first.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: August 5, 2008
    Assignee: Konarka Technologies, Inc.
    Inventors: Christoph Brabec, Schilinsky Pavel
  • Patent number: 7345297
    Abstract: A semiconductor device includes an active layer, an n-side contact layer, and a p-side contact layer. The nitride semiconductor device includes at least a first n-side layer, a second n-side layer, a third n-side layer and a fourth n-side layer formed in this order from the n-side contact layer between the n-side contact layer and the active layer, while at least the second n-side layer and the fourth n-side layer each contain an n-type impurity, and the concentration of the n-type impurity in at least the second n-side layer and the fourth n-side layer is higher than the concentration of the n-type impurity in the first n-side layer and the third n-side layer.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: March 18, 2008
    Assignee: Nichia Corporation
    Inventors: Masahito Yamazoe, Masayuki Eguchi, Hiroki Narimatsu, Kazunori Sasakura, Yukio Narukawa
  • Patent number: 7338826
    Abstract: This invention pertains to an electronic device and to a method for making it. The device is a heterojunction transistor, particularly a high electron mobility transistor, characterized by presence of a 2 DEG channel. Transistors of this invention contain an AlGaN barrier and a GaN buffer, with the channel disposed, when present, at the interface of the barrier and the buffer. Surface treated with ammonia plasma resembles untreated surface. The method pertains to treatment of the device with ammonia plasma prior to passivation to extend reliability of the device beyond a period of time on the order of 300 hours of operation, the device typically being a 2 DEG AlGaN/GaN high electron mobility transistor with essentially no gate lag and with essentially no rf power output degradation.
    Type: Grant
    Filed: December 9, 2005
    Date of Patent: March 4, 2008
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Jeffrey A. Mittereder, Andrew P. Edwards, Steven C. Binari
  • Publication number: 20080012005
    Abstract: An optoelectronic device and a method of fabricating a photosensitive optoelectronic device includes depositing a first organic semiconductor material on a first electrode to form a continuous first layer having protrusions, a side of the first layer opposite the first electrode having a surface area at least three times greater than an underlying lateral cross-sectional area; depositing a second organic semiconductor material directly on the first layer to form a discontinuous second layer, portions of the first layer remaining exposed; depositing a third organic semiconductor material directly on the second layer to form a discontinuous third layer, portions of at least the second layer remaining exposed; depositing a fourth organic semiconductor material on the third layer to form a continuous fourth layer, filling any exposed gaps and recesses in the first, second, and third layers; and depositing a second electrode on the fourth layer, wherein at least one of the first electrode and the second electrode
    Type: Application
    Filed: July 11, 2006
    Publication date: January 17, 2008
    Inventors: Fan Yang, Stephen R. Forrest
  • Patent number: 7297589
    Abstract: A method for making a heterojunction bipolar transistor includes the following steps: forming a heterojunction bipolar transistor by depositing, on a substrate, subcollector, collector, base, and emitter regions of semiconductor material; the step of depositing the subcollector region including depositing a material composition transition from a relatively larger bandgap material nearer the substrate to a relatively smaller bandgap material adjacent the collector; and the step of depositing the collector region including depositing a material composition transition from a relatively smaller bandgap material adjacent the subcollector to a relatively larger bandgap material adjacent the base.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: November 20, 2007
    Assignee: The Board of Trustees of The University of Illinois
    Inventor: Milton Feng
  • Patent number: 7288430
    Abstract: An efficient method of fabricating a high-quality heteroepitaxial microstructure having a smooth surface. The method includes detaching a layer from a base structure to provide a carrier substrate having a detached surface, and then forming a heteroepitaxial microstructure on the detached surface of the carrier substrate by depositing an epitaxial layer on the detached surface of a carrier substrate. Also included is a heteroepitaxial microstructure fabricated from such method.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: October 30, 2007
    Assignee: S.O.I.Tec Silicon on Insulator Technolgoies
    Inventors: Bruce Faure, Fabrice Letertre, Bruno Ghyselen
  • Patent number: 7279698
    Abstract: The optical modulator may include a strained layer of SiGe to confine carriers in a quantum well. The strained layer of SiGe may be doped with arsenic to provide electrons. The optical modulator may receive an optical signal and modulate the received signal by altering the absorption coefficient of the strained layer of SiGe responsive to an electrical signal. The optical modulator device device may be suitable for use in chip-to-chip and on-chip interconnections.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: October 9, 2007
    Assignee: Intel Corporation
    Inventor: Donald S. Gardner
  • Patent number: 7250320
    Abstract: A semiconductor light emitting element, manufacturing method thereof, integrated semiconductor light emitting device, manufacturing method thereof, illuminating device, and manufacturing method thereof are provided. An n-type GaN layer is grown on a sapphire substrate, and a growth mask of SiN, for example, is formed thereon. On the n-type GaN layer exposed through an opening in the growth mask, a six-sided steeple-shaped n-type GaN layer is selectively grown, which has inclined crystal planes each composed of a plurality of crystal planes inclined from the major surface of the sapphire substrate by different angles of inclination to exhibit a convex plane as a whole. On the n-type GaN layer, an active layer and a p-type GaN layer are grown to make a light emitting element structure. Thereafter, a p-side electrode and an n-side electrode are formed.
    Type: Grant
    Filed: February 19, 2004
    Date of Patent: July 31, 2007
    Assignee: Sony Corporation
    Inventors: Hiroyuki Okuyama, Masato Doi, Goshi Biwa, Jun Suzuki, Toyoharu Oohata
  • Patent number: 7244630
    Abstract: To increase the lattice constant of AlInGaP LED layers to greater than the lattice constant of GaAs for reduced temperature sensitivity, an engineered growth layer is formed over a substrate, where the growth layer has a lattice constant equal to or approximately equal to that of the desired AlInGaP layers. In one embodiment, a graded InGaAs or InGaP layer is grown over a GaAs substrate. The amount of indium is increased during growth of the layer such that the final lattice constant is equal to that of the desired AlInGaP active layer. In another embodiment, a very thin InGaP, InGaAs, or AlInGaP layer is grown on a GaAs substrate, where the InGaP, InGaAs, or AlInGaP layer is strained (compressed). The InGaP, InGaAs, or AlInGaP thin layer is then delaminated from the GaAs and relaxed, causing the lattice constant of the thin layer to increase to the lattice constant of the desired overlying AlInGaP LED layers. The LED layers are then grown over the thin InGaP, InGaAs, or AlInGaP layer.
    Type: Grant
    Filed: April 5, 2005
    Date of Patent: July 17, 2007
    Assignee: Philips Lumileds Lighting Company, LLC
    Inventors: Michael R. Krames, Nathan F. Gardner, Frank M. Steranka
  • Patent number: 7179677
    Abstract: A process for making a thin film ZnO/Cu(InGa)Se2 solar cell without depositing a buffer layer and by Zn doping from a vapor phase, comprising: depositing Cu(InGa)Se2 layer on a metal back contact deposited on a glass substrate; heating the Cu(InGa)Se2 layer on the metal back contact on the glass substrate to a temperature range between about 100° C. to about 250° C.; subjecting the heated layer of Cu(InGa)Se2 to an evaporant species from a Zn compound; and sputter depositing ZnO on the Zn compound evaporant species treated layer of Cu(InGa)Se2.
    Type: Grant
    Filed: September 3, 2003
    Date of Patent: February 20, 2007
    Assignee: Midwest Research Institute
    Inventors: Kannan Ramanathan, Falah S. Hasoon, Sarah E. Asher, James Dolan, James C. Keane
  • Patent number: 7141449
    Abstract: A method of fabricating a thin-film compound solar cell having an n-type buffer layer formed therein for providing a heterojunction with a p-type compound semiconductor light absorbing layer formed on a back electrode by spreading a powder of a sulfur compound containing n-type doping element over the light absorbing layer surface or applying a coat of a solution of a sulfur compound containing n-type doping element onto the light absorbing layer surface and then fusing the powder or the coat thereon by heat. This process can produce a high-quality n-type buffer layer tightly adhered to a p-type compound semiconductor light absorbing layer to achieve stable characteristic of heterojunction therewith.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: November 28, 2006
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventor: Satoshi Shiozaki
  • Patent number: 7053294
    Abstract: A thin-film solar cell (10) is provided. The thin-film solar cell (10) comprises a flexible metallic substrate (12) having a first surface and a second surface. A back metal contact layer (16) is deposited on the first surface of the flexible metallic substrate (12). A semiconductor absorber layer (14) is deposited on the back metal contact. A photoactive film deposited on the semiconductor absorber layer (14) forms a heterojunction structure and a grid contact (24) deposited on the heterjunction structure. The flexible metal substrate (12) can be constructed of either aluminium or stainless steel. Furthermore, a method of constructing a solar cell is provided. The method comprises providing an aluminum substrate (12), depositing a semiconductor absorber layer (14) on the aluminum substrate (12), and insulating the aluminum substrate (12) from the semiconductor absorber layer (14) to inhibit reaction between the aluminum substrate (12) and the semiconductor absorber layer (14).
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: May 30, 2006
    Assignee: Midwest Research Institute
    Inventors: John R. Tuttle, Rommel Noufi, Falah S. Hasoon
  • Patent number: 7053417
    Abstract: The present invention provides a semiconductor device with InxGa1-xN crystal passivation layer and manufacturing method thereof which effectively blocks the leakage current between the surface & boundary of a device and a pn-junction boundary, and enhances the light emission efficiency as forming new structural semiconductor devices by removing the conventional dielectric passivation layer and using InxGa1-xN crystal layer instead. A semiconductor device with gallium nitride type crystal passivation layer, wherein said semiconductor device has a p-n junction diode construction and forms a InxGa1-xN crystal passivation layer with a specified thickness and a width around the edge of the upper surface of p-GaN layer which is the top layer of the semiconductor device.
    Type: Grant
    Filed: September 4, 2001
    Date of Patent: May 30, 2006
    Assignees: Epivalley Co., Ltd., Samsung Electro-Mechanics Co., Ltd.
    Inventor: Chang-Tae Kim
  • Patent number: 7045378
    Abstract: A photosensitive diode has superlattice exclusion region formed from a stack of first and second layers. The first layers are penetrated by minority carriers using quantum mechanical tunneling and reduce minority carrier mobility. The second layers have a sufficiently low bandgap that the tunneling minority carriers can reach an active region of the diode. The process of successively forming first and second layers is repeated until the exclusion region is at least three times the minority carrier diffusion length.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: May 16, 2006
    Assignee: EPIR Technologies, Inc.
    Inventors: Christoph H. Grein, Silviu Velicu, Sivalingam Sivananthan
  • Patent number: 7029940
    Abstract: Ammonia for use in the manufacture of a GaN-type compound semiconductor, filled in a charging container 18 such that at least a part of the ammonia is liquid and the liquid phase ammonia has a water concentration determined by a Fourier-transform infrared spectroscopy (FT-IR) of 0.5 vol ppm or less, is introduced in the gaseous state into a reaction chamber 11 housing therein a substrate 1, and a layer comprising a GaN-type compound started from this ammonia is formed on the substrate 1.
    Type: Grant
    Filed: April 12, 2004
    Date of Patent: April 18, 2006
    Assignee: Showa Denko Kabushiki Kaisha
    Inventors: Hideki Hayashida, Taizo Ito, Yasuyuki Sakaguchi
  • Patent number: 7026228
    Abstract: The invention relates to a method of depositing Hg1-xCdxTe onto a substrate, in a MOVPE technique, where 0?x?1; comprising the step of reacting together a volatile organotellurium compound, and one or both of (i) a volatile organocadmium compound and (ii) mercury vapour; characterised in that the organotellurium compound is isopropylallyltelluride. The invention also relates to devices, such as infrared sensors and solar cells, that comprise Hg1-xCdxTe materials.
    Type: Grant
    Filed: August 22, 2000
    Date of Patent: April 11, 2006
    Assignee: QinetiQ Limited
    Inventors: Janet E. Hails, Saamara N. Turney, legal representative, David J. Cole-Hamilton, William Bell, Douglas F. Foster, John Stevenson, deceased