Abstract: A bulk heterojunction comprising an intermixed blend of fully inorganic n- and p-type particles and its method of manufacture are described. The particles are preferably nanometer-scale, spherical-shaped particles known as nanocrystals which are assembled into a densely packed three-dimensional array. The nanocrystals are preferably fabricated from a photo-active material which, in combination with the nanocrystal shape and size, can be engineered to produce a bulk heterojunction with a specific absorption spectrum. The bulk heterojunction is preferably formed by dispersing a predetermined ratio of the desired n- and p-type nanocrystals in an organic solvent and employing low-cost solution processing techniques to deposit a film having the desired thickness, relative concentration of nanocrystal types, and degree of intermixing onto a substrate.

Abstract: The present invention provides a method of manufacturing a solar cell, comprising forming a buffer layer comprising a group-III nitride semiconductor on a substrate using a sputtering method, and forming a group-III nitride semiconductor layer and electrodes on the buffer layer. The group-III nitride semiconductor layer is formed on the buffer layer by at least one selected from the group consisting of the sputtering method, a MOCVD method, an MBE method, a CBE method, and an MLE method, and the electrodes are formed on the group-III nitride semiconductor layer.

Abstract: High frequency performance of (e.g., silicon) bipolar devices (100, 100?) is improved by reducing the extrinsic base resistance Rbx. Emitter (160), base (161) and collector (190) are formed in or on a semiconductor substrate (110). The emitter contact (154) has a portion (154?) that overhangs a portion (1293, 293?) of the extrinsic base contact (129), thereby forming a cave-like cavity (181, 181?) between the overhanging portion (154?) of the emitter contact (154) and the underlying regions (1293, 1293?) of the extrinsic base contact (129). When the emitter contact and the extrinsic base contact are silicided, some of the metal atoms forming the silicide penetrate into the cavity (181, 181?) so that the highly conductive silicided extrinsic base contact extends under the edge of the emitter contact (154?) closer to the base (161, 163) itself, thereby reducing Rbx. Smaller Rbx provides transistors with higher fMAX.

Abstract: A method of manufacturing a solar cell comprising providing a growth substrate; depositing on said growth substrate a sequence of layers of semiconductor material forming a solar cell; applying a coating layer over said sequence of layers; and removing the semiconductor substrate.

Abstract: A solar cell is provided as one capable of increasing the open voltage when compared with the conventional solar cells. A solar cell according to the present invention has a p-type semiconductor layer containing a group Ib element, a group IIIb element, and a group VIb element, and an n-type semiconductor layer containing a group Ib element, a group IIIb element, a group VIb element, and Zn and formed on the p-type semiconductor layer. A content of the group Ib element in the n-type semiconductor layer is from 15 to 21 at. % to the total number of atoms of the group Ib element, the group IIIb element, the group VIb element, and Zn in the n-type semiconductor layer, and a content of Zn in the n-type semiconductor layer is from 0.005 to 1.0 at. % to the total number of atoms of the group Ib element, the group IIIb element, the group VIb element, and Zn in the n-type semiconductor layer.

Abstract: The invention relates to a photo-detector with a reduced G-R noise, which comprises a sequence of a p-type contact layer, a middle barrier layer and an n-type photon absorbing layer, wherein the middle barrier layer has an energy bandgap significantly greater than that of the photon absorbing layer, and there is no layer with a narrower energy bandgap than that in the photon-absorbing layer.

Abstract: A method is disclosed for preparing a surface of a Group III-Group V compound semiconductor for epitaxial deposition. The III-V semiconductor surface is treated with boron (B) at a temperature of between about 250° C. and about 350° C. A suitable form for supplying B for the surface treatment is diborane. The B treatment can be followed by epitaxial growth, for instance by a Group IV semiconductor, at temperatures similar to those of the B treatment. The method yields high quality heterojunction, suitable for fabricating a large variety of device structures.

Abstract: A device grade III-V quantum well structure and method of manufacture is described. Embodiments of the present invention enable III-V InSb quantum well device layers with defect densities below 1×108cm?2 to be formed. In an embodiment of the present invention, a delta doped layer is disposed on a dopant segregation barrier in order to confine delta dopant within the delta doped layer and suppress delta dopant surface segregation.

Abstract: Systems and methods for at or near room temperature of infrared detection are disclosed. Embodiments of the disclosure include high temperature split-off band infrared detectors. One embodiment, among others, comprises a first barrier and a second barrier with an emitter disposed between the first and second barrier, each barrier being a layer of a first semiconductor material and the emitter being a layer of a second semiconductor material.

Abstract: Methods and structures are provided for formation of devices, e.g., solar cells, on substrates including, e.g., lattice-mismatched materials, by the use of aspect ratio trapping (ART) and epitaxial layer overgrowth (ELO). In general, in a first aspect, embodiments of the invention may include a method of forming a structure. The method includes forming a first opening in a masking layer disposed over a substrate that includes a first semiconductor material. A first layer, which includes a second semi-conductor material lattice-mismatched to the first semiconductor material, is formed within the first opening. The first layer has a thickness sufficient to extend above a top surface of the masking layer. A second layer, which includes the second semiconductor material, is formed on the first layer and over at least a portion of the masking layer.

Abstract: A photovoltaic cell can include a substrate having a transparent conductive oxide layer, a heterojunction layer, and a cadmium telluride layer. The layers can be deposited by sputtering or by chemical vapor deposition.

Abstract: This disclosure describes devices and methods in which photovoltaic cells are configured such that an active layer of a photovoltaic cell is protected against an environmental condition by another active cell layer that is more robust against the environmental condition. In one aspect, the disclosure describes a multi-junction photovoltaic device that includes (a) an upper photovoltaic cell portion that has a first plurality of active layers of films, at least a subset of which form an upper photovoltaic sub-cell and (b) a lower photovoltaic cell portion disposed below the upper photovoltaic cell portion that has a second plurality of layers of films, at least a subset of which form a lower photovoltaic sub-cell. The first plurality of active layers, of the upper cell portion, include at least two layers of films having different degrees of robustness from each other against environmental conditions, such as exposure to water or oxygen.

Abstract: A continuous deposition process and apparatus for depositing semiconductor layers containing cadmium, tellurium or sulfur as a principal constituent on transparent substrates to form photovoltaic devices as the substrates are continuously conveyed through the deposition apparatus is described. The film deposition process for a photovoltaic device having an n-type window layer and three p-type absorber layers in contiguous contact is carried out by a modular continuous deposition apparatus which has a plurality of processing stations connected in series for depositing successive layers of semiconductor films onto continuously conveying substrates. The fabrication starts by providing an optically transparent substrate coated with a transparent conductive oxide layer, onto which an n-type window layer formed of CdS or CdZnS is sputter deposited. After the window layer is deposited, a first absorber layer is deposited thereon by sputter deposition.

Abstract: A two-terminal mesa phototransistor and a method for making it are disclosed. The photo transistor has a mesa structure having a substantially planar semiconductor surface. In the mesa structure is a first semiconductor region of a first doping type, and a second semiconductor region of a second doping type opposite to that of the first semiconductor region, forming a first semiconductor junction with the first region. In addition, a third semiconductor region of the first doping type forms a second semiconductor junction with the second region. The structure also includes a dielectric layer. The second semiconductor region, first semiconductor junction, and second semiconductor junction each has an intersection with the substantially planar semiconductor surface. The dielectric covers, and is in physical contact with, all of the intersections.

Abstract: A photonic device comprises a substrate and a dielectric material including two or more openings that expose a portion of the substrate, the two or more openings each having an aspect ratio of at least 1. A bottom diode material comprising a compound semiconductor material that is lattice mismatched to the substrate occupies the two or more openings and is coalesced above the two or more openings to form the bottom diode region. The device further includes a top diode material and an active diode region between the top and bottom diode materials.

Abstract: In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.

Abstract: A group III-V compound semiconductor comprising a single quantum well structure which has two barrier layers and a quantum well layer represented by the formula: InxGayAlzN (wherein x+y+z=1, 0<x<1, 0<y<1, and 0?z<1) between the barrier layers, wherein a multiple quantum well structure having repeatedly the barrier layers and the quantum well layer is formed, a ratio of an average mole fraction of InN in the multiple quantum well layer, which is measured by x-ray diffraction, to a mole fraction of InN calculated from a wavelength of light emitted from the group III-V compound semiconductor due to current injection is not more than 42.5%.

Abstract: Embodiments of the invention pertain to the use of alloyed semiconductor nanocrystals for use in solar cells. The use of alloyed semiconductor nanocrystals offers materials that have a flexible stoichiometry. The alloyed semiconductor may be a ternary semiconductor alloy, such as AxB1-xC or AB1-yCy, or a quaternary semiconductor alloy, such as AxByC1-x-yD, AxB1-xCyD1-y or ABxCyD1-x-y (where A, B, C, and D are different elements). In general, alloys with more than four elements can be used as well, although it can be much harder to control the synthesis and quality of such materials. Embodiments of the invention pertain to solar cells having a layer incorporating two or more organic materials such that percolated paths for one or both molecular species are created. Specific embodiments of the invention pertain to a method for fabricating nanostructured bulk heterojunction that facilitates both efficient exciton diffusion and charge transport.

Abstract: A method of manufacturing a photo-detector array device integrated with a read-out integrated circuit (ROIC) monolithically integrated for a laser-radar image signal. A detector array device, a photodiode and control devices for selecting and outputting a laser-radar image signal are simultaneously formed on an InP substrate. In addition, after the photodiode and the control devices are simultaneously formed on the InP substrate, the photodiode and the control devices are electrically separated from each other using a polyamide, whereby a PN junction surface of the photodiode is buried to reduce surface leakage current and improve electrical reliability, and the structure of the control devices can be simplified to improve image signal reception characteristics.

Abstract: Provided is a photoelectric conversion device including: a semiconductor substrate (3) of a first conductivity type; a photoelectric conversion region (7) of a second conductivity type which is located in the semiconductor substrate (3), the second conductivity type being opposite to the first conductivity type; and a buried layer (17) of the first conductivity type which is formed in an inner portion of the semiconductor substrate (3) to cover a lower side of the photoelectric conversion region (7), the buried layer (17) including a higher impurity concentration than the semiconductor substrate (3).

Abstract: Provided is a method of forming quantum dots, including: forming a buffer layer on an InP substrate so as to be lattice-matched with the InP substrate; and sequentially alternately depositing In(Ga)As layers and InAl(Ga)As or In(Ga, Al, As)P layers that are greatly lattice-mismatched with each other on the buffer layer so as to form In(Ga, Al)As or In(Ga, Al, P)As quantum dots.

Abstract: Embodiments of the invention are provided for a thin film stack containing a plurality of epitaxial stacks disposed on a substrate and a method for forming such a thin film stack. In one embodiment, the epitaxial stack contains a first sacrificial layer disposed over the substrate, a first epitaxial film disposed over the first sacrificial layer, a second sacrificial layer disposed over the first epitaxial film, and a second epitaxial film disposed over the second sacrificial layer. The thin film stack may further contain additional epitaxial films disposed over sacrificial layers. Generally, the epitaxial films contain gallium arsenide alloys and the sacrificial layers contain aluminum arsenide alloys. Methods provide the removal of the epitaxial films from the substrate by etching away the sacrificial layers during an epitaxial lift off (ELO) process. The epitaxial films are useful as photovoltaic cells, laser diodes, or other devices or materials.

Abstract: A semiconductor light detecting element having a mesa structure comprises: a first semiconductor layer having n-type conductivity located on a semiconductor substrate, a light absorbing layer located on the first semiconductor layer, and a second semiconductor layer located on the light absorbing layer; a burying layer burying peripheries of the light absorbing layer and the second semiconductor layer. The burying layer has a band gap larger than the band gap of the light absorbing layer. The second semiconductor layer has a first region having p-type conductivity, and a second region having i-type or n-type conductivity and located between the first region and the burying layer.

Abstract: A semiconductor photo detecting element includes a PIN-type photo detecting element and window semiconductor layer. The PIN-type photo detecting element has a semiconductor substrate, a first semiconductor layer, a second semiconductor layer and a third semiconductor layer. The first semiconductor layer is provided on the semiconductor substrate, is lattice-matched to the semiconductor substrate, includes a first conductivity type dopant, and has first band gap energy. The second semiconductor layer is provided on the first semiconductor layer, has the first band gap energy, and has a concentration of the first conductivity type dopant lower than that of the first semiconductor layer or is substantially undoped. The third semiconductor layer is provided on the second semiconductor layer. The window semiconductor layer has second band gap energy larger than the first band gap energy at a light-incoming side with respect to the second semiconductor layer and has a thickness of 5 nm to 50 nm.

Abstract: Provided are an optical receiver and a method of forming the same. The optical receiver includes a lens, a photo detector, and a hetero-junction bipolar transistor. The lens is attached to a backside of a substrate. The photo detector is disposed on a top surface of the substrate. The hetero-junction bipolar transistor is disposed on the top surface of the substrate. The lens condenses an incident optical signal to transmit the condensed optical signal to the photo detector.

Abstract: A semiconductor device structure comprising a first bulk crystal semiconductor material and a second bulk crystal semiconductor material provided on a surface of the first bulk crystal semiconductor material with or without a deliberate intermediate region, the second bulk crystal semiconductor material being a Group II-VI material dissimilar to the first bulk crystal semiconductor material, wherein portions of the first and/or second bulk crystal semiconductor material have been selectively removed to produce a patterned area of reduced thickness of the first and/or second bulk crystal semiconductor and preferably to expose a patterned area of the said surface of the first and/or second bulk crystal semiconductor material.

Abstract: The method is disclosed that Si+ is implanted on Si substrate to enhance strain relaxation at the interface between the metamorphic GexSi1?x buffer layers and Si substrate, in order to facilitate the growth of a high quality Ge on Si substrate. And several GexSi1?x buffer layers (Si/Ge0.8Si0.2/Ge0.9Si0.1/Ge) are grown on top of Si substrate by UHVCVD. Then grow pure Ge layer of low dislocation density on GexSi1?x buffer layer. Finally, grow up high efficiency III-V solar cell on GexSi1?x buffer layer.

Abstract: Methods and apparatus for converting electromagnetic radiation, such as solar energy, into electric energy with increased efficiency when compared to conventional solar cells are provided. A photovoltaic (PV) device generally includes a window layer; an absorber layer disposed below the window layer such that electrons are generated when photons travel through the window layer and are absorbed by the absorber layer; and a plurality of contacts for external connection coupled to the absorber layer, such that all of the contacts for external connection are disposed below the absorber layer and do not block any of the photons from reaching the absorber layer through the window layer. Locating all the contacts on the back side of the PV device avoids solar shadows caused by front side contacts, typically found in conventional solar cells. Therefore, PV devices described herein with back side contacts may allow for increased efficiency when compared to conventional solar cells.

Abstract: An image sensor has a substrate, a dielectric layer positioned on the substrate, a pixel array including a plurality of pixels defined on the substrate, a shield electrode positioned between any two adjacent pixel electrodes of the pixels, a photo conductive layer positioned on the shield electrode and the pixel electrodes, and a transparent conductive layer covering the photo conductive layer.

Abstract: A method for forming a nanostructure according to one embodiment includes creating a hole in an insulating layer positioned over an electrically conductive layer; and forming a nanocable in the hole such that the nanocable extends through the hole in the insulating layer and protrudes therefrom, the nanocable being in communication with the electrically conductive layer. Additional systems and methods are also presented.

Abstract: A method of forming a multijunction solar cell includes providing a substrate, forming a first subcell by depositing a nucleation layer over the substrate and a buffer layer including gallium arsenide (GaAs) over the nucleation layer, forming a middle second subcell having a heterojunction base and emitter disposed over the first subcell and forming first and second tunnel junction layers between the first and second subcells. The first tunnel junction layer includes GaAs over the first subcell and the second tunnel junction layer includes aluminum gallium arsenide (AlGaAs) over the first tunnel junction layer. The method further includes forming a third subcell having a homojunction base and emitter disposed over the middle subcell.

Abstract: The present invention provides a method for manufacturing a multi-junction solar cell which makes it possible to implement a 4-junction solar cell and to increase the area of a device. A nucleus generation site is disposed on a substrate 2 made of a first semiconductor. A first material gas is fed to the nucleus generation site to form a wire-like semiconductor 3 in the nucleus generation site. A third material gas and a fourth material gas are fed to form a wire-like semiconductor 4 on the semiconductor 3 and a wire-like semiconductor 5 on the semiconductor 4. A nucleus generation site is disposed on a substrate 6. The first material gas is fed to the nucleus generation site to form a wire-like semiconductor 2a in the nucleus generation site. A second material gas to the fourth material gas are fed to form the wire-like semiconductor 3 on the semiconductor 2a, the wire-like semiconductor 4 on the semiconductor 3, and the wire-like semiconductor 5 on the semiconductor 4.

Abstract: The invention is directed to a group-III nitride vertical-rods substrate. The group-III vertical-rods substrate comprises a substrate, a buffer layer and a vertical rod layer. The buffer layer is located over the substrate. The vertical rod layer is located on the buffer layer and the vertical rod layer is comprised of a plurality of vertical rods standing on the buffer layer.

Abstract: A new solar cell structure called a heterojunction barrier solar cell is described. As with previously reported quantum-well and quantum-dot solar cell structures, a layer of narrow band-gap material, such as GaAs or indium-rich InGaP, is inserted into the depletion region of a wide band-gap PN junction. Rather than being thin, however, the layer of narrow band-gap material is about 400-430 nm wide and forms a single, ultrawide well in the depletion region. Thin (e.g., 20-50 nm), wide band-gap InGaP barrier layers in the depletion region reduce the diode dark current. Engineering the electric field and barrier profile of the absorber layer, barrier layer, and p-type layer of the PN junction maximizes photogenerated carrier escape. This new twist on nanostructured solar cell design allows the separate optimization of current and voltage to maximize conversion efficiency.

Abstract: The invention relates to a structure usable in electronic, optical or optoelectronic engineering which comprises a substantially crystalline layer made of an alloy consisting of at least one element of the column II of the periodic elements system and/or at least one element of the column IV of the periodic elements system and of N2 (said alloy being noted N-IV-N2), wherein said structure also comprises an InN layer. A method for producing an indium nitride layer, a substrate forming plate and the use thereof for indium nitride growth are also disclosed.

Abstract: A barrier infrared detector with absorber materials having selectable cutoff wavelengths and its method of manufacture is described. A GaInAsSb absorber layer may be grown on a GaSb substrate layer formed by mixing GaSb and InAsSb by an absorber mixing ratio. A GaAlAsSb barrier layer may then be grown on the barrier layer formed by mixing GaSb and AlSbAs by a barrier mixing ratio. The absorber mixing ratio may be selected to adjust a band gap of the absorber layer and thereby determine a cutoff wavelength for the barrier infrared detector. The absorber mixing ratio may vary along an absorber layer growth direction. Various contact layer architectures may be used. In addition, a top contact layer may be isolated into an array of elements electrically isolated as individual functional detectors that may be used in a detector array, imaging array, or focal plane array.

Abstract: An apparatus and method for manufacturing thin-film CdS/CdTe photovoltaic modules in a vacuum environment. The apparatus deposits CdS and CdTe layers onto a substrate using heated pocket deposition, a form of physical vapor deposition (PVD) in which a material thermally sublimes from a thermal sublimation source block and is deposited onto a substrate. The thermal sublimation source block includes a pocket having a lower surface into which an array of holes is formed to house plugs of deposition material. Upon heating, deposition material sublimes from a surface of each plug of deposition material, and the surface of each plug regresses into its corresponding hole while maintaining a constant surface area. The sublimation surface area of deposition material across the pocket remains substantially constant during an extended deposition process, and the deposition material is substantially free of undesired thermal radiation from the substrate.

Abstract: Before a buffer layer deposition step P5, a pre-rinse step P4 is provided to remove deposits deposited on the surface of a CIS-based light absorbing layer 3D. Thus, the disturbing factors of the formation reaction of the buffer layer are removed, thereby to improve the coverage of the buffer layer, and to hold the transparency thereof. In addition, a rinse step P6 is provided after the step P5. Thus, the colloidal solid matter remaining on the buffer layer surface is cleaned and removed with a rinse solution, thereby to hold the high resistivity. The rinse solution from a second rinse tank of the step P6 is re-used. After the step P6, a draining/drying step P7 is provided. After drying, an n-type window layer (transparent conductive film) is deposited.

Abstract: A semiconducting device includes a p-type semiconducting layer; a plurality of nanostructures extending from the p-type semiconducting layer; and a n-type semiconducting layer, wherein the n-type semiconducting layer coats the p-type semiconducting layer and the plurality of nanostructures. A photovoltaic cell includes a p-type layer; a plurality of nanowires protruding from the p-type layer; and a n-type layer deposited on the p-type layer and the plurality of nanowires forming a heterojunction.

Abstract: A process for selectively freeing an epitaxial layer from a single crystal substrate upon which it was grown, by providing a first substrate; depositing a separation layer on the first substrate; depositing on the separation layer a sequence of layers of semiconductor material forming a solar cell; mounting and bonding a thin flexible support having a coefficient of thermal expansion substantially greater than that of the adjacent semiconductor material on top of the sequence of layers at an elevated temperature; and etching the separation layer while the temperature of the support and layers of semiconductor material decrease, so that the support and the attached layer curls away from the first substrate in view of their differences in coefficient of thermal expansion, so as to remove the epitaxial layer from the substrate.

Abstract: A fabrication method of fabricating a structure capable of being used for generation or detection of electromagnetic radiation includes a forming step of forming a layer containing a compound semiconductor on a substrate at a substrate temperature below about 300° C., a first heating step of heating the substrate with the layer in an ambience containing arsenic, and a second heating step of heating the substrate with the layer at the substrate temperature above about 600° C. in a gas ambience incapable of chemically reacting on the compound semiconductor. Structures of the present invention capable of being used for generation or detection of electromagnetic radiation can be fabricated using the fabrication method by appropriately regulating the substrate temperature, the heating time, the gas ambience and the like in the second heating step.

Abstract: A solar cell device includes a p-n diode component over a substrate, the p-n diode component including at least one subcell, each subcell including an n-type semiconductor layer and a p-type semiconductor layer to form a p-n junction. The solar cell device further includes at least two features selected from: i) a nano-structured region between at the p-n junction of at least one subcell; ii) an n-type and/or a p-type layer of at least one subcell that includes a built-in quasi-electric field; and iii) a photon reflector structure. Alternatively, the solar cell device includes at least two subcells, and further includes a nano-structured region at the p-n junction of at least one of the subcells, wherein the subcells of the solar cell device are connected in parallel to each other by the p-type or the n-type semiconductor layer of each subcell.

Abstract: The present invention relates to a nitride semiconductor thin film and a method for growing the same. The present invention has an advantage in that a plurality of grooves are formed on a substrate by partially etching the substrate, and leg portions for preventing longitudinal growth of a nitride semiconductor are formed within the grooves so that the nitride semiconductor thin film is grown laterally to cover top portions of the leg portions, thereby ensuring growth of a high quality nitride semiconductor thin film.

Abstract: The subject invention comprises the realization of a superlattice photodiode with polyimide surface passivation. Effective surface passivation of type-II InAs/GaSb superlattice photodiodes with cutoff wavelengths in the long-wavelength infrared is presented. A stable passivation layer, the electrical properties of which do not change as a function of the ambient environment, nor time, can be realized by a solvent-based surface preparation, vacuum desorption, and the application of an insulating polyimide layer.

Abstract: A passivation layer of AlN is deposited on a GaN channel HFET using molecular beam epitaxy (MBE). Using MBE, many other surfaces may also be coated with AlN, including silicon devices, nitride devices, GaN based LEDs and lasers as well as other semiconductor systems. The deposition is performed at approximately 150° C. and uses alternating beams of aluminum and remote plasma RF nitrogen to produce an approximately 500 ? thick AlN layer.

Abstract: There is provided a method for producing a multijunction solar cell having four-junctions, the method allowing the area of a device to be increased. On a nucleation site formed on a substrate 2, is grown a semiconductor 2a comprising the same material as the substrate 2 in the shape of a wire. On the semiconductor 2a, are successively grown semiconductors 3, 4, 5, and 6 with a narrower band gap in the shape of a wire. The semiconductor 3 may be directly grown in the shape of a wire on the nucleation site formed on the substrate 2. It is preferred to form the nucleation site by forming an amorphous SiO2 coating 8a on the substrate 2 and etching a part of the amorphous SiO2 coating 8a. Further, it is preferred to form an insulating film 8 in the region except the nucleation sites on the substrate 2 by allowing the amorphous SiO2 coating 8a to remain therein. The semiconductor 2a is GaP; the semiconductor 3 is Al0.3Ga0.7As; the semiconductor 4 is GaAs; the semiconductor 5 is In0.3Ga0.

Abstract: A multijunction solar cell including an upper first solar subcell having a first band gap; a middle second solar subcell adjacent to the first solar subcell and having a second band gap smaller than the first band gap and having a base layer and an adjacent emitter layer, wherein the other layer adjacent to the emitter layer has an index of refraction substantially equal to that of the emitter layer; a graded interlayer adjacent to the second solar having a third band gap greater than said second band gap; and a lower solar subcell adjacent to the interlayer, and having a fourth band gap smaller than the second band gap, the third subcell being lattice mismatched with respect to the second subcell.

Abstract: A method of manufacturing a solar cell by providing a first semiconductor substrate for the epitaxial growth of semiconductor material; forming a first subcell on the substrate with a first semiconductor material with a first band gap and a first lattice constant; forming a second subcell with a second semiconductor material with a second band gap and a second lattice constant, wherein the second band gap is less than the first band gap and the second lattice constant is greater than the first lattice constant; the second subcell including a strain balanced quantum well structure; and forming a lattice constant transition material positioned between the first subcell and the second subcell, the lattice constant transition material having a lattice constant that changes gradually from the first lattice constant to the second lattice constant.

Abstract: Methods of manufacturing a semiconductor device and resulting products. The semiconductor device includes a semiconductor substrate, a hetero semiconductor region hetero-adjoined with the semiconductor substrate, a gate insulation layer contacting the semiconductor substrate and a heterojunction of the hetero semiconductor region, a gate electrode formed on the gate insulation layer, an electric field alleviation region spaced apart from a heterojunction driving end of the heterojunction that contacts the gate insulation layer by a predetermined distance and contacting the semiconductor substrate and the gate insulation layer, a source electrode contacting the hetero semiconductor region and a drain electrode contacting the semiconductor substrate. A mask layer is formed on the hetero semiconductor region, and the electric field alleviation region and the heterojunction driving end are formed by using at least a portion of the first mask layer.

Abstract: A photo-detector, in which metal wiring for connecting electrodes is arranged on a planarized surface and thus the metal wiring arrangement is simplified, and a method of manufacturing the same are provided. The photo-detector includes a multi-layer compound semiconductor layer formed on a compound semiconductor substrate. A number of p-n junction diodes are arranged in a regular order in a selected region of the compound semiconductor layer, and an isolation region for individually isolating the p-n junction diodes is formed by implanting impurity ions in the multi-layer compound semiconductor layer. The isolation region and the surface of the compound semiconductor layer are positioned on the same level. The isolation region may be a Fe-impurity region.