Abstract: A method for tuning a digital compensation filter within a transmitter includes: obtaining at least one loop gain calibration result by performing loop gain calibration based upon signals of at least a portion of the transmitter, and obtaining at least one resistance-capacitance (RC) detection result by performing RC detection on the portion of the transmitter without individually measuring resistance values of resistors therein and capacitance values of capacitors therein, wherein the RC detection result corresponds to a detected value representing a product of a resistance value and a capacitance value, and the digital compensation filter includes a gain compensation module and an RC compensation module; and tuning the digital compensation filter by respectively inputting the loop gain calibration result and the RC detection result into the gain compensation module and the RC compensation module. An associated digital compensation filter and an associated calibration circuit are also provided.

Abstract: Methods and apparatus for determining at least part of the width of the eye of a high-speed serial data signal use clock and data recovery circuitry operating on that signal to produce a first clock signal having a first phase relationship to the data signal. The first clock signal is used to produce a second clock signal whose phase can be controllably shifted relative to the first phase. The second clock signal is used to sample the data signal with different amounts of phase shift, e.g., until error checking circuitry detects that data errors in the resulting sample exceed an acceptable threshold for such errors. The amount(s) of phase shift that caused exceeding the threshold can be used as a basis for a measurement of eye width.

Abstract: A local oscillator includes a phase-locked loop. The phase-locked loop includes voltage controlled oscillator (VCO) and a novel VCO control circuit. The VCO control circuit may be programmable and configurable. In one example, an instruction is received onto the VCO control circuit to change the power state of the VCO. The instruction is issued by other circuitry in response to a detected change in RF channel conditions (for example, a change in a signal-to-noise determination) in a cellular telephone. In response, the VCO control circuit outputs control signals that gradually widen the loop bandwidth of the PLL, then gradually change the VCO bias current to change the VCO power state, and then narrow the loop bandwidth of the PLL back to its original bandwidth. The entire process of widening the PLL bandwidth, changing the VCO power state, and narrowing the PLL bandwidth occurs while the PLL remains locked.

Abstract: A voltage controlled oscillator-phase lock loop (VCO-PLL) system includes a voltage controlled oscillator (VCO) system implementing four-channel architecture, such that two bands support two channels; a phase-locked-loop (PLL) system; and a mixer system. The VCO system further includes a control circuit; a first cross-coupled oscillator system adapted to receive a source voltage; a second cross-coupled oscillator system adapted to receive the source voltage; and a plurality of isolation buffer systems adapted to protect the first and second cross-coupled oscillator systems.

Abstract: A self-oscillating driver circuit comprises a driver stage, a feedforward path which is coupled to an input of the driver stage, and a feedback path which couples an output of the driver stage to an input of the feedforward path. The feedforward path comprises a feedforward filter which is designed as an active filter. In order to prevent an oscillatory state of the driver circuit at an unwanted frequency, it is proposed that an internal state variable of the feedforward filter be monitored and that the feedforward filter be reset if the value of the monitored internal state variable is outside a predefined range.

Abstract: The radio receiver includes: a mixer configured to convert a received signal to an IF signal using a local oscillation signal; an IF processing section configured to limit the band of the IF signal; a detection section configured to demodulate the band-limited IF signal; a frequency control section configured to output a frequency control signal corresponding to a desired signal; and a local oscillation section configured to generate the local oscillation signal having a frequency corresponding to the desired signal according to the frequency control signal. The frequency control section outputs as the frequency control signal to change the frequency of the local oscillation signal so that the difference from the frequency corresponding to the desired signal is not more than the frequency of the IF signal, and determines one of the set values with which the corresponding image signal strength is lowest as the frequency control signal.

Abstract: A radio frequency transceiver (102), including a transmitter (104), a duplexer (108) and a direct-conversion receiver (106) including a mixer (140 and 141). An IIP2 calibration system (170), coupled to the transceiver, includes an IIP2 coefficient estimator (172) for calculating an estimate of second-order distortion intermodulation distortion, and an IIP2 controller (174) for adjusting an IIP2 tuning port of the mixer in the receiver to minimize second-order distortion intermodulation distortion in the receiver that may be caused by the receiver receiving a transmit RF signal leaking through the duplexer.

Abstract: A wireless communication system includes: a filter; and a semiconductor chip including a signal processing integrated circuit having an amplifier, wherein a main surface of the semiconductor chip is provided with a plurality of electrode terminals along an edge portion thereof; wherein the amplifier has a transistor including a control electrode, a first electrode through which a signal is outputted, and a second electrode to which a voltage is applied; wherein the control electrode, the first electrode and the second electrode of the transistor are connected to the electrode terminals, respectively; and wherein none of wirings are arranged between the electrode terminals and placements of the control electrode, the first electrode and the second electrode, making space between the electrodes and the electrode terminals narrow.

Abstract: A frequency calibration loop circuit having a pre-set frequency channel word (FCW) command value, a bit inputted to obtain a target frequency in an oscillator and a pre-set minimum division ratio n (n is a constant) of a programmable divider, includes: an oscillator adjusting an oscillation frequency of an oscillation signal according to a control value; a programmable divider dividing the oscillation signal according to a division ratio to output a divided signal; a counter counting the number of clocks of the divided signal for one cycle of a reference signal to output a count value; and a frequency detector obtaining the control value by subtracting the count value from a reference comparison value, wherein the reference comparison value is obtained by dividing a Frequency Channel Word (FCW) command value by a minimum division ratio of the programmable divider.

Abstract: In one embodiment, this disclosure describes a frequency synthesizer for use in a wireless communication device, or similar device that requires precision frequency synthesis but small amounts of noise. In particular, the frequency synthesizer may include a phase locked loop (PLL) and an integrated voltage controlled oscillator (VCO). The frequency synthesizer may implement one or more calibration techniques to quickly and precisely calibrate the VCO. In this manner, the analog gain of the VCO can be significantly reduced, which may improve performance of the wireless communication device. Also, the initial state of the PLL may be improved to reduce lock time of the PLL, which may enhance performance of the wireless communication device.

Abstract: Common sample timing control for sample timing of multiple read channels, wherein the signal clocking of the signals received by the multiple read channels are correlated, for example from parallel tracks of magnetic tape that have been written simultaneously. In one embodiment, a common sample timing control comprises multiple phase error inputs, each indicating phase error of one of the read channels. Logic responsive to the multiple phase error inputs is configured to weight and crosscouple the phase error indication of each phase error input with the phase error indication of each other phase error input, and to apply gain related to the variance of noise of the phase error indications. Feedback logic is responsive to the crosscoupling and is configured to provide a sample timing phase estimate for each read channel.

Abstract: One embodiment includes a system configured to identify a preferred channel for radio communication from a plurality of consecutive integer frequencies including preferred channels and non-preferred channels, the system further to generate a plurality of radio channels corresponding to a plurality of consecutive integer frequencies based on a generation of reference frequencies, identifies preferred channels and non-preferred channels from the plurality of radio channels, where frequency synthesizer settling times of the preferred channels are faster than frequency synthesizer settling times of the non-preferred channels, scan the preferred channels for radio activity, select one of preferred channels responsive to the scanned radio activity; and utilize one of the reference frequencies to generate a radio frequency corresponding to the selected one of the preferred channels.

Abstract: Methods and systems for utilizing a single PLL to clock an array of DDFS for multi-protocol applications are disclosed. Aspects of one method may include generating a first signal for use in generating a plurality of local oscillator (LO) signals. The first signal may be communicated to a plurality of LO generators. Each of the LO signals may be generated independently of each other by a corresponding one of the LO generators. Each of the LO signals may be communicated to one or more mixers, where each mixer may perform down-conversion or up-conversion. A LO generator may utilize, for example, a DDFS or a digital delay circuit. A frequency of a LO signal may be varied by adjusting a divide factor for a divider that generates a reference clock for the DDFS or for a divider that generates a second signal used for mixing with a signal generated by the DDFS. The LO signal frequency may also be varied by adjusting frequency control words received by a DDFS.

Abstract: Methods and systems of generating a frequency switching local oscillator signal are disclosed. One method includes generating a reference clock signal, and clocking a counter with the reference clock signal. The counter controls selection of a one of a plurality of analog values stored in at least one of a plurality of periodic signal generators. The frequency switching local oscillator signal is generated by selecting an output of a one of the plurality of periodic signal generators.

Abstract: A technique for agile region and band conscious frequency planning for wireless transceivers in which a comparison frequency is selected for generating a local oscillator signal. The comparison frequency (Fcomp) is selected for a frequency band of a particular communication standard or protocol, in order not to introduce harmonic components of the selected comparison frequency in a transmitted signal from the wireless device that generates spurious emissions restricted by the particular communication protocol or another protocol. The Fcomp selection may also take into consideration restrictive region-specific criteria for out-of band spurious emissions.

Abstract: A technique for improving frequency synthesizer performance by frequency-compensating charge pump current in order to maintain a consistent loop bandwidth over a wide operating frequency range is described. A relationship between the capacitance value associated with a voltage controlled oscillator resonant tank and the magnitude of current pulses in a related charge pump is exploited to bound the loop bandwidth of the frequency synthesizer over both operating frequency and process variation. A control state machine generates digital coarse tune values that dynamically select a capacitance for the resonant tank, such that the voltage controlled oscillator operates within an optimal control voltage range. Each dynamically selected capacitance value is then used to determine the magnitude of current pulses in the charge pump.

Abstract: A method and apparatus for providing a dual-loop phase lock loop (PLL) for a radio-frequency (RF) receiver is provided. The dual-loop PLL may include coarse tuning circuitry and fine tuning circuitry. The coarse turning circuitry and fine tuning circuitry may be arranged in parallel. Both of the coarse tuning circuitry and fine tuning circuitry provide respective tuning signals to a voltage-controlled oscillator (e.g., a varactor tuned VCO). The coarse tuning circuitry and the fine tuning circuitry may provide the respective tuning signals simultaneously. In addition, coarse and fine tuning circuitry may be formed monolithically with other elements of the dual-loop PLL so as to provide a highly-integratable having a wide frequency lock range and high sensitivity.

Abstract: An integrated circuit (IC) includes a first die, a second die, a packaging substrate, and coupling circuit. The first die includes first circuitry and the second die includes second circuitry. The packaging substrate supports the first and second dies, wherein the first and second dies are stacked with respect to the packaging substrate. The coupling circuit couples the first die to the second die, wherein the first and second circuitry communicate via the coupling circuit.

Abstract: A signal filtering system for a frequency reuse system. A first implementation may include a downlink baseband signal, coupled to a downlink bandwidth filter, including a composite received signal including at least an interfering signal and a signal of interest, each having a composite bandwidth, a first bandwidth, and a second bandwidth, respectively. An uplink baseband signal may be included, coupled to an uplink bandwidth filter, having a replica of the interfering signal corresponding with the interfering signal and having an interference bandwidth. A baseband processing module may be coupled with the downlink bandwidth filter and the uplink bandwidth filter and may be configured to cancel the interfering signal from the composite received signal using the replica of the interfering signal. The downlink bandwidth filter may be configured to reduce the composite bandwidth and the uplink bandwidth filter may be configured to reduce the interference bandwidth.

Abstract: In one embodiment, the present invention includes a method for filtering an incoming signal in a channel filter of an automatic frequency control (AFC) loop to obtain a filtered incoming signal, generating a frequency offset from the filtered incoming signal in the AFC loop, removing the frequency offset from the incoming signal to obtain an adjusted signal, and providing the adjusted signal to an input of the channel filter.

Abstract: An apparatus including a first circuit, a second circuit, a third circuit, and a fourth circuit. The first circuit may be configured to generate a demodulated signal in response to a modulated signal and a seed value selected in response to a first control signal. The second circuit may be configured to generate a second control signal in response to the demodulated signal. The third circuit may be configured to generate the first control signal in response to the second control signal, a compensation signal, and the first control signal, where generation of the first control signal includes adding the second control signal, the compensation signal, and a latched version of the first control signal. Generation of the latched version of the first control signal may include sampling the first control signal in response to a clock signal. The compensation signal may compensate for variation in the clock signal.

Abstract: A clock and data recovery circuit including a phase synchronization loop including an oscillator, the oscillation frequency of which is variably controlled, the phase synchronization loop performing phase-synchronization of a clock signal output from the oscillator with an input data signal. The circuit also includes a discriminator circuit, responsive to a clock signal for discrimination, for discriminating the input data signal and outputting the discriminated signal. The circuit further includes a phase detector circuit for detecting the phase difference between an output data signal, discriminated and output by the discriminator circuit, and the input data signal. The circuit also includes a phase shift circuit for shifting the phase of the clock signal, output from the oscillator, based on a comparison result output from the phase detector circuit. The clock signal, which is output from the phase shift circuit, is supplied as the clock signal for discrimination to the discriminator circuit.

Abstract: A frequency synthesizer includes a digitally-controlled oscillator and an oscillation frequency control unit. The digitally-controlled oscillator includes a loop-shaped transmission line path having an odd number of parallel portions in each of which two conductors are arranged in parallel to each other with a space therebetween, and an odd number of intersection portions in each of which two conductors intersect spatially, an active circuit coupled between the two conductors, and a first variable capacitance unit and a second variable capacitance unit. The oscillation frequency control unit includes a ?? modulation circuit for subjecting to ?? modulation a first control signal for switching a high capacitance state and a low capacitance state of a first variable capacitance element included in the first variable capacitance unit.

Abstract: An object is to provide a PLL having a wide operating range. Another object is to provide a semiconductor device or a wireless tag which has a wide operating range in a communication distance or temperature by incorporating such a PLL. The semiconductor device or the wireless tag includes a first divider circuit; a second divider circuit; a phase comparator circuit to which an output of the first divider circuit and an output of the second divider circuit are provided; a loop filter to which an output of the phase comparator circuit is supplied and in which a time constant is switched in accordance with an inputted signal; and a voltage controlled oscillator circuit to which an output of the loop filter is supplied and which supplies an output to the second divider circuit.

Abstract: A radio frequency (RF) receiver with frequency planning includes an analog receiver, a digital processor, and a clock synthesizer. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, a signal output for providing an IF output signal, and a control output for providing a clock control signal. The clock synthesizer has an input for receiving the clock control signal, and an output for providing the clock signal, and is controllable to adjust a frequency of the clock signal to a selected one of a predetermined number of frequencies within a predetermined frequency range in response to the clock control signal.

Abstract: A clock recovery apparatus for generating a recovery clock from received data may include, but is not limited to, first and second oscillators. The first oscillator generates a first signal having a first frequency. The first signal synchronizes with the received data when the received data has a first level. The second oscillator is connected in series to the first oscillator. The second oscillator generates a second signal as the recovery clock when the first signal has a second level. The second signal has a second frequency. The second signal synchronizes with the first signal.

Abstract: A single chip receiver is disclosed herein. The chip only requires an external antenna for operation. A decoder is formed on chip for performing logical operations on demodulated digital data. A baseband filter is controlled by external control signals to have one of a plurality of discrete frequency response bandwidths depending on the type of signal to be received. To compensate for process variations in the implementation of the IC, bias currents setting the operating conditions for various amplifiers and other components in the system are adjusted based on frequency control signals in a PLL circuit in the local oscillator. Since the magnitude of the control signal reflects the process variations, the bias currents are adjusted based on the control signal to offset these variations in other portions of the receiver.

Abstract: A wireless communication system includes: a filter; and a semiconductor chip including a signal processing integrated circuit having an amplifier, wherein a main surface of the semiconductor chip is provided with a plurality of electrode terminals along an edge portion thereof; wherein the amplifier has a transistor including a control electrode, a first electrode through which a signal is outputted, and a second electrode to which a voltage is applied; wherein the control electrode, the first electrode and the second electrode of the transistor are connected to the electrode terminals, respectively; and wherein none of wirings are arranged between the electrode terminals and placements of the control electrode, the first electrode and the second electrode, making space between the electrodes and the electrode terminals narrow.

Abstract: There is provided a dual band receiver receiving frequency signals in different bands, the receiver including: a first down converter converting a first band signal into a first intermediate frequency signal; a second down converter converting a second band signal into a second intermediate frequency signal; a first voltage control oscillator supplying a first oscillation frequency to the first down converter; a second voltage control oscillator supplying a second oscillation frequency to the second down converter; a first filter passing the first intermediate frequency signal within a desired bandwidth; a second filter passing the second intermediate frequency signal within a desired bandwidth; and a clock generator converting the first oscillation frequency of the first voltage control oscillator into sampling frequencies corresponding to integer multiples of first and second oscillation frequencies and supplying the sampling frequencies to first and second AD converters, respectively.

Abstract: A receiver has a first semiconductor chip and second semiconductor chip for receiving signals of a first radio frequency band, and a communication unit for performing communication using signals of a second radio frequency band. A second mixing unit in the second semiconductor chip uses second local signals supplied from a second local signal oscillator when the frequency of first local signals fed from a first-local-signal-output terminal to a first-local-signal-input terminal is within a predetermined range from the second frequency band, or uses first local signals supplied from the first-local-signal-input terminal when the frequency of the first local signals fed from the first-local-signal-output terminal to the first-local-signal-input terminal is out of the predetermined range from the second frequency band.

Abstract: A frequency synthesizer for generating a plurality of frequencies of a MB-OFDM UWB system is disclosed, wherein the frequencies include first to fourteenth frequencies from low to high and any of the adjacent two frequencies differs by a basic intervallic frequency. The frequency synthesizer includes a phase locked loop generating an initial signal with a frequency equal to the second frequency, an intervallic frequency generator generating first to third intervallic frequencies from low to high and all being integers times the basic intervallic frequency and generating a forth intervallic frequency equal to the basic intervallic frequency, and first to third mixers connected in series, respectively receiving the fourth intervallic frequency, one of the first to third intervallic, and the first intervallic frequency, to respectively generate the first to third frequencies, the fourth to ninth and the thirteenth to fourteenth frequencies, and the tenth to twelfth frequencies.

Abstract: A GPS RF Front End IC using a single conversion stage, which is immune from self jamming from clock signal harmonics generated internally or from dominant clock signal harmonics generated externally by the subsequent baseband GPS processor which uses a clock of 48?fo for GPS processing. The improved frequency plan reduces the problems of interference when the integration of the RF and Baseband functions is required in the form of a single-chip, or as 2 individual chips on a common substrate.

Abstract: A system is provided, the system includes a phase-locked loop (PLL) that multiplies a reference clock input to generate a communication link clock signal. The system also includes a transmitter/receiver (TX/RX) module coupled to the PLL, the TX/RX module is configured to transmit and receive data based on the communication link clock signal. The system also includes a divider coupled to the PLL, the divider receives the communication link clock signal and outputs a PLL-adjusted reference clock that approximates the reference clock input. The PLL-adjusted reference clock is used to generate at least one other communication link clock signal.

Abstract: A system and method providing variable-frequency IF conversion in a multimode communication device. Various aspects of the present invention provide a multimode communication device comprising at least one RF signal receiver adapted to receive at least a first RF signal corresponding to a first communication protocol and a second RF signal corresponding to a second communication protocol. A controllable frequency source may, for example, be adapted to output a mixing signal characterized by one of a plurality of selectable frequencies. Such selectable frequencies may, for example, comprise a first frequency corresponding to the first communication protocol and a second frequency corresponding to the second communication protocol. A mixer may, for example, receive a received RF signal from the RF signal receiver, receive a mixing signal from the controllable frequency source, and convert the received RF signal to an IF signal utilizing the received mixing signal.

Abstract: A jitter measurement circuit and a method for calibrating the jitter measurement circuit are disclosed. The jitter measurement circuit includes a synchronous dual-phase detector and a decision circuit. In a test mode, a probability distribution function (PDF) of the jitter of a clock signal output by a circuit under test is obtained. In a calibration mode, a random clock, which is externally generated or generated by a free-run oscillator in the circuit under test, is used to calibrate the synchronous dual-phase detector. The decision circuit performs logic operations, data latching and counting on a phase relationship detected by the synchronous dual-phase detector in order to obtain a counting value and a PDF relative to the jitter of the clock signal.

Abstract: In a PLL circuit, an oscillation frequency is quickly and accurately locked to a target frequency. There is provided a PLL circuit, including a VCO that controls the frequency of an output signal according to a voltage of an input signal, a loop divider that divides the frequency of a signal, which is acquired by causing a mixer to mix a local signal generated by a local oscillator and the output signal with each other, by N, and a reference frequency divider that divides the frequency of a reference signal, which is output by a reference signal oscillator, by R.

Abstract: A phase detector includes a plurality of phase detectors located in a phase correction loop, each phase detector configured to receive as input a radio frequency (RF) input signal and an RF reference signal, each of the plurality of phase detectors also configured to provide a signal representing a different phase offset based on the phase difference between the RE input signal and the RF reference signal; and a switch configured to receive an output of each of the plurality of phase detectors and configured to select the output representing the phase offset, that is closest to a phase of an output of an amplifier.

Abstract: A Global Positioning System (GPS) receiver integrated with a cellular phone system, comprising a single-balanced mixer, a poly phase filter, a channel select filter, an analog-to-digital converter, a reference frequency source, and a PLL unit is disclosed. The single-balanced mixer downconverts a GPS signal to generate an in-phase signal I and a quadrature signal Q. The poly phase filter generates an IF signal based on the in-phase signal I and the quadrature signal Q. The channel select filter receives the IF signal to filter unwanted channel signals. The analog-to-digital converter converts the signal from the channel select filter to a digital output signal. The reference frequency source provides a reference frequency to the analog-to-digital converter. The PLL unit receives the reference frequency for generating a clock signal to the single-balanced mixer for downconversion.

Abstract: A sigma delta modulated phase lock loop reduces quantization noise by using phase interpolation to increase an effective frequency resolution of the dividing ratio of a divider.

Abstract: A method for reducing frequency glitches in a digital transceiver due to power amplifier input impedance variations. According to the method, the power amplifier is switched on after the end of a prior packet reception period and before a new packet transmission begins. Instead of ramping the power amplifier gain, the method ramps the modulation signals. As a consequence, any VCO frequency transients that may result from turning on the power amplifier have an opportunity to decay before the new packet transmission is initiated. This technique effectively isolates the transmitter power amplifier from the frequency synthesizer VCO to facilitate fast switching transceiver operation.

Abstract: A method for calibrating a phase locked loop begins by determining a gain offset of a voltage controlled oscillator of the phase locked loop. The processing then continues by adjusting current of a charge pump of the phase locked loop based on the gain offset.

Abstract: A filter circuit arrangement for filtering of a radio-frequency signal has a first tunable filter and a phase regulation loop in order to hold the first tunable filter to a transmission phase constant relative to the frequency of the radio-frequency signal. The filter circuit arrangement has a second tunable filter arranged parallel to the first tunable filter in the phase regulation loop. The first tunable filter and the second tunable filter exhibit different attenuation characteristics and are fashioned and connected within the phase regulation loop so that: a capture range of the filter circuit arrangement, in which a tuning of the phase regulation loop to a radio-frequency signal to be filtered is possible is dominated by the attenuation characteristic of the second tunable filter, and so that the transmission behavior of the filter circuit arrangement in operation is dominated by the attenuation characteristic of the first tunable filter, given a tuned phase regulation loop.

Abstract: A high-speed receiver includes multiple receiver components. Each receiver component includes sampling latches for receiving data, phase rotators for controlling timing of sampling of data by the sampling latches, and a clock-tracking logic stage for providing clock and data recovery. The clock-tracking logic stage is divided into a high-speed early/late (E/L) logic and aggregation counter section and a low-speed logic section, separated by a synchronization logic block. The receiver also includes a delay locked loop (DLL) for receiving an input clock signal corresponding to a data rate of the received data, providing coarse delay adjustment of the clock signal and outputting multiple clock phase vectors corresponding to the adjusted clock signal to the phase rotators on each receiver component. The phase rotators control sampling of the data based on the clock phase vectors received from the DLL. A single regulated power supply regulator regulates power supplied to the DLL and the phase rotators.

Abstract: A phase locked loop (PLL) includes a detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO), a divider, and a frequency change module. The detector provides a phase difference based on a reference signal and a feedback signal. The charge pump provides a charge based on the phase difference. The loop filter provides a voltage based on the charge. The VCO provides an output signal based on the voltage received from the loop filter. The divider divides a frequency of the output signal by a value to provide the feedback signal. The frequency change module processes an input signal having a first frequency to provide a processed signal having a second frequency that is different from the first frequency. The frequency change module selects the input signal or the processed signal to provide as the reference signal to the detector. Changing the frequency of the reference signal can change a frequency of a spur.

Abstract: An embodiment of the invention provides a clock and data recovery circuit. The clock and data recovery circuit comprises a phase detector, a pre-accumulator, a register, an accumulator and a digital controlled oscillator. By using the transmission path formed by the pre-accumulator, the output of the phase detector can be transmitted to the digital controlled oscillator in advance to adjust the frequency of its output clock signal and the latency due to the accumulator can be reduced.

Abstract: An FLL circuit having a capability of configuring a desired loop bandwidth in a short period of time is provided. An FDC 17 generates a feedback of an output signal of a VCO 15. An error detector 11 detects an error of the output signal of the VCO 15. A voltage retainer 13 retains an output of a control voltage of the VCO 15. A reference signal generator 16 generates a reference signal. An adder 14 adds the reference signal to a control voltage outputted by the voltage retainer 13. A Kv calculator 18 calculates a gain Kv of the VCO 15 based on a degree of transition of an output frequency of the VCO 15. A loop bandwidth controller 19 adjusts, based on the gain Kv of the VCO 15, a gain of a loop filter 12 to an optimum value, and configures a desired loop bandwidth.

Abstract: A semiconductor device, a spread spectrum clock generator and method thereof are provided. The example semiconductor device may include a frequency dividing unit receiving an output signal, generating a first feedback signal and a second feedback signal by dividing a frequency of the received output signal, and a phase offset unit outputting the output signal having a predetermined or desired phase difference with a reference signal in response to the second feedback signal, wherein the second feedback signal having a higher frequency than the first feedback signal. The example spread spectrum clock generator may include a plurality of frequency dividers which are connected in series and a selector selecting and outputting one of a plurality of output signals, each of the plurality of output signals having a different phase difference with respect to a reference signal, in response to at least one output from one or more of the plurality of frequency dividers.

Abstract: An integrated circuit radio transceiver and method therefor includes capacitive loop filter with selectable capacitive elements that are operable to adjust a signal level provided to a voltage controlled oscillator to control a frequency of an output signal of the oscillator. A plurality of switches are controlled by logic to define a discharge mode, a charge mode and charge sharing mode in which a plurality of capacitive elements share charge while generating the input voltage to the oscillator.

Abstract: A local oscillator (LO) signal generator that has a reference phase-locked loop (PLL), a receiver LO PLL and a transmitter LO PLL. A reference PLL is coupled to receive a reference clock input and to generate a reference PLL signal at its output, which then drives a receiver PLL and a transmitter PLL. The receiver PLL is coupled to receive the reference PLL signal and to use the reference PLL signal as its reference input to generate a receiver LO signal at its output. The transmitter PLL is coupled to receive the reference PLL signal and to use the reference PLL signal as its reference input to generate a transmitter LO signal at its output.

Abstract: A broadband integrated television receiver for receiving a standard antenna or cable input and outputting an analog composite video signal and composite audio signal is disclosed. The receiver employs an up-conversion mixer and a down-conversion mixer in series to produce an IF signal. An IF filter between the mixers performs coarse channel selection. The down-conversion mixer may be an image rejection mixer to provide additional filtering. The received RF television signals are converted to a standard 45.75 MHz IF signal for processing on-chip by additional circuitry.