Abstract: An amplifying circuit includes a pair of MOS transistors; an amplifier that amplify a difference between potentials of differential output nodes coupled to drains of the pair of MOS transistors; cancel circuits that cause cancel current to flow to one of the differential output nodes when the amplifier amplifies a voltage between the differential output nodes and that shut off, after the amplifier performs the amplification operation, inflow of the cancel current; and a controller that performs setting so that a potential of first one of the differential input signals is equal to a potential of another one of the differential input signals, that compares, before the inflow of the cancel current, potentials generated at differential output nodes when the difference between potentials of the differential output nodes is amplified, and that sets the cancel current so that the potentials are reversed after the inflow of the cancel current.

Abstract: A transmitter and a signal amplifier are provided. The signal amplifier includes a digital-to-analog converter converting an input digital signal into an analog signal, a local oscillator signal generator outputting in-phase and quadrature-phase oscillator signals, a first mixer mixing the analog signal with the in-phase local oscillator signal to output an in-phase high frequency signal, a second mixer mixing the analog signal with the quadrature-phase local oscillator signal to output a quadrature-phase high frequency signal, a main amplifier amplifying the in-phase high frequency signal output from the first mixer, and an auxiliary amplifier amplifying the quadrature-phase high frequency signal output from the second mixer.

Abstract: A system comprises a first clock module configured to generate a first clock reference that is not corrected using automatic frequency correction (AFC). A global position system (GPS) module is configured to receive the first clock reference. An integrated circuit for a cellular transceiver includes a system phase lock loop configured to receive the first clock reference, to perform AFC, and to generate a second clock reference that is AFC corrected.

Abstract: Circuits, systems, and methods are disclosed for controlling multiple antenna receive paths in a wireless communication device. In some embodiments, the circuit may include a pair of receiving antennas, a first receive path including a VCO coupled to receive a PLL signal and a first mixer coupled to receive a first signal from the VCO and a signal from one of the antennas, and a second receive path integrated separately from the first receive path including a second mixer coupled to receive a second signal from the VCO and a signal from the other antenna. By utilizing the output of the VCO to tune the first and second mixers in the first and second receive paths to the same phase and frequency, control of the multiple antenna receive paths may be optimized.

Abstract: A communication system comprising one or more transceiver units of a first type and one or more transceiver units of a second type capable of communicating with the transceiver units of the first type; each transceiver unit of the first type comprising: a frequency comparison unit for comparing the frequency of a signal received from a transceiver unit of the second type with a reference frequency; a feedback signal generator for generating a feedback signal dependent on the result of that comparison; and a transmitter for transmitting that signal to the transceiver unit of the second type; and each transceiver unit of the second type comprising: a local frequency reference unit on which the frequency of signals transmitted by it are dependent; and a frequency adjustment unit for receiving the feedback signal and adjusting the local frequency reference unit in dependence on the feedback signal.

Abstract: Some aspects of the present disclosure provide for polar modulation techniques that utilize an 180° phase shift module disposed downstream of a VCO-DCO. In some embodiments, this configuration allows a polar modulator to use the VCO-DCO to achieve small phase shifts (e.g., less than or equal to) 90°, while carrying out 180° phase shifts in the 180° phase shift module downstream of the VCO-DCO.

Abstract: A clock and data recovery device receives a serial data stream and produces recovered clock and data signals. The clock and data recovery device operates over a range of frequencies and without use an external reference clock. A first loop supplies a first clock signal to a second loop. The second loop modifies the first clock signal to produce the recovered clock signal and uses the recover clock signal to produce the recovered data signal. The first loop changes the frequency of the first clock signal based on frequency comparison and data transition density metrics.

Abstract: A system and method for low-cost performance and compliance testing of local oscillators and transmitters for wireless RF applications. A preferred embodiment comprises observing a digital signal from within an RF circuit, manipulating the signal with digital signal processing techniques, and determining if the RF circuit passes a test based upon results from the manipulating. Since the signal is clocked at a much lower frequency than an RF output of the RF circuit and the manipulation is performed digitally, testing can be performed at different stages of the production cycle and expensive test equipment can be eliminated.

Abstract: A receiver has an input amplifier (RFAMP) that comprises a signal-voltage amplifier (SVA) and a feedback path (FBP). The signal-voltage amplifier (SVA) provides a voltage gain (VG) from an input node (SESf) to an output node (SON). The voltage gain (VG) is controllable. The feedback path (FBP) provides a transadmittance (GM) from the output node (SON) to the input node (SIN). The transadmittance (GM) is controllable.

Abstract: A device is provided for dividing a clock signal by even and odd integers. The device includes a divider, a delay portion and a duty cycle corrector. The divider is arranged to receive the clock signal and can divide the clock signal and output a divided clock signal. The delay portion can output a delayed signal based on the divided clock signal. The duty cycle corrector can output a first signal based on the delayed signal and the divided clock signal.

Abstract: Systems of clock generation for integrated radio frequency receiver. In an integrated radio frequency receiver, a mixer is often used to down convert the incoming radio frequency signal. The down converted signal is then digitized and digital signal processing circuitry is used for efficient and flexible implementation of various functions to receive the underlying audio and/or data information. The mixer requires clock generation circuitry to provide a proper local oscillator signal for a selected channel. On the other hand, the digital signal processing circuitry requires its separate digital clock for proper operations. The clock generation system utilizes single local oscillator generation circuitry to provide the local oscillator signals required by the mixer and the digital clock signals required by the digital signal processing circuitry.

Abstract: Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.

Abstract: The transmitter of the transceiver includes: a transmitter-side mixers of a transmitter-side modulator; a transmitter-side voltage-controlled oscillator; and a transmitter-side divider. The divider having a dividing factor of a non-integral number is supplied with an oscillating output of the oscillator. A pair of non-quadrature local signals having a phase difference of 90° plus a predetermined offset angle is produced by the divider and supplied to the mixers. The transmitter includes a phase-shift unit which converts a pair of quadrature transmit signals having a phase difference of about 90° on an analog basis into a pair of non-quadrature shifted transmit signals. Consequently, quadrature modulation is performed by the mixers. Use of a similar configuration enables the reduction in interference of an RF signal with local signals supplied to receiver-side mixers of the receiver.

Abstract: An oscillator circuit having a source of an oscillating signal, a tank circuit including an inductor and a capacitor, and a discretely switchable capacitance module configured to control an amount of capacitance in the oscillator circuit. The discretely switchable capacitance module includes, in one embodiment, a capacitor coupled between a first node and a second node, a switch, having a control node, coupled between the second node and a third node; and a DC feed circuit, having a first end coupled to the second node and a second end configured to receive a first or second control signal. The control node of the switch is tied to a predetermined bias voltage. When the first control signal is applied, the capacitor is coupled between the first node and the third node via the switch such that the capacitor is coupled in parallel with the capacitor of the tank circuit, and when the second control signal is applied the capacitor is decoupled from the tank circuit.

Abstract: An apparatus for transferring data in a non-spread domain to a spread domain. The apparatus comprises a first-in-first-out (FIFO) memory; a write pointer generator adapted to generate a write pointer for writing data into the FIFO memory in response to a non-spread clock signal; a spread-clock generator adapted to generate a spread clock signal based on the non-spread clock signal; a read pointer generator adapted to generate a read pointer for reading data from the FIFO memory in response to the spread clock signal; and a controller adapted to control the spread-clock generator in response to the read and write pointers indicating predetermined potential data overflow or underflow of the FIFO memory.

Abstract: In one embodiment, a circuit comprises a first inductor-capacitor based voltage-controlled oscillator (LCVCO) generating a first periodic signal with a first frequency and a first phase and a second LCVCO generating a second periodic signal with a second frequency and a second phase, and the second phase is offset relative to the first phase by a 90 degrees offset.

Abstract: A rapidly adjustable local oscillation (LO) module for use in a radio transmitter or a radio receiver includes an oscillation generating module and a high frequency switching module. The oscillation generating module is operably coupled to generate a plurality of local oscillations. The high frequency switching module is operably coupled to, for a first one of a plurality of transmission paths, provide one of the plurality of local oscillations when a first transmission path selection indication is in a first state and provide another one of the plurality of local oscillations when the first transmission path selection indication is in a second state and, for a second one of the plurality of transmission paths, provide the one of the plurality of local oscillations when a second transmission path selection indication is in a first state and provide the another one of the plurality of local oscillations when the second transmission path selection indication is in a second state.

Abstract: Various embodiments relate to a receiver and a timing circuit for synchronization between a transmitter clock of an MPEG stream and the local system clock of a receiver. The timing circuit may implement a phase-locked loop (PLL) circuit with a PID controller to produce a control signal based on the difference between the transmitter reference clock and the local system clock. Various embodiments may use clock differential signals and an accumulated error signal to produce proportional, integral, and derivative output components for a control signal. The control signal may control a signal generator that adjusts the frequency and/or phase of the local signal clock to lock with the transmitter reference clock. Various embodiments may also include an outlier filter to remove error signals outside a defined range and/or a programmable system clock to add precision to the generated local system clock.

Abstract: A communication terminal includes first and second transmitters, which are coupled to produce respective first and second Radio Frequency (RF) signals that are phase-shifted with respect to one another by a beamforming phase offset, and to transmit the RF signals toward a remote communication terminal. The terminal includes a reception subsystem including first and second receivers and a phase correction unit. The first and second receivers are respectively coupled to receive third and fourth RF signals from the remote communication terminal. The phase correction unit is coupled to produce, responsively to the third and fourth RF signals, a phase correction for correcting an error component in the beamforming phase offset.

Abstract: A wireless communications system can include a charged particle generator configured to generate plural energized particles and a charge transformer configured to receive the plural energized particles that include charged particles from the charged particle generator and to output energized particles that include particles having substantially zero charge. The charged particle generator can be configured to direct the plural energized particles through the charge transformer to propagate through free space until received by a broadband signal receiver that can demodulate a data signal to complete the data communication.

Abstract: A system and method for generating for efficiently obtaining a desired harmonic from a fundamental frequency the prior art is needed. The system and method of the present invention produces a desired harmonic by employing techniques using gain stages (or limiter/comparator circuits) in combination with pre-defined offset voltages (or currents). The output signals of the gain stages are added with the correct phase to generate the desired harmonic.

Abstract: A differential transmitter and an auto-adjustment method of data strobe thereof are provided. The differential transmitter includes a phase-detecting unit, a switching unit, a rising edge strobe unit, and a falling edge strobe unit. The phase-detecting unit detects a phase relation between a clock signal and a data signal to outputs a detection result. The rising edge strobe unit latches the data signal at a rising edge of the clock signal, and converts a latching result to a first differential output signal. The falling-edge-strobe unit latches the data signal at a falling edge of the clock signal, and converts a latching result to a second differential output signal. The switching unit determines whether to switch the clock signal and data signal to the rising edge strobe unit or to the falling edge strobe unit according to the detection result.

Abstract: A method for processing wireless information is disclosed and may include performing by one or more circuits within a single-chip multi-band RF receiver, the one or more circuits comprising a filter, generating at least one control signal based on a signal strength of a baseband frequency signal generated by the one or more circuits within the single-chip multi-band RF receiver. A bandwidth of the filter may be adjusted using the generated at least one control signal. The generated baseband frequency signal may be filtered utilizing the bandwidth adjusted filter. A frequency response signal of the filter may be determined using a reference frequency signal. An attenuated reference frequency signal may be generated by attenuating the reference frequency signal. The attenuated reference frequency signal may be compared with the frequency response signal. The at least one control signal may be generated based on the comparison.

Abstract: A system and method providing variable-frequency IF conversion in a multimode communication device. Various aspects of the present invention provide a multimode communication device comprising at least one RF signal receiver adapted to receive at least a first RF signal corresponding to a first communication protocol and a second RF signal corresponding to a second communication protocol. A controllable frequency source may, for example, be adapted to output a mixing signal characterized by one of a plurality of selectable frequencies. Such selectable frequencies may, for example, comprise a first frequency corresponding to the first communication protocol and a second frequency corresponding to the second communication protocol. A mixer may, for example, receive a received RF signal from the RF signal receiver, receive a mixing signal from the controllable frequency source, and convert the received RF signal to an IF signal utilizing the received mixing signal.

Abstract: Disclosed herein is a carrier synchronizing circuit including at least frequency synchronizing means and phase synchronizing means. The phase synchronizing means includes residual frequency error detecting means for detecting a residual frequency error after a frequency synchronizing process by the frequency synchronizing means and supplying the residual frequency error to the frequency synchronizing means, and the frequency synchronizing means performs frequency pull-in for the residual frequency error supplied from the residual frequency error detecting means after first timing.

Abstract: Circuits, systems, and methods are disclosed for controlling multiple antenna receive paths in a wireless communication device. In some embodiments, the circuit may include a pair of receiving antennas, a first receive path including a VCO coupled to receive a PLL signal and a first mixer coupled to receive a first signal from the VCO and a signal from one of the antennas, and a second receive path integrated separately from the first receive path including a second mixer coupled to receive a second signal from the VCO and a signal from the other antenna. By utilizing the output of the VCO to tune the first and second mixers in the first and second receive paths to the same phase and frequency, control of the multiple antenna receive paths may be optimized.

Abstract: A clock generating device includes: a frequency divider having an input node coupled to a transmission interface for generating a reference clock signal according to an input data received from the transmission interface; and a clock/data recovery circuit having a data input node coupled to the transmission interface and a reference clock input node coupled to an output node of the frequency divider, for generating an output clock signal according to one of the input data received at the data input node and the reference clock signal received at the reference clock input node.

Abstract: Aspects of a method and system for compensating for using a transmitter to calibrate a receiver for channel equalization are provided. Various embodiments of the invention may be applicable wireless devices in TDM systems, Bluetooth, and/or WLAN applications, for example. Transmit tones may be generated by a transmitter PLL and the baseband response may be measured for each of the injected tones. The tones may be swept over a frequency range and a corresponding oscillator signal may be mixed with the received signal to determine the response of, for example, the receiver filters. Adjusting any of a plurality of receiver and/or transmitter parameters based on baseband measurements may provide appropriate channel compensation or calibration. Accordingly, the baseband circuitry may generate equalization signals, which may be utilized to adjust receiver and/or transmitter circuitry. This approach may be provide I/Q balancing and transmit filtering calibration after receiver calibration is completed.

Abstract: A VCO in a phase-locked loop (PLL) is arranged to receive low-pass data via a first input and high-pass data at a second input. The first input is coupled to a first set of varactors in the VCO. The second input is coupled to a second set of varactors in the VCO. The controller sets the input voltage at the first input and directs a charge pump to operate in a tri-state mode that opens the feedback loop of the PLL. The controller applies different voltages via the second input and measures the change in output frequency. A present gain of the VCO is determined from the ratio of the change in frequency and the change in voltage at the second input.

Abstract: A method for verifying alignment between first and second integrated devices coupled together using a reference and a coupling capacitor, including: transmitting a reference signal on a transmission electrode of the reference capacitor; receiving a coupling signal on a reception electrode of the reference capacitor; amplifying the coupling signal, generating a reception reference signal; generating a reception control signal as a function of the reception reference signal; transmitting a communication signal on an electrode of the coupling capacitor; receiving a reception signal on an electrode of the coupling capacitor; amplifying the reception signal, generating a first compensated signal; controlling a level of amplification of amplifying the coupling signal and the reception signal as a function of the reception control signal; and detecting a possible misalignment between the first and second devices based on an amplitude of the communication signal and an amplitude of the compensated signal.

Abstract: A method of a slot-level remapping physical uplink control channels into two resource blocks respectively located at two slots of a subframe, is generally adapted to a complex 3GPP LTE physical uplink where ACK/NAK recourse blocks may be applied by the extended cyclic prefix, mixed resource blocks (where the ACK/NAK and CQI channels coexist) may be applied by the normal cyclic prefix, or mixed recourse blocks (where the ACK/NAK and CQI channels coexist) may be applied by the extended cyclic prefix.

Abstract: Oscillator circuit for radio frequency transceivers. An oscillator circuit includes a first oscillator that generates a signal having a first frequency and a second oscillator that generates a signal having a second frequency. The oscillator circuit includes a mixer that is responsive to the signal having the first frequency and the signal having the second frequency to provide a signal having a third frequency and one or more frequency components. The oscillator circuit includes a filter that is responsive to the signal from the mixer to attenuate the one or more frequency components and provide a signal having a desired frequency. The oscillator circuit includes a correction circuit to correct a drift in at least one of the first frequency and the second frequency by controlling the second frequency, thereby correcting the drift in the third frequency and the desired frequency.

Abstract: A clock clean-up phase-locked loop (PLL) that may reduce spurs and improve performance of a receiver is described. In one exemplary design, an integrated circuit includes a PLL and an analog-to-digital converter (ADC). The PLL receives a first clock signal generated with a fractional divider ratio and having spurs due to abrupt frequency jumps. The first clock signal may be generated by a fractional-N frequency synthesizer external to the integrated circuit. The PLL generates a second clock signal with an integer divider ratio and having reduced spurs. The ADC digitizes an analog baseband signal based on the second clock signal and provides digital samples. The integrated circuit may further include a low noise amplifier (LNA), which may observe less spurs coupled via the substrate of the integrated circuit due to the use of the PLL to clean up the first clock signal.

Abstract: The present invention relates to a jitter measuring system, comprising: a delay circuit for receiving a clock signal and delaying the clock signal to generate a delay signal; a jitter amplifier for receiving the clock signal and delay signal to generate a first signal and a second signal; and a converter for converting a phase different between the first signal and the second signal into a relevant digital code; wherein the phase difference between the first signal and the second signal is an amplification of jitter.

Abstract: The present invention relates to a quadrature divider which may be used in a phase locked loop or frequency synthesizer or with a single side band mixer. According to a preferred embodiment the divider takes a quadrature input and has a quadrature output. The divider has four analog mixers 1, 2, 3 and 4. The first two mixers 1, 2 take the in-phase quadrature input, while the second mixers 3, 4 take the quadrature-phase quadrature input. The outputs and feedback loops of the mixers are properly arranged such that the in-phase and quadrature-phase outputs of the divider have a determinisitic phase sequence relationship based on the phase sequence relationship of the corresponding quadrature inputs. Third order harmonics may be minimized or reduced by addition or subtraction of the mixer outputs. As the divider is able to take a quadrature input, there is no need for a dummy divider in the phase locked loop, thus saving space and power.

Abstract: A data relay apparatus according to one embodiment described herein can include a phase detection unit that can detect a phase difference between a clock output from a transmitter and a clock output from a receiver, and generate a plurality of phase detection signals, a data relay control unit that can distinguish a difference in clock timing between the clocks of the transmitter and the receiver in response to the plurality of phase detection signals, and output a relay data selection signal and a relay control clock, and a data relay unit that can transmit data output from the receiver to the transmitter in response to the relay data selection signal and the relay control clock.

Abstract: An integrated circuit including a Phase Locked Loop (PLL) configured for use with a continuous stream receiver is disclosed. A control voltage line is configured to deliver a control voltage with a capacitive load delivered by a capacitor array to the control voltage based upon an add signal and a subtract signal. A threshold generator generates a high threshold voltage and a low threshold voltage using and including at least one process dependent resistor and at least two temperature and process dependent current sources. The PLL responds during calibration to the control voltage being above the high threshold voltage by asserting the add signal directing the capacitor array to increase the capacitive load on the control voltage line, and to the control voltage being below the low threshold voltage by asserting the subtract signal to decrease the capacitive load.

Abstract: In a receiving circuit 44 for receiving an electromagnetic wave signal, a frequency converter/detector circuit 100 comprises a local oscillator 131 for generating an oscillation signal, plural mixers 133, 134 for mixing the received electromagnetic wave signal with the oscillation signal to generate intermediate frequency signals having different phases, and a signal generating/synthesizing circuit 140 for generating based on the intermediate frequency signals generated by the mixers other intermediate frequency signals which are different in phase from the original intermediate frequency signals, for detecting the intermediate frequency signals and other intermediate frequency signal, and for adding the detected signals together to generate a synthesized signal.

Abstract: Provided are a multi-output oscillator using a single oscillator, and a method of generating multiple outputs. The multi-output oscillator includes: an oscillator outputting the single frequency; a multiplier multiplying the single frequency to output a first frequency; a first frequency divider dividing the single frequency by a first division factor; a first mixer outputting a second frequency by mixing an output of the first frequency divider and an output of the multiplier; a second frequency divider dividing the single frequency by a second division factor; a second mixer mixing the output of the second frequency divider and the output of the first mixer to output a third frequency; and a third mixer mixing the output of the second frequency divider and the output of the multiplier to output a fourth frequency.

Abstract: Methods and systems for coexistence in a multiband, multistandard communication system utilizing a plurality of phase locked loops (PLLs) are disclosed. Aspects may include determining one or more desired frequencies of operation of a transceiver, determining a frequency of unwanted signals such as spurs, intermodulation, and/or mixing product signals, and configuring the PLLs to operate at a multiple of the desired frequencies while avoiding the unwanted signals. The desired frequencies may be generated utilizing integer, which may include multi-modulus dividers. The wireless standards may include LTE, GSM, EDGE, GPS, Bluetooth, WiFi, and/or WCDMA, for example. The frequencies may be configured to mitigate interference. PLLs may be shared when operating in TDD mode, and used separately operating in FDD mode. One or more digital interface signals, zero exceptions on a transmitter spur emission mask, and sampling clocks for ADCs and/or DACs in the transceiver may be generated utilizing the PLLs.

Abstract: An electronic apparatus includes: a first integrated circuit including an internal component section, a nonvolatile memory, and an interface section; a test signal generation section configured to generate a test signal to be supplied to the first integrated circuit; a second integrated circuit including a processing section configured to process an output signal of the first integrated circuit, a signal processor to which the interface section of the first integrated circuit is connected and a detection section configured to detect decision information for deciding a result of the process of the test signal carried out by the processing section; and a control section configured to supply the test signal from the test signal generation section in place of the input signal to the first integrated circuit and issuing an instruction to the signal processor of the second integrated circuit to produce actual use adjustment data.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: In a system with an intermittently operating radio, the frequency of which is controlled by a Phase Locked Loop (PLL), a method and system for reducing the power consumed by the PLL by tri-stating the control capacitor in the PLL after the PLL has stabilized at a design frequency. After the capacitor is stabilized, power to some of the components in the PLL is reduced.

Abstract: A method, user equipment, and computer program product are disclosed for accepting a plurality of media streams at a first user equipment, and then sending a session initiation protocol refer request to a recipient. The request specifies a second user equipment, and the request also indicates a subset of those media streams which the recipient is requested to offer to the second user equipment. There can be at least two media streams of the same media type, out of which some media stream(s) are to be offered to the second user equipment and the other media stream(s) are not to be offered to the second user equipment.

Abstract: A demodulation system for Radio Data System (RDS) signals in a receiver includes a quadrature mixer (303) configured to convert a RDS signal at an input frequency directly to a base band RDS signal, a single filter (305) configured to filter the base band RDS signal to provide a RDS signal, and a signal level detector (311) configured to provide an indication of a level of the RDS signal (313), a demodulator (315) configured to demodulate the RDS signal and provide RDS data, the RDS data corresponding to information for user consumption, where the indication is used for selectively interrupting the user consumption when the level of the RDS signal is unsatisfactory.

Abstract: Provided is a modulating apparatus and method of an on-channel repeater. An object of the present invention is to provide a modulating apparatus of an on-channel repeater for reducing time delay by configuring and up-sampling a baseband signal, filtering the up-sampled baseband signal with an Equi-Ripple (ER) filter or in a window method, and converting the filtered baseband signal into an RF signal. The modulating apparatus includes: a baseband signal configuring unit for configuring a baseband. signal by combining an input field and a segment sync signal; a pilot adding unit for adding a pilot signal to the baseband signal; a filtering unit for filtering the baseband signal with the pilot signal; and an RF up-converting unit for up-converting the filtered signal into an RF signal. The present invention is used to form an on-channel repeating network in a transmitting system including a digital TV broadcasting system.

Abstract: A system and method are provided for holding the frequency of a non-synchronous communication signal in a clock and data recovery (CDR) device frequency synthesizer. The method initially acquires the phase of a non-synchronous first communication signal having a first frequency, and divides a first synthesized signal by a selected frequency ratio value, creating a frequency detection signal having a frequency equal to a reference signal frequency. In response to losing the first communication signal and subsequently receiving a second communication signal with a non-predetermined second frequency, the frequency ratio value is retrieved from memory based upon the assumption that the second frequency is the same, or close to the first frequency. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a second synthesized signal is generated having an output frequency equal to first frequency.

Abstract: An open loop frequency calibration algorithm is employed whereby frequency counters are utilized to provide frequency information concerning the difference in frequency between a local oscillator and a reference signal prior to obtaining phase locked operation of a phase locked loop (PLL). The frequency difference is then used to adjust the local oscillator's frequency to be changed by a value that is proportional to the frequency difference measured. Through adaptive calibration of the local oscillator's frequency prior to closed loop PLL operations, a substantial reduction in the amount of time required to obtain phase/frequency coherent operation of the PLL is realized.

Abstract: A spread spectrum controller (20) controls a PLL (10) so that the PLL outputs a spread-spectrum processed clock signal. A loop bandwidth controller (30) controls at least one of a phase detector (11), a loop filter (12), a voltage-controlled oscillator (13), and a frequency divider (14) in the PLL (10) during operation of the spread spectrum controller (20) to change a loop bandwidth of the PLL (10).

Abstract: A magnetically differential input circuit is arranged to define at least two loops, wherein each of the loops traverses the input of a receiving circuit. The loops are physically arranged so that a source of interference induces opposing signals in the loops, thereby effecting cancellation of the interference at the input of the receiving circuit. In one embodiment, the input circuit is arranged to be electrically differential as well as magnetically differential.