Abstract: A method includes transmitting, by a first node, a first carrier signal and receiving, from a second node, which receives the first carrier signal, a second carrier signal. The first node measures first and second values of a first phase, the first value assigned to a first frequency of the second carrier signal and the second value assigned to a second frequency of the second carrier signal. The first and second frequencies have a frequency difference. A third value of a second phase is assigned to a third frequency of the first carrier signal, and a fourth value of the second phase is assigned to a fourth frequency of the first carrier signal. The third and fourth frequencies have the frequency difference. A distance between the first and second nodes is determined from the frequency difference from the first and second values and from the third and fourth values.

Abstract: A transmitter including a first mixer, a first frequency divider to divide a frequency of an input signal to generate a first signal, and a plurality of second frequency dividers to divide the frequency to respectively generate a plurality of second signals, and a control module. In response to the transmitter being turned on, the control module turns on the first frequency divider, turns off the plurality of second frequency dividers, and drives the first mixer with the first signal. Subsequently, in response to determining that a transmit power of the transmitter is to be increased, the control module sequentially turns on and connects each of the plurality of second frequency dividers in parallel to the first frequency divider. Upon a second frequency divider being connected to the first frequency divider, the control module also drives the first mixer using the second signal generated by that second frequency divider.

Abstract: A communications device is disclosed that implements a phase-locked-loop to multiply a clock signal provided to a power management unit (PMU) by a variable integer value. Multiplying the PMU clock signal provides a second clock signal where the second clock signal is characterized by a fundamental component with one or more harmonics of the fundamental component that differ from the fundamental component and the one or more harmonics of the PMU clock signal. The fundamental component with one or more harmonics of the second clock signal does not occupy the same communication channel as the transmission communication signal of the communications device. Thus, minimizing the degradation of the transmission communication signal.

Abstract: A narrow band receiver or transceiver for processing electrical signals. The narrow band receiver or transceiver includes an amplifier, a voltage controlled oscillator and a tuning assembly comprising at least one control loop for tuning of the voltage controlled oscillator. At least a gain control of the amplifier is coupled to the control loop for simultaneously tuning the output amplitude of the voltage controlled oscillator and the gain of the amplifier. A compensation of the effect of variation on the gain of the amplifier, which includes an LC tank circuit, is performed by using an information in another LC tank circuit of the voltage controlled oscillator in the control loop.

Abstract: A wireless communication receiver includes a circuit, an analog-to-digital converter (ADC) and a processing circuit. The circuit receives a wireless signal and outputs an analog signal according to a gain index. The ADC converts the analog signal to a digital signal. The processing circuit adjusts the gain index according to a clipping number of the ADC.

Abstract: A clock data recovery circuit (CDR) extracts bit data values from a serial bit stream without reference to a transmitter clock. A controllable oscillator produces a regenerated clock signal controlled to match the frequency and phase of transitions between bits and the serial data is sampled at an optimal phase. A phase detector generates early-or-late indication bits for clock versus data transition times, which are accumulated and applied to a second order feedback control with two distinct feedback paths for frequency and phase, combined for correcting the controllable oscillator, selecting a sub-phase and/or determining an optimal phase at which the bit stream data values are sampled. The second order filter is operated at distinct rates such that the phase correction has a latency as short as one clock cycle and the frequency correction latency occurs over plural cycles.

Abstract: Embodiments of the present disclosure provide power-efficient time division duplexing (TDD) mode configurations of frequency division duplexing (FDD) transceivers. Embodiments avoid time slotted operation of the receive and transmit synthesizers, thereby avoiding undesired operation under transient conditions, frequent calibration, and reduced power supply efficiency. In embodiments, a single synthesizer is used to enable TDD operation, thereby reducing power consumption and calibration requirements by approximately 50%. The single synthesizer may be maintained ON at all times, thus allowing the power supply's switching regulator to operate with substantially constant load conditions.

Abstract: A method and apparatus for non-linear frequency control tracking of a control loop of a voltage controlled oscillator (VCO) in a wireless mobile device receiver is provided. A channel metric based on one or more channel quality indicators associated with a received radio frequency channel is determined and a state metric associated with the current operating state of the control loop are determined. One or more state metric threshold value associated with the determined channel metric, providing hysteresis between operating states, are determined wherein each state metric threshold value is associated with a transition to a possible operating state of the control loop. The control loop transitions from the current operating state to the operating state associated with an exceeded state metric threshold value. Coefficients are provided to an adaptive loop filter of the control loop, wherein the coefficients are associated with the transitioned operating state.

Abstract: A variable capacitance circuit includes: a prescribed node, to which an alternate current signal with a reference potential as a center voltage is applied; a first capacitor connected to the prescribed node; a second capacitor connected between the first capacitor and the reference potential; a third capacitor and a transistor for controlling capacitance, provide between a first node between the second capacitor and the first capacitor, and the reference potential; and a bias circuit which applies a first bias voltage to a second node between the third capacitor and the transistor.

Abstract: A phase locked loop (PLL) includes a detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO), a divider, and a frequency change module. The detector provides a phase difference based on a reference signal and a feedback signal. The charge pump provides a charge based on the phase difference. The loop filter provides a voltage based on the charge. The VCO provides an output signal based on the voltage received from the loop filter. The divider divides a frequency of the output signal by a value to provide the feedback signal. The frequency change module processes an input signal having a first frequency to provide a processed signal having a second frequency that is different from the first frequency. The frequency change module selects the input signal or the processed signal to provide as the reference signal to the detector. Changing the frequency of the reference signal can change a frequency of a spur.

Abstract: A signal generator for a transmitter or a receiver for transmitting or receiving RF-signals according to a given communication protocol includes an oscillator and a mismatch compensator. The oscillator is configured to provide a signal generator output signal having a signal generator output frequency and comprises a fine tuning circuit for providing a fine adjustment of the signal generator output frequency based on a fine tuning signal and a coarse tuning circuit for providing a course adjustment of the signal generator output frequency based on a coarse tuning signal.

Abstract: A method for tuning a digital compensation filter within a transmitter includes: obtaining at least one resistance-capacitance (RC) detection result, wherein the digital compensation filter includes an RC compensation module; and tuning the digital compensation filter by inputting the RC detection result into the RC compensation module. For example, the RC detection result may correspond to a detected value representing a product of a resistance value and a capacitance value. In another example, the at least one RC detection result may be obtained by performing RC detection on at least a portion of the transmitter without individually measuring resistance values of resistors therein and capacitance values of capacitors therein. An associated digital compensation filter and an associated calibration circuit are also provided.

Abstract: A frequency synthesizer for a WLAN transceiver is disclosed that may be used to generate 5.4 GHz and 2.4 GHz signals. The frequency synthesizer may be configured to minimize VCO pulling by using VCO operating frequencies that are not integer multiples of the RF bands. Further, the frequency synthesizer may be configured to minimize interference with other frequency bands used by existing wireless systems.

Abstract: This invention compensates for the unintentional magnetic coupling between a first and second inductor of two different closely spaced inductors separated by a conversion circuit. A cancellation circuit formed from transistors senses the magnetic coupling in the first inductor and feeds a current opposite to the induced magnetic coupling captured by the second inductor such that the coupled magnetic coupling can be compensated and allows the first and second inductors to behave independently with regards to the coupled magnetic coupling between the first and second inductors. This allows the distance between the first and second inductors to be minimized which saves silicon area. In addition, the performance is improved since the overall capacitance in both circuits can be decreased. This cancellation technique to reduce the magnetic coupling between two closed placed inductively loaded circuits allows the design of a more compact and faster performing circuit.

Abstract: A radio frequency (RF) receiver with frequency planning includes an analog receiver, a digital processor, and a clock synthesizer. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, a signal output for providing an IF output signal, and a control output for providing a clock control signal. The clock synthesizer has an input for receiving the clock control signal, and an output for providing the clock signal, and is controllable to adjust a frequency of the clock signal to a selected one of a predetermined number of frequencies within a predetermined frequency range in response to the clock control signal.

Abstract: In one embodiment, a method includes adjusting a first frequency of a first clock signal based on a frequency difference between the first frequency and a reference clock signal frequency of a reference clock signal, and further adjusting the first frequency and a first phase of the first clock signal based on a phase difference between the first clock signal and an input data bit stream and the frequency difference between the first frequency and the reference clock signal frequency to substantially lock the first frequency and the first phase of the first clock signal to the input data bit frequency and input data bit phase of the input data bit stream.

Abstract: A method and an apparatus for augmenting timing synchronization in a base station using backhaul network frequency synchronization are provided. When in a first mode an external time epoch reference synchronized with system time is used to synchronize the base station to system time. When in a second mode a network frequency reference recovered from a backhaul network link is used to maintain the timing synchronization.

Abstract: A direct-conversion transmitter including an oscillator, a frequency divider, a transmitter, and a filter is provided. The oscillator generates an oscillating signal with an original frequency. The frequency divider performs frequency dividing on the oscillating signal, so as to generate a carrier signal. The transmitter receives the carrier signal from the frequency divider and generates an output signal based on the carrier signal and a data signal. The filter is coupled between the frequency divider and the transmitter. The filter filters out an interference signal fed-back from the transmitter to the oscillator, wherein the interference signal may cause the oscillating signal to float.

Abstract: A circuit arrangement for generation of radio frequency output signals which form a broadband frequency ramp, with a reference oscillator, a phase detector, a loop filter, a VC oscillator for generating the output signals, a frequency divider, a step-down mixer and a local oscillator for generating a local oscillator signal. The reference oscillator, the phase detector, the loop filter, the VC oscillator, the frequency divider and the step-down mixer belong to a phase-locking loop. The frequency divider and the step-down mixer are in the feedback path of the phase-locking loop. The step-down mixer mixes the output signals and the local oscillator signal. The frequency of the output signal is adjustable by varying the division ratio of the frequency divider. Characteristics of the output signal are improved using the adjustable frequency of the local oscillator signal.

Abstract: A digital frequency synthesizer with an automatic calibration system. The digital frequency synthesizer is calibrated by initiating a coarse tuning operation to rapidly reach a preliminary frequency that is proximate to the desired final frequency. A calibration procedure is then executed for adjusting gain in the frequency synthesizer based on the preliminary frequency. This test involves applying one or more test signals to the frequency synthesizer and measuring a signal generated in the frequency synthesizer. This measured signal corresponds to a gain response of the circuit at the preliminary frequency. When the expected gain is known, any difference relative to the gain of the measured signal is used to adjust the gain in a circuit of the frequency synthesizer such that the actual gain substantially matches the expected gain.

Abstract: Apparatuses, circuits, and methods are disclosed for reducing or eliminating unintended operation resulting from metastability in data synchronization. In one such example apparatus, a sampling circuit is configured to provide four samples of a data input signal. A first and a second of the four samples are associated with a first edge of a latching signal, and a third and a fourth of the four samples are associated with a second edge of the latching signal. A masking circuit is configured to selectively mask a signal corresponding to one of the four samples responsive to the four samples not sharing a common logic level. The masking circuit is also configured to provide a decision signal responsive to selectively masking or not masking the signal.

Abstract: A wireless communications system includes a clock module, a communications module, a receiver module, and a baseband module. The clock module is configured to generate a first clock reference. The communications module is configured to operate in response to the first clock reference and independent of a corrected clock reference. The corrected clock reference is generated by performing automatic frequency correction on the first clock reference according to an automatic frequency correction signal. The receiver module is configured to (i) receive radio frequency signals from a wireless medium, and (ii) in response to the corrected clock reference, generate baseband signals based on the received radio frequency signals. The baseband module is configured to (i) receive the baseband signals, and (ii) in response to a selected one of the first clock reference and the corrected clock reference, generate the automatic frequency correction signal based on the baseband signals.

Abstract: A clock and data recovery device receives a serial data stream and produces recovered clock and data signals. The clock and data recovery device operates over a range of frequencies and without use an external reference clock. A first loop supplies a first clock signal to a second loop. The second loop modifies the first clock signal to produce the recovered clock signal and uses the recover clock signal to produce the recovered data signal. The first loop changes the frequency of the first clock signal based on frequency comparison and data transition density metrics.

Abstract: Techniques for performing analog calibration of a receiver to optimize a second-order input intercept point (IIP2). In an aspect, a signal generator modeling an interferer is coupled to an adjustable input of a receiver, e.g., a gate bias voltage of a mixer. For example, the signal generator output may be a single-tone on-off keying (OOK) modulated signal. The mixer mixes the signal down to baseband, wherein an analog correlator correlates the down-converted signal with the known sequence of bits used to perform the OOK modulation. The analog correlation output is then provided to drive the bias voltage in the mixer, e.g., one or more gate voltages of transistors in the differential mixer, to optimize the overall receiver IIP2. Further aspects of the disclosure provide for calibrating receivers having multiple LNA's, and also dual or diversity receivers having multiple receive paths.

Abstract: A frequency synthesizer includes a controlled oscillator configured to extend a temperature range and phase noise of the synthesizer without compromising the frequency coverage of the synthesizer. The frequency synthesizer also includes bias generation circuitry that sets a bias current of a charge pump to reduce bandwidth variations of the synthesizer. The frequency synthesizer further includes switching circuitry to dynamically turn a charge pump on and off to reduce effects of current leakage in the charge pump.

Abstract: A network device includes a physical layer transceiver configured to receive incoming data on a data link at an input clock rate and to store the incoming data in a buffer. The physical layer transceiver includes a Media Independent Interface (MII) controller configured to receive the incoming data stored in the buffer and to transmit the incoming data over a MII bus based on a MII clock where the MII clock is a spread spectrum clock. The network device further includes a Media Access Control (MAC) device configured to receiving incoming data from the physical layer transceiver over the MII bus where the incoming data is clocked by the spread spectrum MII clock.

Abstract: Adjusting a phase locked loop (PLL) clock source to reduce wireless communication (e.g., radio frequency (RF)) interference within a device. The PLL may be included in a high speed serial interface, e.g., coupled to a display, and may be initially driven by a first clock. Later, when a second clock is available and aligned with the first clock, the PLL may be driven by the second clock. The second clock may be configured to change its frequency over time such that the PLL does not lose lock and also does not interfere (or reduces interference) with wireless communication of the device. For example, the second clock may be programmable or may dynamically vary its operating frequency, thereby reducing its interference with the wireless communication of the device.

Abstract: A wireless base station apparatus communicates with first terminal devices belonging to the present cell by means of IDMA.

Abstract: A receiver, receiving method, and use of an in-phase signal and a quadrature-phase signal is provided, that includes a mixer in the receiving path, an oscillator whose output is connected to a mixer input of the mixer, whereby the oscillator is formed to output a base signal, oscillating at a base frequency, at the output, a clock generation device to generate a clock signal from the base signal, whose input is connected to the output of the oscillator, whereby the clock generation device has a frequency converter for converting a base frequency of the base signal by the factor F=x+A, where x is a positive whole number and A a rational number between 0 and 1, and a signal processing device, which is connected downstream of the mixer in the receive path, whereby the signal processing device is connected to the clock generation device for control with the clock signal.

Abstract: A wireless device having a central control entity that coordinates multiple radio transceivers co-located within the same device platform to mitigate coexistence interference. The wireless device comprises an LTE transceiver, a WiFi transceiver, a BT transceiver, or a GNSS receiver. In one embodiment, the central control entity receives radio signal information from the transceivers and determines control information. The control information is used to trigger FDM solution such that the transceivers operate in designated frequency channels to mitigate co-existence interference. In another embodiment, the central control entity receives traffic and scheduling information from the transceivers and determines control information. The control information is used to trigger TDM solution such that the transceivers are scheduled for transmitting or receiving radio signals over specific time duration to mitigate co-existence interference.

Abstract: A frequency offset of a received signal comprising a number of subsequently received data symbols is estimated. A first estimate is determined from a calculated change in phase of the received signal between two received symbols having a first time distance between them. At least one further estimate is determined from a calculated change in phase of the received signal between two received symbols having a different time distance. A frequency periodicity is determined for each estimate from the distance between the two received symbols from which the estimate was determined. A set of integer values is determined for each estimate so that frequency values calculated for each estimate as the frequency periodicity multiplied by the integer value added to the estimate are at least approximately equal to each other, and a corrected estimate of the frequency offset is determined from the integer values.

Abstract: A frequency synthesizer and a frequency synthesis method thereof are provided. The frequency synthesizer includes a phase-locked loop unit, a voltage-controlled oscillating unit, and a frequency mixing unit. The phase-locked loop unit receives a reference signal and a feedback injection signal and generates a first oscillating signal according to the reference signal and the feedback injection signal. The voltage-controlled oscillating unit receives the feedback injection signal and generates a second oscillating signal according to the feedback injection signal. The frequency mixing unit is coupled to the phase-locked loop unit and the voltage-controlled oscillating unit, receives the first oscillating signal and the second oscillating signal, and mixes the first oscillating signal and the second oscillating signal to generate the feedback injection signal and an output signal.

Abstract: A system includes a first clock module, a global positioning system (GPS) module, a phase-locked loop (PLL) module, a cellular transceiver, and a baseband module. The first clock module generates a first clock reference. The GPS module operates in response to the first clock reference. The WLAN module operates in response to the first clock reference. The PLL module generates a second clock reference by performing automatic frequency correction (AFC) on the first clock reference in response to an AFC signal. The cellular transceiver receives radio frequency signals from a wireless medium and generates baseband signals in response to the received radio frequency signals. The baseband module receives the baseband signals, operates in response to a selected one of the first clock reference and the second clock reference, and generates the AFC signal in response to the baseband signals.

Abstract: A portable wideband harmonic signal generator includes circuitry for generating a signal having a selected fundamental frequency, for producing a signal having a harmonic series of the selected fundamental frequency, for transferring the signal having the harmonic series using a balanced impedance output, and for directionally transmitting transferred signal having the harmonic series using a directional antenna having a characteristic impedance that is matched to the balanced impedance output. There is thus provided a compact, efficient transmitter and antenna assembly for transmitting a wideband signal.

Abstract: Aspects of a method and system for compensating for using a transmitter to calibrate a receiver for channel equalization are provided. Various embodiments of the invention may be applicable wireless devices in TDM systems, Bluetooth, and/or WLAN applications, for example. Transmit tones may be generated by a transmitter PLL and the baseband response may be measured for each of the injected tones. The tones may be swept over a frequency range and a corresponding oscillator signal may be mixed with the received signal to determine the response of, for example, the receiver filters. Adjusting any of a plurality of receiver and/or transmitter parameters based on baseband measurements may provide appropriate channel compensation or calibration. Accordingly, the baseband circuitry may generate equalization signals, which may be utilized to adjust receiver and/or transmitter circuitry. This approach may be provide I/Q balancing and transmit filtering calibration after receiver calibration is completed.

Abstract: A signal processor includes a frequency generator that employs a direct digital synthesizer (DDS) to generate a first local oscillator (LO) signal with a variable first LO frequency. The signal processor also includes an oscillator generating a second LO signal having a second LO frequency. The DDS employs programmable frequency control word and a sampling clock signal having a variable sampling clock frequency that is derived from the second LO frequency, to generate a DDS output signal from which the first LO signal is produced. The variable sampling clock frequency and the programmable frequency control word are selected to avoid crossing spurs in the frequency spectrum of the DDS output signal.

Abstract: A clock data recovery circuit includes a phase detector circuit, a majority voter circuit, and a phase shift circuit. The phase detector circuit is operable to compare a phase of a periodic signal to a phase of a data signal to generate a phase error signal. The majority voter circuit includes a shift register circuit. The shift register circuit is operable to generate an output signal based on the phase error signal. The majority voter circuit is operable to generate a majority vote of the phase error signal based on the output signal of the shift register circuit. The phase shift circuit is operable to set the phase of the periodic signal based on the majority vote generated by the majority voter circuit.

Abstract: The invention discloses a DCS/WCDMA dual frequency multiplexer. On one hand, the multiplexer utilizes distributed parameter type capacitors in place of conventionally used capacitors. On the other hand, within the multiplexer, a direct circuit and a RF circuit are isolated from each other physically. All components including capacitors co-exist together physically. Similarly, the invention further discloses a dual frequency multiplexer with large application range. It also utilizes the distributed parameter type capacitors like the DCS/WCDMA dual frequency multiplexer. Because the invention has redesigned the entire construction of the multiplexer, it results good effects such as small size, less differential loss, large power capacity, as well as high isolation degree between circuits.

Abstract: An electronic apparatus includes: a first integrated circuit including an internal component section capable of being adjusted with adjustment data, a nonvolatile memory in which beforehand acquired adjustment data of a result of adjustment carried out in advance for the internal component section are stored, and an interface section having a data transfer function of transferring the beforehand acquired adjustment data read out from the nonvolatile memory to the outside and a data storage function of storing actual use adjustment data sent thereto from the outside and supplying the stored actual use adjustment data to the internal component section; and a second integrated circuit including a signal processor, to which the interface section of the first integrated circuit is connected.

Abstract: Disclosed herein is a synchronizing circuit including: a first PLL circuit; a second PLL circuit; a first output circuit; a second output circuit; a first detection circuit; a second detection circuit; a control circuit; and a holding section.

Abstract: A digital delta sigma modulator includes an input integration stage, a resonating stage, a quantizer, and a plurality of feedback paths operably coupled to the quantizer, the input integration stage, and the resonating stage. The input integration stage is operably coupled to integrate a digital input signal to produce an integrated digital signal, wherein the input integration stage has a pole at substantially zero Hertz. The resonating stage is operably coupled to resonate the integrated digital signal to produce a resonating digital signal, wherein the resonating stage has poles at a frequency above zero Hertz. The quantizer stage is operably coupled to produce a quantized signal from the resonating digital signal.

Abstract: Disclosed are a phase shifter, a wireless communication apparatus, and a phase control method in which power consumption is reduced. A phase shifter includes a 90° step phase shifter (17) and a 45° phase shifter (18) and adds phase information to two baseband signals to be output to an orthogonal modulator. The 90° step phase shifter (17) contributes to adding any one of phases 0°, 90°, 180°, and 270° to the baseband signals according to a first control signal. The 45° phase shifter (18) contributes to adding one of phases 0° and 45° to the baseband signals according to a second control signal. A phase shifter (8) performs replacement of component signals of one of the baseband signals with component signals of the other of the baseband signals and inversion of polarities of the component signals.

Abstract: A frequency synthesizer includes a phase-locked loop circuit having an output. A frequency divider is connected to the output of the phase-locked loop circuit for receiving the signal therefrom and dividing the frequency of the signal. A tunable bandpass filter is connected to the frequency divider and is tuned for selecting a harmonic frequency to obtain a fractional frequency division for a signal output from the phase-locked loop circuit.

Abstract: A fractional-N PLL synthesizer has an up-down counter counting up for positive edges of a frequency-divided signal produced by a frequency divider with a fractional divide ratio in a feedback path of the synthesizer and down for positive edges of a reference signal. A phase offset between portions of the synthesizer signal before and after a loss-of-lock interval is then assessed as a numerical value proportional to the product of the divide ratio and the cycle difference registered by the up-down counter (36) after the loss-of-lock interval. A correction term derived from the phase offset can be used in a signal processing device as employed, e.g., in a GNSS receiver, for producing, from an analog input signal, a phase-corrected baseband signal where portions of the signal before and after loss of lock are phase coherent.

Abstract: A system and method for distance measurement between two nodes of a radio network is provided. A first unmodulated carrier signal is transmitted by the first node and received by the second node. A second unmodulated carrier signal is transmitted by the second node and received by the first node. A first value and a second value of a first phase are measured by the first node, whereby the first value of the first phase is assigned to a first frequency of the received second carrier signal and the second value the first phase is assigned to a second frequency of the received second carrier signal, whereby the first frequency and the second frequency have a frequency difference.

Abstract: The data processing unit (15) for a receiver of signals carrying information (1) includes a clock and data recovery circuit (16) on the basis of a data signal (DOUT), and a processor circuit (17) connected to the clock and data recovery circuit. The clock and data recovery circuit is clocked by a local clock signal (CLK) and includes a numerical phase lock loop, in which a numerically controlled oscillator (25) is arranged. This numerically controlled oscillator generates an in-phase pulse signal (IP) and a quadrature pulse signal (QP) at output. The frequency and phase of the pulse signals IP and QP are adapted on the basis of the received data signal (DOUT). The processor circuit is arranged to calculate over time the mean and variance of the numerical input signal (NCOIN) of the numerically controlled oscillator (25), so as to determine the coherence of the data signal if the calculated mean and variance are below a predefined coherence threshold.

Abstract: An RFID transponder comprises an antenna for receiving data in a downlink mode and transmitting data in an uplink mode, with a modulation stage for modulating uplink data and a demodulation stage for demodulating downlink data. A class C amplifier is provided, which has a resonant circuit, a plucking device coupled to the resonant circuit, and a controllable pulse width generator coupled to the plucking device. The controllable pulse width generator is adapted to periodically switch the plucking device on and off so as to maintain an oscillation of the resonant circuit. The transponder further comprises a phase locked loop configured to be locked to an oscillating signal received through the antenna and to be switched into a free running mode without being locked to the oscillating signal received through the antenna, thereby being adapted to output an independent internal clock signal for the RFID transponder.

Abstract: A system includes a first clock module, a global positioning system (GPS) module, a phase-locked loop (PLL) module, a cellular transceiver, and a baseband module. The first clock module generates a first clock reference. The GPS module operates in response to the first clock reference. The WLAN module operates in response to the first clock reference. The PLL module generates a second clock reference by performing automatic frequency correction (AFC) on the first clock reference in response to an AFC signal. The cellular transceiver receives radio frequency signals from a wireless medium and generates baseband signals in response to the received radio frequency signals. The baseband module receives the baseband signals, operates in response to a selected one of the first clock reference and the second clock reference, and generates the AFC signal in response to the baseband signals.

Abstract: Systems, methods, and circuits provide a time to digital converter comprising a sigma-delta modulator. The sigma-delta based time to digital converter may receive an analog signal representing a phase error between a reference clock signal and a feedback clock signal and generate a digital signal representing the phase error. The sigma-delta modulator may comprise a subtractor, an integrator, a feedback path, and a quantizer. The subtractor may receive the analog signal and subtract a feedback signal from the analog signal and the integrator may integrate the output of the subtractor. The sigma-delta modulator may accumulate a voltage or a charge over a capacitor as pulses are received from the analog signal and after a number of clock cycles, the capacitor may be discharged to generate a pulse in an output signal.

Abstract: A frequency synthesizer includes: a first oscillator (1) controlled by a first control device, the first oscillator having a high quality factor that is greater than 300 and produces a first clock signal (2) RF having a fixed frequency, the first control device (30) controlling the frequency of the first controlled oscillator (1) on the basis of a first reference frequency; a second oscillator (3) controlled by a second control device and producing a second clock signal (4); the second control device (31) controlling the frequency of the second controlled oscillator (3) on the basis of a second reference frequency; and an integer frequency divider (5) dividing the frequency of the second clock signal (4) by a variable integer factor N1 and producing a third clock signal (6), the frequency of which is continuously variable by modifying the factor N1 and the control of the second oscillator.