Abstract: An apparatus included a receiver for receiving an audio file signal, a decoder for demodulating the audio file signal; and a processor for polling the decoder for a loss of a phase lock in the demodulating of the audio file signal. The processor resets and reinitializes the decoder in response to the loss in the phase lock loop. The receiver includes 90 MHz radio frequency reception circuit. The decoder comprises an eight-to-four modulation EFM decoder. In the preferred embodiment, the decoder outputs a digital audio stream that conforms to a known I2S audio stream format.

Abstract: Embodiments of a millimeter-wave phase-locked loop with an injection-locked frequency divider (ILFD) are generally described herein. Other embodiments may be described and claimed. In some embodiments, the ILFD uses a quarter-wavelength transmission line. A method of calibrating an ILFD is also provided to allow the ILFD to operate at or near the center of its locking range for each of a plurality of VCO oscillating frequency bands.

Abstract: Synthesizers are configured with first and second phase-locked loops (PLL's). The first PLL is arranged to include a digitally-controlled oscillator (DCO) and to respond to an input signal to provide a reference signal with a plurality of selectable reference frequencies. The second PLL is arranged to include a voltage-controlled oscillator (VCO) to thereby provide output signals in response to the reference signal. This synthesizer structure is particularly effective when responding to a noisy input signal as may be the case, for example, in wireless communication systems that provide a network clock to transceivers through lengthy optical links.

Abstract: A phase locked loop (PLL) a phase detector, a charge pump, a loop filter, a controlled oscillator, and a feedback divider. The phase detector is coupled to produce a difference signal based on a difference between phase of a reference oscillation and phase of a feedback oscillation. The charge pump is coupled to convert the difference signal into an up-signal or a down signal. The loop filter coupled to filter the up signal or the down signal to produce a control signal. The controlled oscillator is coupled to generate an output oscillation based on the control signal. The feedback divider is coupled to generate the feedback oscillation from the output oscillation based on a divider value. The loop filter includes a first resistor-capacitor circuit and a second resistor-capacitor circuit. The first resistor-capacitor circuit is calibrated using a first calibration technique and the second resistor-capacitor circuit is calibrated using a second calibration technique.

Abstract: A system and method for ensuring proper synchronization of a plurality of frequency sources used in reception diversity-based radio reception. The frequency sources are concatenated in a synchronization loop, through which one frequency source having a high performance oscillator is configured as a master source. Through its oscillator, the master provides an internal synchronization signal that synchronizes all other sources, which have lower performance oscillators and are configured as slaves. Upon a failure in the master oscillator or in the synchronization loop, a slave source takes over as an alternative master source and provides its internal oscillator signal as an alternative synchronization signal to all other frequency sources.

Abstract: System and method for processing signals are disclosed. The method may include converting, in an RF receiver, one or more analog samples, which are selected from one of a plurality of output paths of the RF receiver, to one or more digital samples. A digital feedback value may be generated based on an average of the one or more converted digital samples. A scaled version of the generated digital feedback value may be converted to an analog value. The converted analog value may be fed back to one or more of a plurality of input paths of the RF receiver. The one or more analog samples may be selected from among a plurality of output analog samples from the plurality of output paths of the RF receiver.

Abstract: The present invention provides a voltage-controlled oscillator operating from microwave frequencies to millimeter wave frequencies, which is capable of outputting a large power with an output impedance thereof being set up to a predetermined level at low power consumption, and a communication device using the same.

Abstract: An RF transmitter (104) includes a shared local oscillator circuit (126), transmit path circuitry (120, 122, 124), a divider (134), and a lowpass filter (322). The shared local oscillator circuit (126) generates a shared LO signal (116). The transmit path circuitry (120, 122, 124) mixes a baseband signal (107) and an IF mixing signal (116) to provide an IF signal (112), and converts the IF signal (112) to an RF transmit signal (105) at a desired frequency using an RF mixing signal received at a mixing input thereof. The divider (134) divides the shared LO signal (116) to provide an unfiltered RF mixing signal. The lowpass filter (322) has an input for receiving the unfiltered RF mixing signal, and an output coupled to the mixing input of the transmit path circuitry (120, 122, 124) for providing the RF mixing signal.

Abstract: A method for controlling a synthesized local oscillator (SLO) includes: receiving a control input specifying a desired SLO output; receiving reference clock signal; generating a predefined set of dynamic clock signals from the reference clock signal; selecting a dynamic clock signal from the predefined set of dynamic clock signals in response to the control input; using the dynamic clock signal as an input to a direct digital synthesizer (DDS) module to generate a DDS output signal; selecting a DDS output band in response to the control input, the DDS output band including one of a baseband and an alias band; and processing the DDS output band to generate the SLO output.

Abstract: A phase/frequency detector module allows operation as either a phase locked loop or a frequency locked loop. As a phased locked loop (PLL), the phase detector module is configured to decode phase differences between a reference signal and a voltage controlled oscillator (VCO) signal into phase correction signals that are updated at the rate of the VCO signal. An accumulation of the phase correction signals is implemented to form an accumulated phase error signal, which is then sampled at a lower rate than the VCO signal to accommodate slower components of the PLL, such as a digital to analog converter (DAC). As a frequency locked loop (FLL), the phase detector module is configured with frequency counters, so that frequency error may instead be detected. Any reduction of gain caused by the frequency counters is inherently equalized by the phase detector module.

Abstract: A frequency synthesizer comprises: a single-tone signal generator which outputs signals of a single frequency; a frequency multiplier which generates one or more intermediate signals having different frequencies based on frequencies of input signals and outputs the same as output signals; a frequency selector; a mixer; and a frequency synthesizer control circuit which includes a frequency synthesizer control terminal, wherein an output of the single-tone signal generator is set as an input of the frequency multiplier, one or more outputs of the frequency multiplier are set as one or more inputs of the frequency selector, an output of the frequency selector and one output of the outputs of the frequency multiplier are set as first and second inputs of the mixer, and an output of the mixer is set as an output of the frequency synthesizer.

Abstract: In at least some embodiments, a communication system includes a receiver having a local oscillator (LO) for each of a plurality of frequency bands. Each LO is controlled by a separate phase-locked loop (PLL) that tracks carrier frequency offset (CFO) using a common phase error (CPE). The CPE is selectively weighted based on at least one inter-band frequency correlation (IFC) coefficient.

Abstract: A stereo decoding system comprises an oscillator, a bandpass filter, a PLL unit and a stereo decoder. The oscillator generates a first signal with a center frequency. The bandpass filter receives a stereo multiplexed signal and the first signal to filter out a pilot signal. The PLL unit receives the pilot signal to generate a PLL output signal. The stereo decoder receives the stereo multiplexed signal and the PLL output signal to separate a left channel signal and a right channel signal from the stereo multiplexed signal.

Abstract: A wireless receiver (100) for receiving and demodulating a frequency modulated RF (radio frequency) signal by a direct conversion procedure, including channels (110, 112) for producing in-phase and quadrature components of a received RF signal, and a processor (123, 133) for periodically estimating an error in at least one of the in-phase and quadrature phase components and for producing a signal for adjustment of at least one of the in-phase and quadrature components to compensate for the detected error, wherein the processor is operable to apply alternatively each of a plurality of different procedures to estimate the error, the procedures including a first procedure which is applied when a signal quality value of the received RF signal is above a threshold value and a second procedure which is applied when a signal quality value of the RF received signal is not above the threshold value.

Abstract: A method of generating an output signal comprises receiving an input signal, mixing the input signal with a reference signal having a reference frequency to obtain an intermediate frequency signal having an intermediate frequency, filtering the intermediate frequency signal using a filter having a filter characteristic that is configured according to the intermediate frequency and performing frequency translation on the filtered intermediate frequency signal to obtain the output signal.

Abstract: A wireless communication system includes: a base station; a first wireless communication terminal that receives a first signal from the base station; and a second wireless communication terminal that receives a second signal from the base station. The first signal is to be used by the second wireless communication terminal. The first wireless communication terminal includes: a transmitting unit that transmits the first signal to the second wireless communication terminal. The second wireless communication terminal includes: a receiving unit that receives the first signal from the first wireless communication terminal; and a signal synthesizing unit that receives the first signal from the receiving unit and performs at least one synthesis based on the first signal and the second signal.

Abstract: A digital phase locked loop (PLL) includes a digital phase detector, a digital loop filter, a digitally controlled oscillation module, and a variable feedback divider. The digital phase detector is coupled to produce a difference signal based on a phase difference between a reference oscillation and a feedback oscillation. The digital loop filter is coupled to process the difference signal to produce a control signal. The digitally controlled oscillation module is coupled to generate an output oscillation based on the control signal. The variable feedback divider is coupled to produce the feedback oscillation from the output oscillation based on a divider value and a controlled variable delay.

Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. An input baseband signal is interpolated and upconverted in the digital domain to an IF. The LO operates at a frequency which is a n/m division of the target RF frequency fRF. The IF frequency is configured to ½ of the LO frequency. The upconverted IF signal is then converted to the analog domain via digital power amplifiers followed by voltage combiners. The output of the combiners is band pass filtered to extract the desired replica.

Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. The signal is input to a synthesizer timed to a rational multiplier of the RF frequency fRF. The signal is then divided to generate a plurality of phases of the divided signal. A plurality of combination signals are generated which are then multiplied by a set of weights and summed to cancel out some undersired products. The result is filtered to generate the LO output signal.

Abstract: A method of communication between a first transceiver having a first local oscillator set at a first frequency and a second transceiver having a second local oscillator set at a second frequency disclosed. The method includes transmitting a first signal at a first frequency from the first transceiver to the second transceiver, transmitting a second signal at the second frequency from the second transceiver to the first transceiver, and receiving the second signal at the first transceiver. The method further includes maintaining the first local oscillator at the first frequency and the second local oscillator at the second frequency during the transmitting of the first signal, during the receiving of the first signal, during the transmitting of the second signal, and during the receiving of the second signal.

Abstract: A technique of frequency hopping communication capable of high-speed switching of a plurality of signals having ultra-wide band 528 MHz bandwidth at high-speed and setting and switching a band center frequency and the number of bands arbitrary is provided. A radio transceiver has a frequency hopping communication function of UWB system for switching the ultra wide band signal. In the device, high-speed frequency hopping is realized by controlling an SSB mixer in a local oscillator circuit and switching the frequency of a DDS. The device sets NCO data to the DDS and switches a quadrature phase signal of an output, and switches a signal input of an input terminal of the SSB mixer by a control of a phase switching switch. One of a sum component and a difference component of a mixture of first and second quadrature phase signals is outputted from the output terminal of the SSB mixer.

Abstract: The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation. This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulates the output of the counter, and a comparison operation circuit block that compares the count value of the ACL and the design value pre-stored in a register, and the loop gain of the PLL circuit is detected taking advantage of the fact that the ACL count value is inversely proportional to the loop gain. Based on the detection result, the loop gain is calibrated by correcting the loop gain with a charge pump current, etc. This allows the PLL circuit to maintain stable loop characteristics that will not affect the characteristics variation of each element constituting the PLL.

Abstract: A method of performing a frequency correction of a radio module. Multiple samples of frequency data during a quiescent portion of the base station transmission is taken to estimate the amount of frequency correction needed. An embodiment applies the frequency data to a median filter to eliminate invalid data. Next, a new reference frequency is applied to a radio transceiver in the radio module to provide the frequency correction. If the frequency was corrected by greater than a pre-determined amount, the process performs a large shift frequency correction, including verifying that the first frequency correction was satisfactory and verifying that the radio transceiver is able to receive data after the frequency correction has been performed. If the frequency was corrected by smaller than a pre-determined amount, the process performs a small shift frequency correction, including updating a total of all frequency corrections made since a stored reference frequency was updated.

Abstract: Transceivers for use in time division telecommunication units in a transmitting mode, include switching a direct digital synthesizer (DDS) driven phase locked loop (PLL) into a modulating state and supplying a modulation signal to the DDS and switching in the PLL a first filter, thus allowing the generation of an improved modulated signal. In a receiving mode, the DDS driven PLL is switched into an oscillating state including supplying a non-modulation signal to the DDS and switching in the PLL a second filter, thus allowing demodulation with reduced phase noise. A transmitter part and a non-transmitter part share a single DDS driven PLL.

Abstract: A system and method for communicating between a base and a remote device in a security system. The base receives an audio signal from a telephone network via a panel and then frequency modulates the audio signal at a carrier frequency to generate an FM signal. The remote device receives the FM signal from the base, determines a phase error signal representing the phase error between the received FM signal and an output signal of a voltage controlled oscillator, determines a difference between the carrier frequency and a center frequency of the voltage controlled oscillator, and, if there is a difference, then changes the center frequency of the voltage controlled oscillator to match the carrier frequency of the FM signal.

Abstract: A multi-mode PLL frequency synthesizer of a wireless multi-mode transceiver is provided which includes a reference frequency source providing an oscillator signal with a constant reference frequency, a first frequency synthesizer subunit for converting the signal into carrier signals with frequencies in the range of a first frequency band, a second frequency synthesizer subunit for transforming the oscillator signal into carrier signals having frequencies in the range of a second frequency band, and a third frequency synthesizer subunit for converting the oscillator signal into an auxiliary signal with a fixed frequency. The auxiliary signal is used together with the carrier signals of the second frequency band to generate carrier signals with frequencies in the range of a third and fourth frequency band.

Abstract: A method is for reducing a DC component of an input signal transposed into baseband and being generated by a first frequency transposition stage starting from an initial signal and from a transposition signal. The method includes amplifying the transposed input signal in a first amplifier. The first amplifier receives at a DC offset compensation input, a compensation signal extracted from an output signal of a second amplifier subjected to a compensation of a offset DC voltage of the second amplifier. The method also included alternating between receiving at an input of the second amplifier, a first auxiliary signal from an auto-transposition of a transposition signal in a second frequency transposition stage and a second auxiliary signal from a transposition of the initial signal in the second frequency transposition stage with the transposition signal.

Abstract: The invention relates to a phase-locked loop circuit including a phase detector, loop filter and an oscillator. The loop filter is implemented digitally instead of by means of analog components. The chip area required for such a digital loop filter is substantially smaller than an analog equivalence and can be implemented on a single integrated circuit die together with an oscillator, phase detector and possible counters. There is thus no need for the use of external components, greatly simplifying the design and manufacture of the circuit, and having reduced assemblage costs. Further, by means of the digital filter the loop dynamics are also easily changed.

Abstract: A novel system and method for correcting the residual phase offset between a recovered pilot signal and the received stereo signal. The invention uses a Costas loop as an auxiliary loop in addition to the pilot recovery phase locked loop (PLL) to lock onto the stereo component itself. This auxiliary loop functions to generate a pilot to stereo component phase correction signal that is added to the stereo carrier phase The resultant phase is used to generate the recovered pilot carrier used to demodulate the stereo MPX signal. The Costas loop is activated together with the main pilot recovery PLL that locks onto the pilot tone in the demodulated MPX signal. The auxiliary Costas loop is operative to track and determine a residual phase error of up to several degrees.

Abstract: A wireless communication system includes: a filter; and a semiconductor chip including a signal processing integrated circuit having an amplifier, wherein a main surface of the semiconductor chip is provided with a plurality of electrode terminals along an edge portion thereof; wherein the amplifier has a transistor including a control electrode, a first electrode through which a signal is outputted, and a second electrode to which a voltage is applied; wherein the control electrode, the first electrode and the second electrode of the transistor are connected to the electrode terminals, respectively; and wherein none of wirings are arranged between the electrode terminals and placements of the control electrode, the first electrode and the second electrode, making space between the electrodes and the electrode terminals narrow.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A method of controlling a phase locked loop in a mobile station and a mobile station of a cellular telecommunications system are provided. The mobile station comprises an integrated phase locked loop for generating output frequencies; a frequency control unit for providing a frequency control word for the phase locked loop, according to which frequency control word an output frequency is generated; and a tuning unit for providing a synchronized tuning word for the phase locked loop, the tuning unit being configured to output the synchronized tuning word to the phase locked loop in synchronization with the output of the frequency control word. The invention reduces the settling time of a mobile station when an operating frequency is changed from one to another.

Abstract: An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A programmable filter is connected to receive the phase error samples and connected to provide a filtered output having a gain and a phase margin to the controllable oscillator. The programmable filter includes a proportional loop gain control having a programmable loop gain coefficient (alpha—?) and an integral loop gain control having a programmable loop gain coefficient (rho—?). Alpha and rho are configured to be programmatically changed simultaneously and are selected such that the gain is changed and the phase margin remains substantially unchanged.

Abstract: A phase detector includes a first clock driver comprising a first LC tank. The first clock driver provides a strobe to a plurality of flip-flops associated with sampled data being received by the phase detector. The second clock driver includes a second LC tank. The second clock driver provides a strobe to a plurality of flip-flops associated with sampling the phase error of the phase detector. The first and second LC tanks have different adjustable center frequencies and experience a programmable delay between the outputs of the first and second clock drivers so as to determine the data sampling phase of the phase detector.

Abstract: A device and method for synthesizing a transmission frequency (a Tx frequency) in a wireless terminal are provided, which are designed for stably operating a Phase Locked Loop (PLL) in order to synthesize a Tx frequency for a certain channel.

Abstract: In one embodiment, a phase error signal generated by a phase detector is equalized to compensate for the distortion in the phase error signal due to finite circuit speeds. The equalization may be based on suppressing the low frequency components of the phase error signal. For example, the amplitude of the phase error signal may be reduced when the amplitude of the phase error signal is not changing.

Abstract: A circuit and method for tracking a local oscillator signal frequency in an RF tuner, for tuning input RF signals. The RF tuner includes a frequency-dependent impedance generator that generates a frequency-dependent impedance at the input by rejecting unwanted input RF signals and shunt feeding back the desired signal to the input. The desired signal frequency is centered at the local oscillator signal frequency. The frequency-dependent impedance generator is used with an amplifier circuit to generate a tracking amplifier, the frequency-dependent amplifier gain of which tracks the local oscillator signal frequency.

Abstract: The proposed apparatus and is used for signal generation by multiplexing signals such that there appears no glitches in an output signal. The present apparatus utilizes the knowledge of phase difference between input oscillator signals being multiplexed in order to provide a glitchless output signal. The apparatus comprises a first selection circuit configured to synchronize its response to a first control signal to a next determined event of one of input oscillator signals and convey an input oscillator signal to its output in response to the first control signal. The apparatus comprises a similar selection circuit for each input oscillator signal being multiplexed. Outputs of the selection circuits may be connected to a combining circuit which combines the outputs, thus providing the glitchless output signal.

Abstract: A distortion compensator, comprising a distortion component generator that generates a distortion component orthogonal baseband signal corresponding to a nonlinear distortion component based upon an analog orthogonal baseband signal, a distortion component synthesizer that synthesizes a composite signal by combining the analog orthogonal baseband signal and the distortion component orthogonal baseband signal and a first switch through which control is executed as to whether or not to input the distortion component orthogonal baseband signal to the distortion component synthesizer, is provided.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A clock and data recovery apparatus reduces current consumption and enables easy integration. The inventive apparatus includes a first loop including a frequency/phase detection unit, a first charge pump unit, a multiplexing unit, a filtering unit, and a voltage controlled oscillator unit operating at a speed ¼ as fast as that of received data; a second loop having a phase detection unit operating at a speed ¼ as fast as a speed of received data, a second charge pump unit suitable for the phase detection unit, the multiplexing unit, the filtering unit, and the voltage controlled oscillator unit; a frequency lock detection unit for judging whether a frequency of a feedback clock signal falls within a desired frequency range; and a data recovery unit for recovering data from received data.

Abstract: A numerically-controlled phase-lock loop with input clock dependent ratio adjustment provides for narrower-bandwidth loops that lock to a wide range of frequencies and/or operation with an absent or degraded input timing reference. A timing reference characteristic detector determines an input frequency range of the input timing reference signal, the data type of the timing reference, and/or whether a timing reference signal of sufficient quality is present. A numerically controlled oscillator is controlled by a numeric ratio that is adjusted to provide the desired clock frequency output in conformity with the detected frequency range and/or data type. If the timing reference signal is absent or degraded, then the numeric ratio can be set to a fixed value or a local timing reference can be applied in order to generate the desired clock output frequency.

Abstract: Aspects of a method and system for bandwidth calibration for a phase locked loop are presented. Aspects of the method may include generating one or more carrier signals based on one or more corresponding calibration signals. A pre-distortion function may be computed based on the generated one or more carrier signals for the phase locked loop circuit. An output radio frequency (RF) synthesized signal generated by the phase locked loop circuit may be modified based on the computed pre-distortion function and a subsequent output RF synthesized signal generated based on the modified output RF synthesized signal.

Abstract: A highly agile low phase noise frequency synthesizer is provided for rapid generation of frequency specific signals. The frequency synthesizer is capable of rapidly generating signals at different output frequencies while maintaining low cross-coupling. Two or more signal generators utilize a reference frequency to generate two or more signals. These signals are limit processed to reduce cross-coupling prior to being presented to a switch. Responsive to a control signal, the switch outputs one of the signals to a frequency modification device, such as a frequency divider or multiplier. Responsive to a control signal, the frequency modification device scales the frequency of the switch output to convert the frequency of the switch output signal to a desired output frequency. By maintaining sufficient frequency separation between the switch input signals cross-coupling and phase noise is minimized and implementation on an integrated circuit may be achieved.

Abstract: A device and a method for processing high data rate serial data includes a VCO initial frequency calibration circuit. The circuit includes a frequency detection block for indicating a difference between a reference clock and a divided VCO clock, a frequency calibration block that produces a digital output signal based upon the difference between the reference clock and the divided VCO clock, and a digital-to-analog converter for producing an analog VCO adjust signal. The frequency detection block produces a plurality of signals based upon the reference clock and the divided VCO clock. A plurality of user selected inputs selects a frequency detection lock range and hysteresis range and a coarse loop open calibration lock and hysteresis range. The frequency calibration block implements a state machine for producing the digital output signal that sets the initial operating frequency then adjusts the frequency of the VCO clock.

Abstract: Provided is a frequency modulation circuit 1 for outputting a highly precise frequency-modulated signal regardless of variation in a characteristic of a VCO 15. A correction value calculation section 17 calculates a correction value Vt2 based on a voltage value (Vtx?Vt1) resulting from subtracting a control voltage Vt1, which is generated by a control voltage generation section 11, from a control voltage Vtx at which a sensitivity of the VCO 15 is maximized. A variable amplifier 18 amplifies the correction value Vt2. An addition section 13 outputs a control voltage Vt3, which results from adding the amplified correction value Vt2 to the control voltage Vt1, to the VCO 15 via a DAC 14.

Abstract: A phase tracking system includes a source of an input signal representing a received symbol. A phase rotator has a first input terminal which is responsive to the input signal, a second input terminal which is responsive to a phase correction signal, and an output terminal which produces a phase adjusted output signal. A decision element generates an ideal signal representing the received symbol in response to the phase adjusted output signal. A phase adjuster, which has full phase wrap-around capability, generates the phase correction signal in response to the phase difference between the phase adjusted output signal and the ideal signal.

Abstract: A slot-based low Intermediate Frequency (‘IF’) radio receiver comprises an IF local oscillator (3, 5, 19) for producing I and Q IF local oscillator signal components in phase quadrature, I and Q mixer channels (4, 6) for mixing the input signal with the I and Q IF local oscillator signal components to produce I and Q IF signal components. The IF local oscillator (3, 5, 19) includes frequency alternation means (20) for causing the IF local oscillator frequency to alternate a plurality of times during each frame between first and second values, one of which is greater and the other smaller than the desired carrier frequency of the input signal so as to reduce the effect of adjacent and alternate interferers. The phase of the baseband local oscillator (12, 13) is alternated in synchronism with the alternation of the IF local oscillator frequency.

Abstract: A wireless communication device includes an integrated circuit (IC) and an antenna system. The IC includes a baseband processing module, a network processing module, a calibration processing module, a receiver section and a transmitter section. The network processing module establishes a wireless communication protocol and operational parameters based on the wireless communication protocol. The calibration processing module generates RF receiver calibration information based on the operational parameters and RF receive feedback and generates RF transmitter calibration information based on the operational parameters and RF transmit feedback. The receiver section provides the RF receive feedback and converts an inbound RF signal into an inbound symbol stream. The transmitter section provides the RF transmit feedback and converts an outbound symbol stream into an outbound RF signal.

Abstract: The phase locked loop (PLL) with adjustable phase shift is described. The PLL includes a voltage controlled oscillator which is capable of generating multiple phase shifted output signals, and multiple phase detectors capable of determining the phase differences between the output signals and a reference clock. The PLL further includes a weighting device capable of weighting the phase differences and generating a control signal for the voltage controlled oscillator.