Abstract: A circuit extracting apparatus or method of the present invention extracts circuit information which allows a drain current and a gate capacitance in an actual device to be reproduced with high fidelity in circuit simulation. Transistor-portion-configuration recognizing means recognizes the configuration of a transistor portion in the mask layout of a semiconductor circuit so as to generate transistor-portion-configuration data. Transistor-size calculating means calculates an equivalent transistor size based on the transistor-portion-configuration data, such that a drain current in the circuit simulation coincides with the drain current in the actual device. Corrective-capacitance generating means obtains the difference between a gate capacitance in the circuit simulation using the equivalent transistor size and the gate capacitance in the actual device so as to virtually generate a corrective capacitance having a capacitance value corresponding to the obtained difference.

Abstract: A method for the simulation of responses of a nonlinear amplifier provides for measuring characteristics of nonlinearity of amplitude and of amplitude/phase-shift conversion of the amplifier, each measurement being made at an amplitude that is constant in input. The method further includes measuring the characteristics at different frequencies, developing the characteristics in sequences of direct transfer functions, computing frequency correctors for the direct transfer functions, measuring characteristics of distortion of amplitude modulation, each measurement being performed by modulating the input amplitude, computing modulation transfer functions reproducing the distortion amplitudes at output according to the input modulation amplitudes and correcting the direct transfer functions when the input amplitude is modulated in order to simulate the envelope memory effect. There is a direct application of the invention to the field of the simulation of high efficiency microwave amplification.

Abstract: A computer-aided logic circuit designing apparatus in which data on a plurality of circuits is stored in a database, the data on a plurality of circuits is read out therefrom and combined by a net list-RTL description combining section, a clock system portion is analyzed based on the logic circuit obtained by combining the data by a clock system analyzing section, and a result of the analysis is displayed by an analysis result display section correlating each type of clock system to a corresponding clock input element.

Abstract: The present invention evaluates the power dissipation of an electronic circuit. A power dissipation value is calculated for each transition or event generated during the electronic simulation of an electronic circuit design that corresponds to an actual electronic circuit. The present invention relies on data that includes an electronic circuit design description of the electronic circuit, such as a gate level netlist; a cell library having a power model corresponding to a cell instance; cell activity data such as net transitions; and the total effective load seen by each cell pin of the logic cell to be evaluated for power. The power model includes simple arcs (transition delay values, energy per arc values, cell input capacitances, and output slew rate values) and power evaluation data.

Abstract: A method and system are disclosed that utilize the expressiveness of hardware description languages for automatically adjusting counting rates of instrumentation within a simulation model of a digital circuit design, during simulation of said digital circuit design. According to the present invention a design entity that will be incorporated into a simulation model of a digital circuit design is described utilizing a hardware description language. The design entity operates, during simulation, in conformity with a design cycle that consists of a multiple of a simulator cycle. Next, an instrumentation entity is described utilizing the same hardware description language. The description of the instrumentation entity contains logic to detect occurrences of a count event that occurs in conformity with the design cycle during simulation.

Abstract: A system and method for analyzing timing and noise effects in a hybrid circuit which contains a plurality of electrical components. The timing and noise effects for the hybrid circuit are generated by simulating electrical conditions within a hybrid circuit model. The hybrid circuit model is constructed by creating and integrating analog and behavioral models from the plurality of electrical components. The timing and noise effects remain accurate even at high printed circuit board/multi-chip module clock speeds, thereby ensuring that a user is able to construct an optimal design for any one of the plurality of electrical components.

Abstract: A digital logic simulation/emulation system (20) operates in an engaged operating mode in which a digital-logic simulation process (22) transmits stimulation-control data to a hardware pod (32) for controlling stimulation of a digital logic circuit. In response to the stimulation-control data, the hardware pod (32) performs a stimulation-response cycle, and then sends response data from the digital logic circuit to the simulation process (22). The simulation process (22) and the hardware pod (32) may also operate in a disengaged operating mode in which each operates independently of the other without exchanging stimulation-control data or response data. Operation of the system (20) in the disengaged mode commences if a disengagement event occurs in the hardware pod (32). Operation of the system (20) in the disengaged mode terminates if the simulation process (22) sends stimulation-control data to the hardware pod (32), or if the hardware pod (32) sends response data to the simulation process (22).

Abstract: An apparatus architecture is provided which permits an easily programmed apparatus (10) to serve as an equivalent of an integrated circuit chip, and/or as a building block for a large system. The apparatus (10) is connected to a communications bus (40) which receives apparatus parameter, topological, and microinstruction information from a host processor and/or memory (EPROM). The apparatus includes numerous functional blocks (20), a core (30), and a parametric/microinstruction bus (35). The functional blocks include serial (62,66) and parallel ports (68), D/A (54) and A/D (52) converters, and programmable signal processors (300) which serve to process signal data and are connected in any desired manner through a switching matrix (160) located in the core. The topology of the switching matrix (160) is received via the communications bus (40).

Abstract: An interface system for testing and verifying the design of an ASIC at different levels of abstraction, wherein the ASIC includes a logic entity and a processor entity. The system of the present invention is embodied as software which executes within a computer system. The software, when executed by the computer system, causes the computer system to implement a model of the ASIC, a simulator, and a test interface. The model of the ASIC is embodied in HDL (Hardware Description Language) and includes a logic entity and a processor entity. The simulator is adapted to test the model. The test interface interfaces the model with the simulator. The test interface includes a simulator portion and a model portion. The simulator portion is coupled to the simulator. The model portion is embodied in HDL and is coupled to both the logic entity and the processor entity. The model portion and the simulator portion are coupled to exchange information.

Abstract: In an LSI defective automatic analysis system disclosed here, a potential measuring means 1 applies a series of test vectors to a designated sample and measures an operating potential of a designated place on a surface of an LSI chip at the moment the test vector of a designated address is applied. A potential estimating means 2 receives another measured potential value already obtained, and estimates, in the same sample, the potential of another place or the potential when another test vector is applied. A potential measurement condition determining means 3 receives the measured potential value and the estimated potential value already obtained, and instructs the LSI sample to be measured, the place to be measured and the test vector address to be used, as the condition for the potential measurement required to search for a defective cause place.

Abstract: A method and system are disclosed that utilize the expressiveness of hardware description languages for selectively disabling instrumentation during simulation of a digital circuit design. According to the present invention, an instrumentation entity, described utilizing a hardware description language to include an output signal to indicate an occurrence of an event during simulation, is implemented into a simulation model of a digital circuit design. Next, the output signal is associated with a unique output storage element. Finally, a disable mechanism uniquely associated with said output signal is provided, such that the output signal may be selectively masked by disabling the storage element during simulation testing of the digital circuit design.

Abstract: A method and system are disclosed that utilize the expressiveness of hardware description languages for efficiently and comprehensively monitoring performance characteristics of a digital circuit design during simulation. According to the present invention, a design entity that is part of a digital circuit design is first described utilizing a hardware description language. Next, an instrumentation entity is described utilizing the same hardware description language. Thereafter, the design entity is instantiated in at least one instance within a simulation model of a digital circuit design. Finally, the instrumentation entity is associated with the design entity utilizing a non-conventional call, such that the instrumentation entity may be utilized to monitor each instantiation of the design entity within the simulation model without the instrumentation entity becoming incorporated into the digital circuit design.

Abstract: A time-frequency method and apparatus are disclosed for simulating the initial transient response of quartz oscillators. An original system of differential algebraic equations that characterize a quartz oscillator are reformulated using a system of well-defined partial differential equations (PDEs). The quartz oscillator is initially represented by a system of ordinary differential algebraic equations that are then reformulated using an artificial system of partial differential algebraic equations. The artificial system represents the behavior of the quartz oscillator with two artificial time axes, t1 and t2, at least one of which has periodic boundary conditions. The artificial system is solved numerically using an integration technique along a strip of the artificial system, defined by [0, T(t2)[×[0, ∞[. Thereafter, the time behavior of the signal is calculated from the numerical solution of the artificial system.

Abstract: The present invention is a method of recovering a gate-level netlist from a transistor-level netlist by functionally describing each gate to be recovered using a first transistor model; generating a signature for each gate to be recovered; receiving the transistor-level netlist; selecting a set of connected components from the transistor-level netlist; functionally describing the set of connected components using the first transistor model; generating a signature for the set of connected components; comparing the signature of the set of connected components to the signature of each gate to be recovered; if the signature of the set of connected components matches a signature of a to be recovered then determining if the corresponding functional descriptions match; if a match occurs then functionally describing the set of connected components using a second transistor model; comparing the functional descriptions generated for the set of connected components using the first and second transistor models; identifyi

Abstract: A computer-implemented method for systematically eliminating redundant circuit elements in a state machine of a model having sequential circuit elements possessing one of a fixed number of possible states, typically “0” and “1”. Initially, the sequential circuit elements are sorted into groups whose state is determinate i.e. equal to “0” or “1”. The state of each circuit element whose state is determinate is stored in memory and its next state is calculated and compared with its preceding state. Each circuit element whose successive states are different is moved to the group of indeterminate circuit elements, and the cycle is repeated in respect of all remaining determinate circuit elements until no further circuit elements are moved. Each of the remaining determinate circuit elements is then replaced by a constant equal to its corresponding state i.e. “0” or “1”.

Abstract: A simulation method and a simulation apparatus suppress a parabolic increase in depth angle calculation time to a linear increase at most with respect to an increase in the number of depth angle calculation points on a surface string that represents a processing surface to be simulated. The simulation method and apparatus are applicable to a deposition process that deposits metal such as aluminum on a semiconductor substrate in a vacuum with the use of physical adsorption. The simulation method and apparatus are effective, in particular, to quickly calculate depth angles on a two-dimensional shape to a processing surface to which the deposition process is applied. The depth angles are angles in which particles fly toward the processing surface during the deposition process. The simulation method and apparatus trace a surface string representing the processing surface from the origin to the terminal thereof and find depth angles at all points on the surface string.

Abstract: A method comprising a computational procedure for obtaining reduced-order models of partial element equivalent circuit (PEEC) models of very large scale integrated (VLSI) interconnects. The methodology is not limited to PEEC applications, and can be used for generating reduced-order models of other systems which can be modeled with linear, time-invariant systems of ordinary differential equations with time delays.

Abstract: A methodology is implemented for accurately and precisely computing the output signal times for clock circuit in a data processing system (600) using transistor-level static timing analysis tools which compute delays of blocks or subcircuits that correspond to channel-connected components of transistors. During execution of the Static timing analysis, the predictability of clock signals is recognized and denoted in a timing model (616-622). Furthermore, an actual logical function of the clock circuit is determined during execution of the static timing analysis to provide more precise knowledge of the rise and fall times of the signals provided to the clock circuit.

Abstract: Verification systems which employ automata-theoretic formal verification use a model automaton made from a system process (203) representing the system and a task automaton (205) representing the task and use the model automaton to test (217) whether the language of the system process is contained in the language of the task automaton. An improved technique reduces the computational complexity of the language containment testing by producing a model (216) which represents a system which has been automatically localized with regard to a task. Another technique reduces the computational complexity of stepwise refinement (208). In stepwise refinement, the system automaton is refined a step at a time until it reaches the complexity of a practical implementation. The computational complexity of the stepwise refinement is reduced by a technique which permits language containment to be tested using a set of models made from process-automaton pairs rather than process-process pairs.

Abstract: A system and method for efficiently designing integrated circuits provides a verification manager for verifying an integrated circuit design, a synthesis manager for synthesizing the integrated circuit design, a backend manager for implementing the integrated circuit design, and a processor for simultaneously controlling the verification manager, the synthesis manager, and the backend manager to create the integrated circuit design. The system and method generates a series of regression checkpoints controlled by the verification manager, and a series of timing checkpoints controlled by the synthesis manager to facilitate and expedite the integrated circuit design procedure.

Abstract: Methods and apparatus for performing non-linear analysis using preconditioners to reduce the computation and storage requirements associated with processing a system of equations. A circuit, system or other device to be analyzed includes n unknown waveforms, each characterized by N coefficients in the system of equations. A Jacobian matrix representative of the system of equations is generated. The Jacobian matrix may be in the form of an n×n sparse matrix of dense N×N blocks, such that each block is of size N2. In an illustrative embodiment, a low displacement rank preconditioner is applied to the Jacobian matrix in order to provide a preconditioned linear system. The preconditioner may be in the form of an n×n sparse matrix which includes compressed blocks which can be represented by substantially less than N2 elements.

Abstract: A computer-implemented method and computer program product or software tool for converting a timing graph produced by a static timing engine into a timing diagram and vice versa may be integrated with a static timing analysis tool or may be a stand-alone product. The timing graph is represented by a data structure having nodes that correspond to actual circuit nodes of a circuit simulated by the timing engine and arcs connecting the nodes that correspond to temporal relationships between points on the timing diagram waveforms, such as points at which state transitions occur. To convert a timing graph to a timing diagram, the data structure is traversed from node to node. State transitions are extracted from each node, and temporal relationships between the signals are extracted from each arc. A graphical representation of the timing diagram is then displayed. Alternatively, the timing diagram is output in a suitable file format, such as Timing Diagram Markup Language (TDML).

Abstract: An electromagnetic field intensity computing apparatus for computing electromagnetic field intensity of an electric circuit device in a moment method obtains according to the electric current distribution an electric current of a ground layer and models a transmission line, ground layer, dielectric portion, etc. to be analyzed. When a plate to be analyzed is divided into a plurality of patches, the regularity in given structure data is automatically extracted to compute the mutual impedance among a portion of patches and apply the computation result to other portions. When elements to be analyzed meet the conditions that the electric length of the elements is short and the elements are distant from each other, the mutual impedance can be computed in an approximation obtained under various conditions. Furthermore, approximating a portion near a pigtail portion of a coaxial cable using a polygon allows a vertical electric current to be properly connected to each unit.

Abstract: Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power, and cost goals. Embedded systems are generally specified in terms of a set of acyclic task graphs. According to one embodiment of the present invention, a co-synthesis algorithm, called COSYN, starts with periodic task graphs with real-time constraints and produces a low-cost heterogeneous distributed embedded system architecture meeting these constraints. The algorithm has the following features: 1) it allows the use of multiple types of processing elements (PEs) and inter-PE communication links, where the links can take various forms (point-to-point, bus, local area network, etc.

Abstract: A method, computer system, and a computer readable medium is disclosed for generating triangular meshes for the purpose of performing high-speed generation of triangular meshes with boundary protection layers. One use for the invention is in simulations such as for semiconductor process and device simulations. The invention provides a way to suppress the volume of triangular meshes generated, by limiting the domains that destroy the boundary protection layer, thus, improving the speed of shape analysis. First, shape data is received and then, the next step is defining a boundary protection layer comprising orthogonal meshes matched locally with boundary line segments. After that, mesh points are placed inside domains separated by at least a reference distance from the boundary protection layer.

Abstract: A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die. The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging defective behavior.

Abstract: The present invention relates to a circuit for simulating a break-over semiconductor component, including at least one switch simulating a switching function of the component and at least one voltage or current sensor controlling the switch, the sensor being associated with an adjustable check value corresponding to a characteristic value of the break-over component to be simulated by the circuit.

Abstract: A system and method for memory incoherent verification of functionality of an HDL (Hardware Description Language) design of a computer system component is disclosed. A simulated model of the HDL design receives a memory read stimulus from a stimulus file through a simulated first bus. The simulated model of the HDL design is configured to send its response to the stimulus onto a simulated second bus. A transaction checker receives the response from the simulated second bus and analyzes it to verify operation of the HDL design of the computer system component. The stimulus file and the transaction checker are both stored in the computer system memory. The simulated model's response to the memory read stimulus is evaluated by the transaction checker independently of any previous memory write stimulus from the stimulus file. There is no need to have a previous memory write operation or a master initialization of the system memory for every memory read operation.

Abstract: The invention provides an apparatus and a method for accurately and rapidly estimating a performance of an integrated circuit in the design at a register transfer level. A parsing member converts an HDL description of the integrated circuit at the register transfer level into a representation by using parse trees, and a parse tree allocation member allocates elements of the integrated circuit to respective nodes of the parse trees. A trade-off estimation member predicts a minimum area which can satisfy a timing constraint by applying estimation models stored in an estimation library to the respective elements of the integrated circuit represented by using connections between the elements, and by appropriately changing application of driver models stored in a driver library.

Abstract: A register transfer level (RTL) model is created using an object-oriented programming language. In that RTL model, a logic circuit can be represented by a hierarchy of objects ("modules") each having representation of state elements, input signals, output signals and internal signals. Each object is also provided member functions for initializing, for loading a new state and for generating a next state. These modules are collected in a linked list. In the beginning of simulation, each object is initialized as the linked list is traversed. Then, a consistent next state for the RTL model is obtained by generating a state next based on the initial state. Simulation proceeds by alternately traversing the linked list to load a new state into each module, and traversing the linked list to generate the next state for each module. The step of traversing the linked list to generate the next state of each module may require multiple executions to ensure convergence.

Abstract: Methods and apparatus are described for generating circuit parameters for a plurality of interconnect line circuit models. The plurality of circuit models represent a plurality of interconnect lines in a programmable logic device (PLD). Design description data corresponding to the PLD are generated at least in part from spreadsheet representations of the plurality of interconnect lines. A device model for the PLD is generated using estimated circuit parameters and a plurality of mathematical equations representing the plurality of interconnect line circuit models. Operation of the PLD is simulated using the device model and the design description data thereby generating modeled delay data corresponding to the estimated circuit parameters. The modeled delay data are compared with measured delay data corresponding to the plurality of interconnect lines.

Abstract: A method and apparatus for managing simulation results involve identifying errors within a group of simulation results so that the errors can be recorded into a database and viewed for analysis. In a preferred embodiment of the invention, distinct transactions within a group of simulation results are identified and recorded along with the identified errors. Recorded error-specific data and transaction-specific data are then utilized to graphically display the simulation results such that individual transactions identified within the simulation results are graphically distinct and such that errors occurring during a transaction are visually identified with the transaction. Recording and displaying error information and raising the level of abstraction of simulation results from cycles and signals to transactions enables easier simulation analysis and debugging.

Abstract: A simulation model for a digital system comprises a number of functional units, interconnected by a number of interface units for transmitting messages between the functional units. Each interface unit includes a mechanism for automatically composing and decomposing messages into higher and lower levels of design. The interface thus provides a general mechanism which allows units at any level to communicate with units at any other level, for mixed-level modelling.

Abstract: A method for designing a circuit is described. A block diagram corresponding to the circuit is generated according to an external specification associated with the circuit. Each block in the block diagram has a block specification associated therewith. A design file is generated for each block in the block diagram using the associated block specification and one of a plurality of design file templates. Each block in the block diagram is implemented by editing its corresponding design file. The operation of each block in the block diagram is simulated. A overall design for the circuit is compiled. After the design is compiled, changes are incorporated into the compiled design in response to changes in at least one design file through the use of software links maintained between the compiled design and the design files. A device is then configured according to the compiled design.

Abstract: A semiconductor junction (13) is represented as a junction capacitance (21) in parallel with a junction resistance (23) and junction inductance (22). The junction capacitance, junction resistance and junction inductance are functions of the voltage across the semiconductor junction and are determined using a probability of charge stored across the semiconductor junction. Junction parameters are determined with parameter extraction processes. A circuit simulation tool is used to simulate the performance of a circuit that includes the semiconductor junction. Accordingly, diode junctions are more accurately modeled above their built-in potential and below their reverse break-down voltage.

Abstract: A system and method are described for providing state dependent power consumption characterization data for a logic cell and for minimizing characterization time in a computer controlled power estimation process. The present invention identifies power-equivalent states of the logic cell, and selects one of the power-equivalent states to be characterized. Characterization data produced is then shared among other power-equivalent states. In one embodiment of the present invention, power-equivalent states of a cell are identified by a transition pattern of the inputs and output of the logic cell. Particularly, transitions which result in similar input and output transition patterns are considered power-equivalent states. Because only a single simulation run is carried out for a plurality of power-equivalent states, simulation time is saved significantly.

Abstract: In a logic simulator for simulating a logic circuit described by sentences, each specifying at least one operation and at least two variables which should be subjected to the operation, a model memory memorizes operators for carrying out the operations for the sentences. A variable memory memorizes initial values of the variables for the sentences. A sentence calculating unit calculates one of the sentences as a current sentence at a time to produce a result of calculation by using those of the operators and the initial values which are related to the current sentence. A data or result memory memorizes previous data or initial result values calculated before calculation of the current sentence. The result of calculation is substituted for those of the previous data or the initial result values which are related to the current sentences.

Abstract: Improvements are made to an electronic circuit simulator. The circuit is represented by a set of nodes to which devices and components are connected. In a computer simulator of circuit behavior using the Harmonic Balancing methodology it is desirable to precondition the Jacobian matrix associated with the circuit equations. Proper preconditioning of the Jacobian matrix may increase the computational efficiency of the simulator. A preconditioning matrix for the Jacobian matrix may be obtained by generating an inverse matrix for dissimilar diagonal blocks.

Abstract: Data in a data base that describe a logic circuit are converted to a simulation model, and simulations are performed based on them. When it is desired to change a part of the circuit while a simulation is in progress, a tentative correction is made by directly changing the simulation model without entering logics to the data base again. Simulation is continued based on the changed simulation model, then, after the action has been confirmed, the contents of the change are reflected on the data base. In this way, a circuit can easily be changed while simulation is in progress.

Abstract: A method and apparatus is described which enables a user to analyze an electrical design utilizing a computer. The elements of the electrical design are described at a register transfer level. Embodiments of the invention are described which allow the user to enter the elements described at the register transfer level and estimate the power consumption of portions or all of the electrical design.

Abstract: An efficient method for determining the periodic steady state response of a circuit driven by a periodic signal, the method including the steps of 1) using a shooting method to form a non-linear system of equations for initial conditions of the circuit that directly result in the periodic steady state response; 2) solving the non-linear system via a Newton iterative method, where each iteration of the Newton method involves solution of a respective linear system of equations; and 3) for each iteration of the Newton method, solving the respective linear system of equations associated with the iteration of the Newton method via an iterative technique. The iterative technique may be a matrix-implicit application of a Krylov subspace technique, resulting in a computational cost that grows approximately in a linear fashion with the number of nodes in the circuit.

Abstract: A simulation device comprises an equation generating unit for generating a simultaneous linear equation by application of the implicit integration formula and the Newton iteration method to the description data of an electronic circuit to be simulated, a plurality of block ILU factorization units for performing incomplete LU factorization processing in parallel on each block in a coefficient matrix of the generated simultaneous linear equation, a plurality of fill-in adding units for adding a plurality of fills-in generated by the incomplete LU factorization to a combined portion of coefficient matrices, in parallel, a plurality of line collection ILU factorization units for ILU-factorizing each of several line collections on the combined portion where the fills-in are added, and a convergent solution judging unit for repeating a series of the above processing until convergence of a solution in the simultaneous linear equation generated by the equation generating unit is reached.

Abstract: A method for providing a memory model for simulation which includes the steps of allocating from memory a block of contiguous memory cells, storing a model of memory corresponding to a memory device in the memory, associating the stored model of memory to a corresponding one of the memory cells of the block of contiguous memory cells and, storing a location of the associated one of the memory cells within the model of memory.

Abstract: A system and method for automated design verification. A test bench stimulates a simulated design with test vectors. A coverage analysis tool monitors output data from the simulated design and identifies portions of the simulated design that remain to be tested. A test generator produces and sends test vectors to the test bench which exercise (i.e., test) the portions of the simulated design that the coverage analysis tool has indicated still remain untested. In the method, a first step executes a simulated design on a test bench. A second step interprets the simulated design as if this design were a state diagram composed of a set of basic blocks interconnected by transition arcs. A third step generates test vectors to exercise some of the basic blocks and transition arcs. A fourth step reports the basic blocks and transition arcs which have not been tested. A fifth step generates a new set of test vectors to exercise the as yet untested basic blocks and transition arcs.

Abstract: A method for use in electronic design models encoded into design software for use in SOI based FET logic design includes simulation of an SOI device by and setting a floating body voltage to any desired value at any time during the simulation, by adding to the model an ideal voltage source, whose value is a desired body voltage, in series with an ideal current source, whose value is a constant times the voltage across itself. When the constant is zero, no current can flow, and any additional components have no effect on the circuit. When the constant is non-zero, said ideal current source appears to be the same as a resistor such that current can flow in to or out from the body node, setting its voltage. The constant is kept zero at all times, except when it is desired to change the body voltage. The body voltage can be reset at any time to solve the problem of successive delays in one simulation run and resetting the voltage before each delay measurement starts.

Abstract: A method determines the behavior of a logic cell that receives input signals resulting in a narrow pulse or "glitch." If the pulse width of the output pulse is narrower than a pulse rejection period, the output pulse is rejected and is not propagated to subsequent logic cells connected to the output. The method employs a first internal logic cell model which is assigned an inertial delay function, and a second internal logic cell model which is assigned a transport delay function. In combination, the first and second logic cell models result in an effective propagation delay value, subject to the pulse rejection feature. An exemplary VHDL model is disclosed. A program product embodies a logic cell model in VHDL providing pulse rejection capabilities for output pulses with pulse width smaller than a pulse rejection period.

Abstract: A measuring method for equivalent circuitry is disclosed herein to characterize the interconnects using time-domain reflectometry measurement. By combining the layer peeling algorithm for transmission lines and the matrix-pencil approach for discontinuities, the technique yields a simple equivalent circuit model which consists of distributed transmission lines and networks of lumped elements. With element values being independent of frequency, the model is well suited to model nonlinear broadband circuit simulation for electrical performance of the interconnects.

Abstract: A computer implemented method for simulating a resistive circuit, including a plurality of macro circuits that are arranged hierarchically. The method includes the steps of reading a netlist description of the resistive circuit and recursively traversing the resistive circuit starting from terminal nodes of a macro circuit at a highest level of hierarchy using precharacterizations of each of the plurality of macro circuits to determine node voltages and branch currents of the resistive circuit.

Abstract: A simulation monitor (502) automatically generates a monitor file (510) from a static timer output file (504). The monitor file instantiates a function, a firing equation, that triggers if and only if a critical timing path also triggers. The monitor file is written in a high level language description, suitable for efficient simulation. The test vectors which trigger the firing equation can thereby be monitored and used for hardware test at a later time. The invention may be extended to monitor other conditions of interest.

Abstract: A method and device for automatically verifying results of a simulation is disclosed. External stimuli are applied to a device under test and observed output is generated in response thereto. The observed output is applied to a non-cycle accurate model of the device comprising procedures which simulate significant events corresponding to the significant events of the observed output. Verification conditions are set according to the aspects of the device under test which are being tested and the verification conditions are applied to the output from the non-cycle accurate model. The verification conditions are associated with a procedure of the model such that the verification condition is verified before or after execution of the procedure. In addition, the verification conditions may be executed at the end of the simulation to ensure that all events which should have occur, have occurred.