Abstract: An electrical rule check program takes simulation output files as input and performs an electrical rule check on the simulation to determine if any electrical design rules have been violated. The program scans a simulation output file to produce a subcircuit name list, an instance name list, and an internal index list for each subcircuit. If the number of circuit nodes is less than a first predetermined value, a window limit is set to equal the number of nodes times the number of data points. If the number of nodes is greater than the first predetermined value and less than a second predetermined value, then the window limit is set to equal some first predetermined fraction of the product of the number of nodes and the number of data points.

Abstract: A method is presented for generating functional tests for a microprocessor having several operating modes and features. A test module template file includes a basic set of instructions required to configure the microprocessor to operate in any one of the several operating modes and with any of the several features enabled. A user modifies a copy of the test module template file to form a test module file which provides a desired operating environment and causes the microprocessor to perform a desired activity and to produce a test result. An assembler takes as input the test module file, along with the contents of any library files to be included, and produces both an assembly code list file and a test code file. The assembly code list file is a computer program listing containing assembly language instructions and data.

Abstract: A method is described herein for designing a circuit using graphic editor software. A graphic design file is generated corresponding to a block diagram created in a graphical user interface associated with the graphic editor software. The block diagram includes a plurality of blocks and a plurality of conduits interconnecting the blocks. A block design file is generated in one of a plurality of formats for each of selected ones of the plurality of blocks in the block diagram. Each of the block design files corresponds to an implementation of its corresponding block. Modifications to any of the graphic design file and the block design files are incorporated into each other under software control.

Abstract: A multiprocessor system and method are provided for simulating electrical circuits. The circuit is divided into portions, and separate simulator modules perform a multi-rate behavior simulation, to simulate the performance of respective circuit portions. The simulator modules communicate using block waveform relaxation. Accordingly, the amount of inter-process communication is advantageously low, and the need for backing up digital simulation processes is avoided, providing advantageously fast performance. A system according to the invention is preferably implemented, either physically or logically, in a simulation backplane configuration, having a common connective bus structure, to which multiple active simulation modules are coupled through an interface which is standardized for facilitating block waveform relaxation.

Abstract: When simulating a circuit's behavior, a transistor can be modeled to account for gate resistance induced propagation delay. In one embodiment, the model includes a transistor with a resistor connected to the gate of the transistor. The resistor has a resistance equal to one third of the gate resistance.

Abstract: Multiple test cycles may be randomly generated for simultaneous execution on a design under test using a simultaneous random cycles test generator. One form of the test generator is hardware description code run on a simulator. The test generator provides multiple random cycle description generators. A random cycle description generator randomly generates a particular test cycle at runtime using constraints provided by the test generator. A random cycle description generator granted access to a serial common cycle initiator may initiate random test cycles through the common cycle initiator. The common cycle initiator may execute the randomly determined test cycle or define and arm a cycle executor of a plurality of cycle executors to execute the randomly determined test cycle. While one random test cycle is executed, another random cycle description generator is selected to initiate another random test cycle on the common cycle initiator.

Abstract: Very high speed circuits are adversely effected by parasitic capacitances and line resistances. At high speeds these values of capacitance and resistance change with frequency. A method of verification of the design of high speed circuits includes a simulation of the effects of these changes in resistance and capacitance which occur at high frequency. There is a logic component and a physical-layout component which are combined to provide a full simulation of the circuit taking into account these effects which occur at very high frequency. The physical-layout component utilizes Maxwell's equations in their entirety without removing the time dependent effects. One embodiment considers only cases defined by the bus protocol, reducing the computational penalty of complete electromagnetic simulation.

Abstract: Process simulation for LSIs and other semiconductor devices will handle plural same impurities introduced in different processes as different impurities. Thus, by handling them as different impurities in calculation, it is possible to obtain the distribution profiles of impurities in semiconductor devices without being effected by another same impurity introduced in another process or a number of processes during processing. With this, even a plurality of process conditions are discussed or when one or some of process(es) in a sequence of semiconductor device fabrication processes is (are) changed in procedure, it is not necessary to repeat the process simulation many times from the beginning. And it is possible to easily decide which process must be changed in conditions based on a finally obtained structure of semiconductor devices.

Abstract: A logic circuit simulation device comprises a connection analyzer for detecting circuit connection data from an input logic circuit description, an asynchronous element detector for detecting an asynchronous element in the input logic circuit description, a grouping area determination section for determining a grouping area in the logic circuit from which the asynchronous element is excluded, a grouping section for executing grouping for the determined grouping area, and a simulator for simulating operation of a logic circuit on the basis of the logic circuit having undergone grouping. This prevents a single event execution unit from being repeatedly executed within one simulation cycle. Since signal processing associated with the transfer of values between event execution units is replaced with variable processing, high-speed processing can be performed.

Abstract: Operation cycles to be subjected to an IDDQ test are selected from among operation cycles defined by a test pattern for a functional test of a CMOS integrated circuit so that a sufficient and necessary number of operation cycles are accurately and rapidly selected. A combination of sets of m-bit data are selected so that the combination includes sets of m-bit data each bit of which is changed from one of the values "0" and "1" to the other at least once. The operation cycles corresponding to the sets of m-bit data included in the combination are rendered to be the IDDQ test cycles to be subjected to the IDDQ test.

Abstract: A method and apparatus for detecting floating transistor gates within a netlist model of an integrated circuit is disclosed. All transistor gates and input nodes coupled to the transistor gates are identified. These input nodes are then used to generate a resistor card. The resistor card is used in conjunction with the original netlist during simulation to couple two resistors to each input node. The first resistor is coupled between the input node and a high potential, and the second resistor is coupled between the input node and a lower potential. The resistors may be configured to have equal resistance values. The resistance values may be large enough to ensure that the current conducted through the resistors will be minimal in relation to the currents in the circuit when the input node is not floating. The resistance values may be small enough to overcome any leakage currents present in the circuit.

Abstract: A method and system for predicting the sensitivity of the integrated circuit logic cell timing performance to variations in voltage and temperature. Rather than using the prior art approach of multiplicative derating factors to model voltage and temperature effects on timing performance, adders are used to model the change in performance due to variations in operating conditions (i.e., voltage and temperature). The adders are treated as functions of input transition time (Tx) and output load capacitance (Cload). The change in performance as measured in time forms a plane over the Tx-Cload operating range for variations in either voltage or temperature. The adders, using a plane equation as a function of Tx and Cload, greatly improve the absolute accuracy in predicting the effects of variations in voltage and temperature, as compared to using the prior art methods involving multiplicative derating factors.

Abstract: A process (20) and design tool (62) are presented for the accurate prediction of design parameters (42) for components (38) of an integrated circuit (22) during the early stages of the design of that integrated circuit (22). These predicted design parameters (42) include pin count parameters (50), propagation delay parameters (52), layout area parameters (54), dynamic power parameters (56), static power parameters (58), and total power parameters (60). With these parameters, the designer interactively modifies the design prior to the layout and prototyping of the integrated circuit (22). The dynamic power parameters (56) and total power parameters (60) may be repetitively predicted with differing input items to establish a power usage pattern for the integrated circuit (22).

Abstract: A method of designing an integrated circuit employs hardware testing rule checking so as to ensure hardware testability and to ensure that automated test program generation will succeed when the design cycle reaches that stage. The method calls for, first, receiving a proposed logic design defined at a functional or behavioral level; second, defining a test bench for simulating operation of the logic design, the test bench including at least one input vector for stimulating the logic design for verifying the operation of the logic design; receiving a predetermined set of one or more hardware testing rules associated with a target tester; simulating operation of the logic design using the test bench; and, prior to releasing the logic design for logic synthesis, checking the simulation for compliance with the hardware testing rule set. Preliminary checking of the design and test bench prior to synthesis can avoid costly corrections later in connection with test program generation.

Abstract: An arrangement for designing a testing modeling system provides a testing hierarchy, where non-standard device elements having internal memory and logic structures are modeled by partitioning the device element into a recognizable memory model and a recognizable logic model separate from the memory model. The segregated models are then verified for accuracy using existing design and simulation tool and with comparison to existing hardware implementations. Once the revised models have been verified, the new models can be stored in a model library for future use.

Abstract: One aspect of the invention relates to a method for improving timing convergence in computer aided semiconductor circuit design. In one particular version of the invention, the method includes the steps of generating a behavioral model of a desired semiconductor circuit, which includes timing constraints for individual paths in the circuit, synthesizing the behavioral model to produce a netlist which represents an implementation of the desired semiconductor circuit mapped to a specific semiconductor technology, the netlist including a list of components in the circuit and a list of nets which connect the components in the circuit, and the step of synthesizing includes performing a timing analysis on the implementation so that the paths in the circuit represented by the netlist meet the timing constraints, the timing analysis being performed using estimated wire lengths for the nets. Next, the components in the netlist are placed into an image representing a predefined area of the semiconductor chip.

Abstract: A total impurity concentration which is a result of the solution of a diffusion equation at the immediately preceding point of time is used to solve, for each mesh point, an equation for determining an electrically active impurity concentration to approximately determine an electrically active impurity concentration. A ratio between the approximate value of the electrically active impurity concentration and the total concentration of the impurities at the preceding point of time is determined for each mesh point. A value of the ratio is determined by interpolating values at mesh points at the opposite ends of each mesh branch. A diffusion equation which includes the total concentration of the impurities as a variable and employs an effective diffusion constant is solved to determine a total impurity concentration at the present point of time of analysis.

Abstract: An algorithm (20) or method (20) for verifying that a system hierarchically built from smaller components implements a desired equation that represents the system. Symbolic data is clocked (24) through the system by processing a symbolic test vector using linked equations (22) written (21) for each component of the system. A resulting symbolic equation generated at the output of the system is recorded (25). The symbolic equation is then compared (26) with the desired equation for the system using a symbolic manipulation tool. If the comparison generates a zero difference, the system correctly implements the desired equation representative of the system, and vice-versa.

Abstract: An electronic circuit verification system and method includes an HDL circuit simulator and a circuit simulation verifier that pass control back and forth between each other, and that cooperate so as to perform circuit verification tasks than would be very difficult to perform using only the HDL circuit simulator. The circuit simulation verifier executes a test bench so as to define operational correctness and/or performance criteria, including at least one Expect Event, each Expect Event comprising a combination of one or more signal values that are expected to occur during simulation, and a time frame during which the signal value combination is expected to occur. The circuit simulation verifier includes instructions for blocking execution of a thread of execution associated with the test bench until the earlier of the combination of one or more signal values occurring during simulation and the time frame expiring.

Abstract: Speed, size, and power trade-offs of a VLSI combinational circuit are optimized through iterative restructuring. First, timing analysis for the circuit is performed (102) to find the critical path through the circuit (104). Then, a gate is selected from the critical path (106), and a window is contracted around the gate (108). Within the window, alternate structures are constructed (110) and sized (112). The best alternative is substituted into the window (114), and the new circuit is resized (116). If the new circuit is not an improvement over the old (118), then the original window is replaced (120). In any case, this is repeated for each gate in the circuit (124). The entire process is then repeated until either user constraints are met, or the circuit doesn't change (122).

Abstract: In a delay-power-source-coefficient determining step, a drain saturation current in a P-channel MOSFET is calculated on the basis of specified operating power-source voltage data and of saturation-current parameters such as the mobility of carriers and the thickness of a gate oxide film based on said specified operating power-source voltage data. Thereafter, a ratio of a drain saturation current in the P-channel MOSFET when a reference power-source voltage is applied thereto to the drain saturation current in the P-channel MOSFET when an operating power-source voltage is applied thereto, thereby determining a delay power-source coefficient. Next, in an effective-delay calculating step, effective-delay calculating means multiplies a delay time when the reference power-source voltage calculated by the delay calculating means is applied thereto by the delay power-source coefficient calculated by delay-power-source-coefficient determining means to determine a delay time at the operating power-source voltage.

Abstract: In a circuit simulation method, circuit information of an electronic circuit to be simulated is inputted, and whether or not a linear circuit element circuit included in the electronic circuit is passive, is discriminated. For this discrimination, an inductance matrix of the electronic circuit is prepared, and, before a circuit analysis by a circuit simulator, whether or not the inductance matrix is a positive definite is discriminated by obtaining and checking the value of minor determinants of the matrix, and by determining that the circuit is passive if the values of the diagonal items in the matrix are positive definites, and that the circuit is not passive if at least one of the values of the diagonal items in the matrix is not a positive definite. In the latter case, from information of the minor determinants, additional information indicating a cause for non-passivity is derived and outputted.

Abstract: A method, apparatus and system for simulating the operation of a circuit using a computer-based simulator comprising: (a) distributing at least one signal upon to one or more simulation model subcircuit functions, which use the signal, upon a change in the signal; (b) scheduling one or more subcircuit functions that use the signal for execution according to a priority assigned to each subcircuit function; and (c) providing an output value to the simulator when no subcircuit functions are scheduled, otherwise, executing one or more subcircuit functions with the highest priority and returning to step (a) to repeat the process.

Abstract: A computer system including a memory model of a memory circuit. The computer system comprises a processor coupled to receive and manipulate the memory model, and a memory including the memory model. The memory model includes: a number of address bits corresponding to a number of address bits of the memory circuit; a number of data bits corresponding to a number of data bits of the memory circuit; and a memory type parameter corresponding to a type of the memory circuit.