Abstract: An IC design computer simulation tool is provided with a design reader equipped to assign device characterizations to electronic devices of an IC design, and model evaluators equipped to adaptively perform model evaluations in accordance with the electronic devices' assigned device characterizations. In one embodiment, the electronic devices include transistors, and the adaptive model evaluations provide evaluated model quantities to support solution of the circuit node voltages using fully coupled (implicit) or partially decoupled (explicit) solution techniques. In particular, the transistor capacitive coupling currents are expressed according to the assigned device characterizations.

Abstract: A system and method for designing a low power ASIC using weighted net toggle information. In particular, the system and method includes a simulation system that executes a set of application test suites that is representative of the code that will likely run on the ASIC and weights each of the applications. The weighted net toggle information can then be evaluated and utilized to modify the ASIC design.

Abstract: Metalization structures are modeled by employing a basis function decomposition process for modeling the charge and/or current distributions and the interactions of those distributions on metalization structures arising from voltages and currents flowing in the metalization structures. Then, the charge and/or current distributions and their interactions are employed to obtain the electrical characteristics of a metalization structure. In one embodiment of the invention, representative sub units of the metalization structure are selected, the charge and current distributions are determined in those representative sub units, the self and mutual interactions are determined of those sub units and, then, those self and mutual interactions are used as an initial solution to describe all interactions between similar metalization sub units in the overall system of metals. These interactions are then employed to determine the impedance and admittance of each of the sub units.

Abstract: A process for synthesis and rough placement of an IC design. Initially, a synthesis tool is used to generate a netlist according to HDL, user constraint, and technology data. Each of the wires of the netlist is initially assigned a unit weight. Thereupon, a cell separation process assigns (x,y) locations to each of the cells based on the weights. The wires are then examined to determine their respective performance characteristics. The wires are iteratively re-weighted, and the cells moved according to the new weightings. Next, the cell location information is supplied to the synthesis tool, which can then make changes to the netlist thereto. In the present invention, the size of each of the gates can be either scaled up or down accordingly. Again, the nets are iteratively examined and their weights are adjusted appropriately. The cells are spaced apart according to the new weights.

Abstract: A method and apparatus for calculating circuit delay times efficiently arranges and stores data to reduce system memory requirements, which allows computers without large storage devices, such as conventional personal computers with limited hard disk space, to be used for testing preliminary device designs, Delay time ratio coefficient values representing a ratio of a delay time determined by values of dependency factors having a large correlation with one another to a predetermined reference delay time of a circuit element are stored in a coefficient table. The dependency factors include process condition, in use or operational temperature, and first and second operational supply voltages.

Abstract: The coverification system includes a reconfigurable computing system (hereinafter “RCC computing system”) and a reconfigurable computing hardware array (hereinafter “RCC hardware array”). In some embodiments, the target system and the external I/O devices are not necessary since they can be modeled in software. In other embodiments, the target system and the external I/O devices are actually coupled to the coverification system to obtain speed and use actual data, rather than simulated test bench data. The RCC computing system contains a CPU and memory for processing data for modeling the entire user design in software. The RCC computing system also contains clock logic (for clock edge detection and software clock generation), test bench processes for testing the user design, and device models for any I/O device that the user decides to model in software instead of using an actual physical I/O device.

Abstract: A system and method for using a computer system to determine the desired decoupling components for stabilizing the electrical impedance in the power distribution system of an electrical interconnecting apparatus, including a method for measuring the ESR for an electrical device, a method for determining a number of desired decoupling components for a power distribution system, and a method for placing the desired decoupling components in the power distribution system. The method creates a model of the power distribution system based upon an M×N grid for both the power plane and the ground plane. The model receives input from a user and from a database of various characteristics for a plurality of decoupling components. The method determines a target impedance over a desired frequency range. The method selects decoupling components. The method determines a number for each of the decoupling components chosen.

Abstract: A system and method for generating inline subcircuits that enable a circuit designer to model and simulate circuits that when compared to conventional system and methods reduces the hierarchy from the perspective of the circuit designer, more efficiently models parasitic components, more efficiently parameterizes device models, more effectively creates models that are compatible with other simulation tools, can change the interface of a component without requiring the designer to use an extra layer of hierarchy, provides a more efficient interface by hiding details from the designer, enables hidden monitors and other functional designs to be automatically simulated by hiding these functions from the designer in a design level that is below the design level that is of interest to the designer, such as the geometrical parameter design level, can perform general purpose model binning with automatic selection, can export models and model parameters to other hierarchies without requiring an additional hierarchy in

Abstract: A system and method for analog and digital mixed mode simulation. The system and method simulates analog mixed signal (AMS) systems coded in one or a plurality of hardware description languages (HDLs) that describe digital subsystem, analog circuits, and mixed signal interface components. It implements and simulates AMS circuits using any standardized and specialized type of application programming interface (API) called a HDL programming language interface (PLIs). In it preferred embodiment, the system and method simulates systems coded in the popular Verilog-AMS HDL and legacy Spice HDLs. Utilization of the PLI allows for a much simplified and improved AMS simulation because the mixed mode engine implemented using the PLI invokes any commonly available digital simulator(s) for the digital engine(s) and any commonly available analog solver(s) for the analog engine(s).

Abstract: Electronic circuits and systems which include digital and analog circuit sections are simulated with a combination of analog and digital simulation. For the interface matching of the two types of simulation, there is used, between a connection of an analog-simulated circuit element and a connection of a digitally simulated circuit element, a transport element for transporting current values between the circuit elements.

Abstract: When a logic synthesis of verified logic circuits is executed by a logic synthesis section, respective input variables, main terms, a minimum logical-OR form, and a cover condition of a logical expression are retained as reusable elements. In an optimization of a program code executed by a dedicated compiler, the program code is optimized by using the reusable elements. Thus, the processing time for the optimization of the program code can be shortened, and also, the amount of memory being used can be reduced.

Abstract: Cellular encoding using typed development operators in which basic types are determined for the basic components of a structure being developed. Each development operator for developing the structure is associated with one or more of the basic types. Organisms are generated using tree arrangements of the development operators by matching the basic types associated with connections among the development operators in the trees. The matching among typed development operators reduces the likelihood of creating unfit organisms. Cellular encoding with typed development operators may also be used to evolve the structure.

Abstract: According to a first model of an operation of circuitry, a first set of estimates of the operation is generated in response to a set of conditions, including a first estimate of the operation in response to a first condition. According to a second model of the operation, a second set of estimates of the operation is generated in response to the first condition and the first set. In response to a comparison between the first estimate and the second set, a subset of the first set is selected. According to the second model, an estimate of the operation is generated in response to a second condition and the selected subset.

Abstract: A unique transistor model and methods for analyzing the model are disclosed. The transistor model of the present invention is simple and requires specification of a minimal number of parameters to simulate transistor operation. Three analysis methods are disclosed, each having unique circumstances for application A first method is premised on sampling all waveforms in the circuit and determining the operating point of the transistor. The first method assumes an input of an arbitrary periodic waveform. The first method is very flexible and may be used with a wide range of models other than the disclosed model. A second and a third method are premised on input and output waveform clipping. The second method assumes a single tone input into the transistor. The third method is a combination of features from the first and second methods. The third method is computationally efficient and assumes an arbitrary periodic input waveform.

Abstract: A device for reducing evaluation time of a matrix representing an electrical circuit. Conductance values of each circuit component in the circuit are written to corresponding models utilizing non-blocking writing techniques. The matrix is represented by a reduced memory structure where each matrix node is represented by a matrix element structure having at least one pointer to a conductance value contained in a model structure corresponding to a circuit component that contributes to a value of the matrix node. A set of rows or columns of the matrix are then processed to calculate final matrix node values independently.

Abstract: A plurality of serially coupled circuit cells (12-20) are modeled as a distributed serial load. The distributed serial load provides an accurate load model in situations where one cell is effected by loading on subsequent circuit cells, i.e. downstream loading is conveyed back to the first cell. The capacitance (22) and resistance (24, of each cell has a loading effect on each previous cell. The effective resistance and capacitive values of each cell is identified and maintained as one element of the distributed serial load model. The distributed serial load accurately models the loading of unbuffered cells (16-20). The distributed serial load is also applicable to portions of circuit cells (38,40) that are not be buffered and where the downstream loading has an effect on previous circuit drivers (14).

Abstract: A method reduces circuit data to be simulated, by extracting element data that influences a result of simulation out of the circuit data, thereby shortening a simulation time while maintaining the accuracy of simulation. Also provided is a simulation method that employs the reduction method. The method includes the steps of entering one of an input vector and/or an observation point for the circuit data to be simulated, and extracting an element data corresponding to a node influenced by propagation of a varying state of the input signal, the varying state for the node having an influence for the observation point, from the circuit data according to the input vector and/or observation point. The extracted nodes and elements related thereto are used to prepare reduced circuit data that is simulated. The method reduces the scale of a circuit to simulate by extracting only essential elements that affect a result of simulation from circuit data such as a netlist that forms the circuit to be simulated.

Abstract: A system for characterizing multiple power-supply circuits includes a computer. The computer characterizes energy attributes of a circuit that includes a cell. The cell couples to a plurality of power supplies and has one or more outputs that drive, respectively, one or more loads. The computer uses a model of an operation of the circuit to characterize a dynamic energy attribute of each of the plurality of the power supplies. The computer further uses the model of the operation of the circuit to characterize a dynamic energy attribute of the one or more loads. The computer calculates calculate an overall dynamic energy attribute for the plurality of power supplies by summing together the dynamic energy attributes of the plurality of the power supplies. The computer determines an overall dynamic energy attribute for the one or more loads by adding together the dynamic energy attributes of the one or more loads.

Abstract: A system and method perform a two-pass fault simulation on an original design representation including a software-modeled design element and a hardware-modeled design element. Logic simulation generates input stimulus for a port on the boundary of the software-modeled design element and the hardware-modeled design element, where such ports are output ports of the software-modeled design element and input ports of the hardware-modeled design element. The input stimulus is merged with test patterns for the original design representation. A modified design representation is generated by replacing the software-modeled design element with a nonfunctional block. Most or all possible faults in the hardware-modeled design representation are seeded. The modified design representation is fault simulated in a first pass using the merged input stimulus and test patterns.

Abstract: The present invention is a simulation test program that incorporates a formatter which asks the simulator what, if anything has changed, rather than querying for all of the pin states and strengths at each iteration, i.e. at each time stamp. If nothing has changed in the current time stamp, then the time stamp is increased until a change which has occurred in the states of the pins is detected. Then the particular change is evaluated. This drastically reduces the runtime, memory usage, and output file size of the simulations.

Abstract: A communication network design circuit can derive a path and a necessary link capacity for multiple point communication service permitting arbitrary communication within a predetermined range of communication amount by providing traffic amount of data in-flowing through an ingress node and traffic amount of data flowing out through an egress node. The communication network designing circuit has setting means for setting a mathematical programming problem for deriving the multiple point communication service and optimizing means for solving the mathematical programming problem set by the setting means and obtaining the path for the multiple point communication service.

Abstract: Hardware description language (HDL)-centered design system and methodology uses HDL specification effectively as master depository for design intent or knowledge. Through network browser, designers conveniently navigate or explore design graphically. Designers selectively review or save design in entirety or portions. Design capture, analysis, and manipulation are based on HDL specification, either directly through text file editing, or indirectly through use of graphical tools.

Abstract: A method of and device for simulation which represents variations in electrical characteristics (Idsat, Vth and the like) of a device constituting a semiconductor integrated circuit in the form of a corner model including corners defining the limits of the variations is provided. A circuit simulation is performed to determine device parameter sensitivities which are the derivatives of the electrical characteristics with respect to device parameters such as &Dgr;L, &Dgr;W, Tox and Vth0. Variations in the device parameters at each corner are determined by applying the device parameter sensitivities and the values of the electrical characteristics required for each corner to the normal equation of the linear least squares method. The method and device can determine the values of a set of device parameters at each corner without the need to repeat the circuit simulation and can uniquely determine the values of the set of device parameters.

Abstract: An automated design process and apparatus for use in designing complex structures, such as circuits, to satisfy prespecified design goals, using genetic operations. The present invention uses a population of entities which may be evolved to generate structures that may potentially satisfy the design goals. The behavior of such generated structures is evaluated in view of the design goals, and those structures more closely meeting the design goals are evolved further until a structure is generated that either meets the prespecified design goal or some other process completion criteria. In this manner, a design complex structure may be obtained.

Abstract: In this semiconductor process device simulation method, a coefficient matrix constituted by a principal diagonal submatrix arranged at any one of principal diagonals corresponding to each mesh point and representing a self feedback function at the mesh point, the principal diagonal submatrix having rows and columns in numbers corresponding to the number of mesh points, and a non-principal diagonal submatrix arranged on any one of a row and column passing through principal diagonal positions corresponding to the mesh point and representing an interaction between the mesh point corresponding to the principal diagonal positions and an adjacent mesh point connected to the mesh point through a mesh branch is generated. Calculation for the submatrices is performed while regarding each submatrix of the coefficient matrix as one element, thereby performing incomplete LU factorization of the coefficient matrix.

Abstract: The apparatus includes the wiring-model generation section that generates a wiring model in accordance with high-frequency-circuit design information; the random-pattern analysis section that generates and analyzes a dummy random-pattern waveform for transmitting a wiring model in accordance with a command including the bit information of a random-pattern waveform and a differential waveform corresponding to the dummy random-pattern waveform; and the skew analysis section that skews a random-pattern waveform or differential waveform in accordance with a preset skew width.

Abstract: A set of worst-case device model files is provided for a production process used to mass-produce integrated circuits having a plurality of primitive device model types. A statistical device model for the production process is derived directly from the worst-case files.

Abstract: The present invention makes it possible to obtain an aging deterioration margin amount including an allowance for aging deterioration in a simplified manner. Moreover, in order to allow an appropriate inspection taking aging deterioration into account, a delay deterioration rate predicting part 101 outputs signal path delay information before deterioration 302 and signal path delay deterioration rate information 303 for each signal path, based on LSI design information 301. A delay vs. delay deterioration rate analyzing part 102 outputs delay vs. delay deterioration rate relationship information 304 showing the correlation between the delay and the delay deterioration rate based on the information. A delay deterioration rate extracting part 103 extracts a delay deterioration rate of a predetermined signal path and outputs it as delay deterioration margin 305.

Abstract: A method and system for identifying an inaccurate model of a hardware circuit includes the steps of simulating a digital model and an analogue model of the circuit to provide first and second sets of simulation results respectively. For each result in the first and second sets of simulation an integer value is determined which represents that result. The integer values are stored in first and second sets of comparison results respectively and the sets of comparison results are compared. An output signal indicating that at least one of the models is inaccurate is produced if the comparison results contradict.

Abstract: A method and system for generating reduced models of systems having a time-varying elements, a non-linear elements or both is provided. The system and method can be utilized with any systems that are capable of being described with non-linear or time-varying differential equations. The method and system are especially useful for automated extraction of reduced models for nonlinear RF blocks, such as mixers and filters, that have a near linear signal path but may contain strongly nonlinear time-varying components. The models have the accuracy of a transistor level nonlinear simulation but are very compact and so can be used in system level simulation and design.

Abstract: The invention provides a knowledge management system particularly suited for use in the integrated circuit design environment. The system allows administrators to define standardized component types. Instantiated components versions comprise “deliverables” and “attributes.” Deliverables comprise a file or directory of files or groups of files or directories that perform a common function and are characterized by the system in a standardized manner. Attributes comprise metadata describe the component version. By the abstraction of design files into deliverables, the systems can work with design files originating from any source and having different structures and still make those design files available by other designers in a uniform manner for efficient reuse of pre-qualified components. Tasks in the design flow can be tracked in the system. The system may also include a communications application, an issue tracking application, and an audit trail application.

Abstract: An improved hardware circuit simulation method in particular for history-dependent and cyclic operation-sensitive hardware circuits, like SOI-type hardware, checks for correct cyclic boundary conditions by performing a first run of a DC simulation with input voltage conditions belonging to CYCLE START, and by carrying out a second DC simulation with input voltage conditions belonging to CYCLE STOP. After comparing the results, e.g., comparing the node voltages, any mismatches can be determined which serve as a hint to non-compatibility with cyclic operation. Thus, the design is able to be re-designed before being simulated in vain with a great amount of work and computing time. A transient simulation can be appended for automated correction of dynamic errors.

Abstract: An adjoint network method is used to determine the sensitivity of an electronic circuit model to variations in circuit components. The effects of nonlinear circuit elements are represented by augmenting the elements of the adjoint network. In particular, deviations away from linearity are represented in the original circuit by “fictitious” voltage sources. These voltage sources will map into “fictitious” current sources in the adjoint network. These sources are not static; they are directly proportional to the adjoint current through the branch corresponding to the nonlinear element. As such they may be classified as current-controlled current sources and are sometimes referred to as “correction” sources.

Abstract: A back annotation apparatus, which effectively carries out a back annotation, includes: a pre-layout simulation implementing part for detecting nodes of which the potential changes when a predetermined signal is applied to a logic circuit; a layout pattern verification implementing part for implementing a predetermined layout pattern verification for layout patterns of the logical circuit; a parasitic element extraction part connected to the pre-layout simulation implementing part which extracts parasitic elements from the nodes of which the potential changes; a net list generation part connected to the parasitic element extraction part for generating a net list which includes all the devices included in the layout pattern data and parasitic elements extracted in the parasitic element extraction part; and a post layout simulation implementing part connected to the net list generation part for implementing a post layout simulation by using the net list.

Abstract: A circuit simulating apparatus includes a netlist extracting unit extracting a netlist from circuit diagram data, an unnecessary circuit disconnecting unit forming a netlist with an unnecessary circuit disconnected, from the netlist extracted by the netlist extracting unit, based on an unnecessary circuit disconnecting terminal designated by an unnecessary circuit disconnecting terminal designating unit, and a circuit simulation unit performing a circuit simulation using a simulation input file formed by using the netlist with the unnecessary circuit disconnected. As the circuit simulation is performed using the simulation input file formed from the netlist with the unnecessary circuit disconnected, the time necessary for the circuit simulation can be reduced.

Abstract: A first supply voltage is applied to a computer-controlled apparatus and to a first block of a simulator, while a second supply voltage is applied to a designator unit and to a second block of the simulator. The operation of the computer-controlled apparatus is simulated by the simulator in response to instruction signals supplied from the designator unit.

Abstract: An electric wiring simulation device 1 of the present invention includes an input device 2; a display 5; a characteristics information data base 4 storing parts information on parts and wirings, discharge characteristics of a power supply, current-prearcing time characteristic, of protecting parts and current-smoke time characteristics of the wirings; 4n assigned path searching unit 11 searching an assigned path between a;short-circuit point and the power supply On a test object circuit; a current value calculating unit 12 calculating a resistance value on the assigned path based on the parts information, and calculating a short-circuit value based on the resistance value and the discharge characteristics of the power supply; and a judging unit 13 judging whether or nor each protecting part is fused or etch wiring smoke., based on the current-smoke time characteristics and the current-prearcing time characteristics, at unit time intervals.

Abstract: Testing and validation of custom IC designs is performed using standard ICs. Highly complex integrated circuits, instead of being designed at the gates and flops level, are typically designed using standardized cell libraries that allow for widespread, systematic design reuse. Such libraries may include Functional System Blocks, or FSBs (sometimes referred to as ASIC cores), and Application Specific Standard Parts (ASSPs). ASSPs are designs that are or were once realized as stand-alone parts, but that may also be embedded into larger designs (“embedded ASSPs”). Instead of a conventional software model, testing and validation is performed using a hardware model of a custom integrated circuit. The hardware model may be a breadboard system that is decomposed into three levels of functionality: ASSPs, FSBs and “glue logic”ASSPs are typically 500K gates or more and may be realized as separate ICs. FSBs are typically 50K gates or less.

Abstract: An apparatus and method for determining power consumption in logic devices including mixed static and dynamic logic blocks is implemented. Input logical signals are tagged as having dynamical behavior or static behavior, and the power consumption of the logic block determined according to the behavior of the input signal. If an input signal has dynamic behavior, an output signal making a transition in response thereto will make two transitions per clock cycle, and the per cycle power consumption of the logic block is accordingly weighted. In another embodiment, a Boolean behavior signal is calculated for each block from clock phase tags and “one cycle per cycle” circuit level simulations. The per cycle power consumption of each logic block receives a weight in response to the Boolean behavior signal, according the behavior of the block characterized thereby.

Abstract: Register transfer level (RTL) source code is synthesized to generate a gate-level representation and to generate instrumentation logic corresponding to one or more statements in the RTL source code. The instrumentation logic comprises logic circuitry in addition to that of the gate-level representation. The instrumentation logic indicates an execution status for the corresponding RTL statement(s) during gate-level simulation.

Abstract: A CDM simulator for a magnetic recording head can be used for the in situ testing of such heads and also for electrical and/or magnetic characterization. The recording head is disposed in the simulator adjacent a discharge plate of an electrically conductive material with a dielectric layer disposed therebetween. The recording head is resistively coupled to a ground potential. A stored charge is injected into the discharge plate. When the charge is injected, a current transient similar to electrostatic discharge, is developed through the magnetic recording head.

Abstract: A method for evaluating and correcting a model of an electronic circuit. A list is created which comprises the minimum number of components that must be specified by the operator in order to be able to compute values for the remaining circuit components. Correction of circuit models can be performed even in cases of limited accessibility to the circuit's nodes.

Abstract: A function for verifying the behavior of a digital system, where the digital system can exhibit several differing but valid behaviors from the same input. Identical input vectors are applied to both a hardware model and hardware emulator of the digital system via a simulator. Simulating the hardware emulator generates one or more predicted output vectors, while simulating the hardware model produces a single output vector. The output vector of the hardware model is then compared with the one or more predicted output vectors of the hardware emulator. If there is not an output match, an exception is raised. If the output vector of the hardware model matches one of the predicted output vectors of the hardware emulator, a rules checker applies a set of context specific rules defining a valid behavior to the current matching output vector, the internal model state information from the hardware emulator, and a history file of previous output vectors.

Abstract: A graphical bitmap image of a scanned test pattern drawing is transformed into a test file in a file format that is readily usable to provide stimuli for computer-aided design (CAD) tools or integrated circuit (IC) testing equipment. A bitmap image of each page of the test pattern drawing is produced as a graphical image of the rows and columns of test pattern data. Non-essential drawing symbols are then removed from the bitmap image, such as the lines used to draw the table. Essential test pattern information is recognized and is converted into a machine readable format by first storing the data in a tabular format having rows and columns which correspond to the rows and columns of the test pattern drawing. The stored test pattern data is then integrated with a machine readable file format which is adaptable to the CAD and IC tool in order to produce the machine readable test file.

Abstract: The simulator is provided with a control section that gathers the parameters of a plurality of parts in a computer network and that thereby predicts a future state of the computer network over a prescribed period of time. Further, a scenario creation/management creates a model corresponding to the computer network. Finally, simulation engine executes the simulation on the basis of the created model.

Abstract: A system and method for simulating a networked system for testing of embedded software on an emulated hardware device. The system provides for automated generation of a simulated hardware and facilitates testing of embedded software response to simulated error conditions created by the simulated hardware. Communications from the embedded software are intercepted at a low software level and redirected from the emulated hardware device to the simulated hardware.

Abstract: A method and system for co-verifying a hardware simulation of a field-programmable-system-level integrated circuit (FPSLIC) and a software simulation of the field-programmable-system-level integrated circuit. A FPSLIC device is simulated in hardware, and a simulator-port layout of the FPSLIC device is generated. In software, the method separately simulates, with an instruction-set simulator, the FPSLIC device, and outputs register contents from the instruction-set software. The contents from the simulator-port layout are verified with the register contents. Additionally, the method may further include outputting peripheral contents from the instruction-set simulator, and verifying contents from the simulator-port layout with the peripheral contents. UART contents also may be outputted from the instruction-set simulator, and verified with contents from the simulator-port layout with the UART contents.

Abstract: A computer implemented method for performing testing of a computer model of an integrated circuit design is disclosed. The method includes initially generating a first AVF test file for a first integrated circuit design having slow characteristics. Then, the method proceeds to generate a second AVF test file for a second integrated circuit design having fast characteristics. Once the two AVF test files are generated, the method proceeds to comparing test file parameters from the first AVF test file and the second AVF test file. Based on the comparisons, the method proceeds to generate a modified AVF test file that replaces miscompares (i.e., cycle slips) between output signals of the first and second AVF test files with don't care values. The method also includes options for performing pin margining. The pin margining operations are configured to make modifications to the AVF test files in order to compensate for expected physical test station adjustments.

Abstract: According to a first model of an operation of circuitry, a first set of estimates of the operation is generated in response to a set of conditions, including a first estimate of the operation in response to a first condition. According to a second model of the operation, a second set of estimates of the operation is generated in response to the first condition and the first set. In response to a comparison between the first estimate and the second set, a subset of the first set is selected. According to the second model, an estimate of the operation is generated in response to a second condition and the selected subset.

Abstract: A method, system and computer program product for automatically determining optimal design parameters of a subsystem to meet design constraints. The subsystem comprises a plurality of circuits. The optimal design parameters are determined by performing a parameter-delay curve optimization of the subsystem design parameters. Specifically, an embodiment of the present invention provides a method and/or computer program product for determining optimal values for the design parameters of a circuit block, which result in optimally assigned delay targets for datapath blocks at the minimum power/area point. The problem/solution space is extended to solve the problem of figuring out the best possible implementation, for example, static vs dynamic, for each datapath block. Based on parameter functions, which relate to the design parameters for circuits in the circuit block, the design parameters are optimized to satisfy the design constraints.