Abstract: The present invention is generally directed to a system and method for identifying a storage node that is susceptible to charge sharing by another node. In accordance with one aspect of the invention, a method identifies storage nodes susceptible to charge sharing by first identifying, from a netlist, a storage node. For a given storage node, the method determines whether any pass FET devices are being driven by the storage node. For any such pass FET devices, the method retrieves a capacitance value for both sides of the pass FET devices being driven by the storage node. Specifically, a first capacitance value is retrieved for the storage node side of each pass FET device, and a second capacitance value is retrieved for a node on the opposite side of each pass FET device. Then the method calculates a ratio between the first and second capacitance values for each pass FET device being driven by the storage node.

Abstract: In a semiconductor device characteristic simulation apparatus and its method, performance characteristics of a semiconductor integrated circuit are image-displayed as a distribution on a semiconductor substrate without actually fabricating the semiconductor integrated circuit. To simulate the fluctuation in device characteristic values of a plurality of semiconductor integrated circuits formed on a semiconductor substrate by applying various types of processing to the semiconductor substrate, the present invention generates simulation data for executing simulations in accordance with measured data for a plurality of predetermined portions on the semiconductor substrate after processed, calculates device characteristic values of the semiconductor integrated circuits in accordance with the simulation data, and displays the fluctuation of device characteristic values as a distribution on the semiconductor substrate.

Abstract: A signal pattern representing a signal formed by quanta discretely distributed on a time base is generated. One of a plurality of destination circuits for branching is allocated to each of quanta within the generated signal pattern so that the ratio of the numbers of quanta in the plurality of destination circuits equals a predetermined branching ratio. A signal pattern representing a signal to be input to each of the destination circuits is generated assuming that each quantum enters only an allocated destination circuit. Thus, a result of processing of a signal processing apparatus for processing a signal formed by a very small number of quanta is predicted.

Abstract: A method for verifying an integrated circuit design using constraint information to develop a weighted data structure. In one embodiment, a binary decision diagram (BDD) includes a plurality of nodes (401, 402, 403, 404, 405, 406, 407, 420, and 430) representing signals and states in the circuit, and each node has a branching probability based on user-defined weights. The BDD represents the intersection of the input space and state space which satisfies the constraints. Current state information resulting from simulation is used to dynamically adjust the branching probabilities of the BDD on the fly. In one embodiment, the constraint information is applicable for formal verification of a portion of the circuit. In another embodiment, a simulation controller (12) receives design and constraint information and generates the program to control simulator (14).

Abstract: A method of generating a digital circuit model that has fewer latches than the circuit being modeled. Initially, a determination of whether the digital circuit is reducible is made. The digital circuit suitably includes one or more primary inputs, one or more primary outputs, and a plurality of latches comprised of a level one (L1) latch set and a level two (L2) latch set wherein the latch sets may or may not lack one-to-one correspondence. After determining that the digital circuit is reducible, at least one of the latches is replaced with combinational logic thereby reducing the latch count of the digital circuit model.

Abstract: A system and method for circuitry design verification testing which provides for maximized code re-use without unnecessary allocation of system resources. A circuit simulation subsystem is interfaced with a test subsystem. The test subsystem employs a system transaction class which collects convenience routines and thereby maximizes code re-use. The system transaction class contains pointers to device transaction classes which correspond to each of the functional models in the simulation subsystem, but does not require instantiation of all of the device transaction classes and associated device objects. One or more configuration transaction classes derived from the system transaction class define transactions between selected ones of the functional models within the simulation subsystem. The configuration transaction classes inherit the convenience routines of the system transaction class, but cause instantiation of the respective functional models only when needed for a transaction.

Abstract: The element to be simulated is divided into regions, and each region is further divided into a plurality of quadrature nodes. Pairs are formed for all the quadrature nodes. Green's functions are computed and stored for the pairs. Each of the pairs is allocated to either the far field or the near field for purposes of simulation in accordance with a criterion. A Gaussian quadrature is computed for the pairs allocated to the far field while a high order quadrature is computed for those allocated in the near field. The component simulation is arrived after combining information derived from the Gaussian quadrature and the high order quadrature into a matrix which is then solved to obtain the charge distribution. Summation of the charges thus obtained yields the capacitance of the element. The high order quadrature is computed using a plurality of basis functions. The basis functions, denoted &psgr;ik(r′), are 1,x,y,x2,xy,y2. The basis functions are used to compute a set of weights vjk.

Abstract: A method of, and apparatus for, obtaining a representation of an electrical circuit (400) suitable for time-domain simulation. The electrical circuit comprises a physical structure (102), which is modelled using electromagnetic field analysis, and also comprises a remainder circuit (104) of circuit components which are interconnected with the physical structure. The electromagnetic field analysis is capable of generating at least a high-frequency equivalent circuit which is representative of the physical structure (102) and is valid at the operating frequency of the circuit but not at DC. The method comprises including a set of DC sources (E1 to Ek) to ensure that, in a time-domain simulation, improved DC bias conditions are provided for any non-linear components in the remainder circuit. The DC sources may be voltage sources in each interconnection, current sources between each interconnection and a zero voltage reference interconnection, or a combination of the two.

Abstract: A method of determining a set of parameters for modeling an active semiconductor device in which current flow through a channel or other area is regulated by voltage applied to the device terminals, for example, MOSFETs. The method comprises first providing a plurality of measured values for current as a function of voltage for a plurality of active semiconductor devices of differing geometries. There is then determined an initial population of vectors comprising individual values representing a plurality of desired active semiconductor device model parameters. Fitness is then evaluated for each of the vectors by comparing calculated values for current as a function of voltage from the population to the plurality of measured values for current as a function of voltage of the vectors, converting any current differences to voltage errors and adding any such voltage errors together to arrive at a fitness value for each vector.

Abstract: A method for determining the setup and hold times of static flip-flops during the design and development of integrated circuits. The method utilizes simulations of an integrated circuit to determine a first amount of time required for a data signal to be transmitted from a first external node to a predetermined node in the register of a static flip-flop, and a second amount of time required for a clock signal to be transmitted from a second external node to the predetermined node. The setup time is determined by calculating a difference between the first amount of time from the second amount of time. Similarly, a hold time for the flip-flop is determined by calculating a difference between the amounts of time required for data and the clock signal to reach a second predetermined internal node of the flip-flop.

Abstract: One or more groups, into which a circuit simulator may partition an overall circuit, that are determined to belong to a feedback loop, also known as cycles, may be merged into a single group. The length of the loop, which is the number of groups in the loop, determines whether or not the groups of a loop will be merged into a single group. More particularly, loops of a length less than or equal to a number are merged. The number may be specified by the user, or otherwise determined. Once a merged group is formed, its inputs and outputs are determined, and it is treated like any other previously existing group. Preferably, not all the groups are merged into a single group.

Abstract: A method for simulating a portion of a circuit design is described. The circuit design includes a plurality of design files each corresponding to one of a plurality of design entities in the circuit design. A subset of the design entities is selected. The subset of the design entities corresponds to the portion of the circuit design to be simulated. In response to selection of the subset of the design entities, a netlist is generated under software control directly from the design files associated with the subset of the design entities. The portion of the circuit design is then simulated using the netlist.

Abstract: Techniques for increasing flexibility in use of virtual component blocks include a method for hardening a foundation block, a pin-unscrambling methodology for semi-hardened virtual component blocks, and parameterizable virtual component blocks. A method for hardening a foundation block and utilizing it in a circuit design comprises the steps of defining a virtual component foundation block, hardening an interior region of the foundation block including at least the critical timing components such as the system bus. The foundation block has a “soft collar” for allowing interface parameters to be specified when the foundation block is incorporated into a circuit design. In addition, the foundation block may comprise an internal, hierarchical clocking scheme for even clock distribution and optimum performance. For example, all internal clock delays may be padded, except the longest one, so that the clock signal arrives at all relevant reference points within the foundation block at the same time.

Abstract: In the design verification method, the design verification device, and the pipeline simulator generation device for microprocessors, a pipeline simulator (4, S4, S12) and verification programs for a microprocessor as a target in design are automatically generated (7, S9, S10) based on a pipeline specification described in a description language readable and analyzable by a computer, and the pipeline operation of the microprocessor is verified (12, S15, S16) based on the results (S13) of the simulation (11) of the RTL description and the result (6, S14) of the pipeline simulation performed based on the verification programs and the pipeline simulator.

Abstract: An integrated circuit chip having at least one source pin and a plurality of sink pins. A wire segment connects the source pin to at least one of the sink pins and includes at least two segments where one of the segments is larger than the other where electromigration is likely to occur.

Abstract: A method, system and computer program product for automatically determining optimal design parameters of a subsystem to meet design constraints. The subsystem comprises a plurality of circuits. The optimal design parameters are determined by performing a parameter-delay curve optimization of the subsystem design parameters.

Abstract: Disclosed is a method for generating AVF test file data for use in testing a simulation of an integrated circuit design, and verifying the generated AVF test file data before they are delivered to a physical silicon version of the integrated circuit design. The generation method includes providing a map file that contains a plurality of identifying statements for each multiple port I/O cell (or also including single port I/O cells) in the integrated circuit design. Then, generate a verilog executable file for the integrated circuit design. The verilog executable file is configured to contain data associated with the map file, a netlist of the integrated circuit design, output enable data derived from the netlist, and AVF data conversion information. The method further comprises executing the verilog executable file along with a test bench that includes the netlist of the integrated circuit design, a set of test files, and models.

Abstract: The present invention provides for more realistic worst case extreme determinations for an integrated circuit as compared to conventional techniques. In particular, the present invention provides a framework which affords for improved linkage between semiconductor manufacturing process parameters and an integrated circuit designed based on the electrical properties of cells making up the integrated circuit. The present invention divides an integrated circuit into simple standard cells and more complex cells. For simple standard cells (e.g., XOR, NAND, NOR, inverter), a pre-modeling step is performed to model the simple standard cell as a circuit in order to obtain gate delay and power consumption distributions related thereto. Such pre-modeling affords for more accurate semiconductor physical parameters to be employed to generate the normalized distribution of the integrated circuit which in turn provides for better worst case extremes.

Abstract: A method of, and apparatus for, obtaining a representation of an electrical circuit (400) suitable for time-domain simulation. The electrical circuit comprises a physical structure (102), which is modelled using electromagnetic field analysis, and also comprises a remainder circuit (104) of circuit components which are interconnected with the physical structure. The electromagnetic field analysis is capable of generating at least a high-frequency equivalent circuit which is representative of the physical structure (102) and is valid at the operating frequency of the circuit but not at DC. The method comprises including a set of DC sources ( E1 to Ek) to ensure that, in a time-domain simulation, improved DC bias conditions are provided for any non-linear components in the remainder circuit. The DC sources may be voltage sources in each interconnection, current sources between each interconnection and a zero voltage reference interconnection, or a combination of the two.

Abstract: A simulator simulates and verifies inter-chip functionality in a multi-chip computer system model. The chips within the multi-chip computer system model are characterized by a combination of detailed, low-level hardware models and generalized, high-level hardware emulators. As the simulator executes, inter-chip events are generated which are caused by interactions among and between the hardware models and the hardware emulators. An event processor processes events generated by the simulator, writing events to an event log file. An inter-chip event detector processes the event log file, filtering out inter-chip events caused by the hardware emulators, logging inter-chip events caused by the hardware models. Isolating inter-chip events caused by hardware models helps verification engineers direct the limited number of simulation cycles available during multi-chip verification, thus increasing the confidence level that the multi-chip computer system design is correct.

Abstract: A function simulates and verifies a computer program by inserting a syntactic mutation into one of the source code modules comprising the program. The mutated computer program is compiled and subjected to a subtlety check which detects non-subtle (i.e., easily detectable) syntactic mutations. If the subtlety check identifies the inserted syntactic mutation as non-subtle, functional testing on this mutated computer program is terminated, and a new mutated computer program is generated. However, if the subtlety check determines that the syntactic mutation is subtle, the mutated computer program is subjected to additional regression testing. If the regression testing is able to detect the subtle syntactic mutation within a predetermined simulation period, functional testing is terminated and a new mutated computer program is generated.

Abstract: Plural boundary points are generated on a string on the surface of a material and a first length of a line segment between the boundary points is obtained. Then, the displacement of the boundary point according to a process model and the boundary point is moved by the displacement. A second length of the line segment between the boundary points after the boundary point is moved is found. When the second length is greater than a value obtained by multiplying the first length by a first factor exceeding 1, a new boundary point is added to the line segment whereas when the second length is smaller than a value obtained by multiplying the first length by a second factor less than 1, one of the boundary points of the line segment is eliminated.

Abstract: The present invention is generally directed to a system and method for evaluating a netlist of a schematic to detect the output of a clock driver. In accordance with one embodiment of the invention, a method is provided for determining whether a circuit node is an output node of a clock driver circuit. The method includes the steps of ensuring that the node is a clock node, ensuring that the node is a node within an inverter loop, identifying every FET that is channel connected to the node, and, for every identified FET, ensuring that a signal that drives a gate node of the FET also drives a gate node of a different type FET. With these primary tests satisfied, the method determines the node under consideration to be an output node of a clock driver circuit. In accordance with another aspect of the invention, a method determines whether a circuit node is an output node of a clock driver circuit by ensuring that the node is a node within an inverter loop, and ensuring that a gate node of every FET (i.e.

Abstract: The present invention is a simulation tool input file generator implemented in a computer system that permits a designer to efficiently and effectively create and modify electrical circuit simulation tool input files. The simulation tool input file generator permits a user to conveniently enter high level circuit description information in user friendly formats such as an easy to use GUI. Based upon the information provided by a user, the present invention assembles data including circuit description files stored in a memory and produces a detailed simulation tool input files.

Abstract: A method and apparatus for producing an electronic circuit which allows a device to be connected to a bus, such as a system bus in a computer. The invention accepts user specified parameters for configuring a device adapter which interfaces the device to the bus, and thereafter generates a customized device adapter based on such user specified parameters. By using a common design macro, which is programmable, a user can easily specify and generate custom device adapters for a plurality of dissimilar devices to be connected to the bus. A resulting adapter architecture allows for multiple, dissimilar devices to interface to a computer bus with a single device adapter integrated circuit or card.

Abstract: A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.

Abstract: The simulation method of the present invention for simulating a system having a plurality of circuit modules using software, comprises the steps of: using an object oriented language; preparing a plurality of circuit base classes, which describe base circuit modules as classes, as a library; describing the circuit modules, to be simulated, as classes by inheriting the circuit base classes prepared as the library; and describing the system, to be simulated, by combining the circuit modules described as the classes.

Abstract: A method and apparatus for detecting floating transistor gates within a netlist model of an integrated circuit is disclosed. All transistor gates and input nodes coupled to the transistor gates are identified. These input nodes are then used to generate a resistor card. The resistor card is used in conjunction with the original netlist during simulation to couple two resistors to each input node. The first resistor is coupled between the input node and a high potential, and the second resistor is coupled between the input node and a lower potential. The resistors may be configured to have equal resistance values. The resistance values may be large enough to ensure that the current conducted through the resistors will be minimal in relation to the currents in the circuit when the input node is not floating. The resistance values may be small enough to overcome any leakage currents present in the circuit.

Abstract: A system and method for manipulating a netlist, at the time that the netlist is being created, to permit measurement of current flow through a net, or combination of nets, of a sub-circuit during a subsequent simulation process, the manipulation of the netlist including identifying nets through which current flow is to be measured, creating “artificial” nets for the identified nets, substituting the “artificial” nets for the identified nets in the netlist file, and connecting a power supply between the artificial net and the identified net for which it has been substituted.

Abstract: An approach for simulating hot carrier effects in an integrated circuit (IC) at the circuit level includes generating a hot carrier library of delay data for each cell in the IC, using the hot carrier library data to generate a set of scaled timing data for the IC and using the scaled timing data with a IC performance simulator to simulate the IC operation. The scaled timing data is based upon the cell delay data and time-based switching activity of each cell in the IC.

Abstract: A verification engine for verifying the design of a target system having a plurality of components interconnected by a plurality of target system buses is disclosed. The verification engine comprises a first hardware model and a second hardware model, both configured as a component and having a set of hardware model input/output pins. In addition, a first bus wrapper is connected to the first hardware model and a second bus wrapper is connected to the second hardware model. Further, a set of bus lines are each connected to the first bus wrapper and the second bus wrapper. Each bus wrapper also has switchable communicative circuitry that switchably communicatively connects each hardware model input/output pin to a bus line and has a control block controlling the switchable communicative circuitry. A system controller is connected to at least some of the bus lines and is adapted to transmit a sequence of time synchronization information to each bus wrapper control block by way of the bus lines.

Abstract: A method and system for co-verifying a hardware simulation of a field-programmable-system-level integrated circuit (FPSLIC) and a software simulation of the field-programmable-system-level integrated circuit. A FPSLIC device is simulated in hardware, and a simulator-port layout of the FPSLIC device is generated. In software, the method separately simulates, with an instruction-set simulator, the FPSLIC device, and outputs register contents from the instruction-set software. The contents from the simulator-port layout are verified with the register contents. Additionally, the method may further include outputting peripheral contents from the instruction-set simulator, and verifying contents from the simulator-port layout with the peripheral contents. UART contents also may be outputted from the instruction-set simulator, and verified with contents from the simulator-port layout with the UART contents.

Abstract: In a method and apparatus for carrying out circuit simulation which performs circuit simulation on a circuit to be simulated, a plurality of partial circuits to be inspected for equivalence in order to check if they exhibit equivalent operational characteristics are extracted from the circuit to be simulated, and the intensity of the influence of an external terminal of the circuit to be simulated is assessed by tracing paths linking the external terminal and given terminals of the partial circuits. Moreover, based on the configurations of the partial circuits, the connectional relationships of corresponding input terminals of the partial circuits, the operational characteristics of corresponding component elements of the partial circuits, and the intensity of the influence of the external terminal, the plurality of partial circuits are inspected for equivalence in order to detect partial circuits exhibiting equivalence.

Abstract: A method is provided for large signal modeling of a field effect transistor. The method includes establishing a small signal model for the transistor, such model having a gate-source capacitance Cgs and a drain-gate capacitance Cdg, both being functions of a gate-source voltage Vgs and a drain-source voltage Vds. The s-parameters of the transistor are measured and curve fitting is applied to the measured s-parameters to establish small signal model parameters. The small signal model parameters include gate-source capacitance Cgs as a function of Vgs and Vds and gate-drain capacitance Cdg as a function of Vgs and Vds. Curve fitting is applied to Cgs and Cdg to establish large signal gate charge fitting parameters. The established large signal gate charge fitting parameters are used to express a gate-source charge Qgs and a gate-drain charge Qgd as functions of Vgs and a gate-drain voltage Vgd in a large signal model for the transistor.

Abstract: A method and apparatus for providing a graphical user interface for simulating designs with mixed signals is described. The present invention provides graphical information to a circuit designer as to the solution of the equation(s) that describe or model the design. The graphical information allows the designer to see convergence and convergence rates of the analog circuit simulation. By providing the designer with information related to the convergence of solutions for the modeling equations, the designer is better able to debug the design because he or she can view the timing and situations related to convergence and divergence.

Abstract: A method and apparatus for managing simulation results involves identifying distinct transactions in a group of simulation results so that the simulation results can be stored and viewed on a transaction basis instead of as a single continuous block of simulation results. A transaction is defined as a specific sequence of transitions on a selection or grouping of signals over a period of time where the signal activity has some higher level operational meaning. Simulation results are recorded on a transaction basis by storing standard simulation results information along with transaction-specific data elements, including the name of the transaction, the start time of the transaction, the end time of the transaction, and the interface on which the transaction takes place. Additional transaction-specific data elements may include parent and child relationships and predecessor and successor relationships between transactions.

Abstract: In a structure and a designing method of a memory integrated with a logic, a memory macro comprises L memory array blocks 1-1, 1-2, . . . 1-L each including memory cell arrays each with a storage capacity of K bits and sense amplifiers. Memory array power source driver blocks 4-1, 4-2, . . . 4-L each including a circuit for generating a driver power source which drives a sense amplifier are arranged in a corresponding manner to memory array blocks 1-1, 1-2, . . . 1-L. The memory array blocks 1-1, 1-2, . . . 1-L are arranged along a column direction in an adjacent manner to one another and DQ line pairs extending along a column direction are arranged on the memory array blocks 1-1, 1-2, . . . 1-L. Source line blocks 6a-L, 6b-L, 7a, 7b, 8a, 8b are arranged at an end of the memory array blocks in a row direction. According to such a design, short design turnaround for design and shrinkage of occupying area of a memory macro can be realized.

Abstract: Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width wmux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width wmux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors.

Abstract: Methods of instrumenting synthesizable source code to enable debugging support akin to high-level language programming environments for gate-level simulation are provided. One method of facilitating gate level simulation includes generating cross-reference instrumentation data including instrumentation logic indicative of an execution status of at least one synthesizable register transfer level (RTL) source code statement. A gate-level netlist is synthesized from the source code. Evaluation of the instrumentation logic during simulation of the gate-level netlist facilitates simulation by indicating the execution status of a corresponding source code statement. One method results in a modified gatelevel netlist to generate instrumentation signals corresponding to synthesizable statements within the source code. This may be accomplished by modifying the source code or by generating the modified gate-level netlist as if the source code was modified during synthesis.

Abstract: The number (Nc) of conductor regions and the number (Ncell(i)) of cells constituting each conductor region (ci) are calculated from the result of a configuration simulation. Each conductor region (ci) is judged whether or not the number (Ncell(i)) of cells thereof is less than a minimum cell count (Ncellmin) for recognition as an electrode or interconnect line. A conductor region (ci) judged that the number (Ncell(i)) of cells is not less than the minimum cell count (Ncellmin) is regarded as the electrode or interconnect line. A conductor region (ci) judged that the number (Ncell(i)) of cells is less than the minimum cell count (Ncellmin) is replaced with a dielectric positioned on a previously set one of the top, bottom, left-hand, right-hand, front and rear sides of the conductor region (ci).

Abstract: For an analysis of an electrical behaviour of a specific cell of a monolithically integrated circuit, a simulation model is used which is composed of a fine model part of the cell of interest and a coarse model part of the remainder of the integrated circuit.

Abstract: The Model Editor (106) makes simulation modeling easier and more intuitive by extracting essential information and presenting it to the user, and by providing tools to investigate simulation and model robustness, in an interactive, graphical environment. The Model Editor (106) includes a Newton step manager as an interactive, graphical tool. During simulation of a model, the Newton step manager captures matrix norms. Any indications of Newton limiting are also captured. The matrix norms are plotted as a function of iteration count, and the iterations at which Newton limiting were encountered are identified. Newton step manager can also be run automatically using a functional dependency analysis.

Abstract: The present invention is a design apparatus compiled on a computer environment for generating from a behavioral description of a system comprising at least one digital system part, an implementable description for said system, said behavioral description being represented on said computer environment as a first set of objects with a first set of relations therebetween, said implementable description being represented on said computer environment as a second set of objects with a second set of relations therebetween, said first and second set of objects being part of a design environment.

Abstract: Method of simultaneously carrying out manufacturing and product engineering integrated with knowledge networking.

Abstract: A system and method for manipulating a netlist, at the time that the netlist is being created, to permit measurement of current flow through a net, or combination of nets, of a sub-circuit during a subsequent simulation process, the manipulation of the netlist including identifying nets through which current flow is to be measured, creating “artificial” nets for the identified nets, substituting the “artificial” nets for the identified nets in the netlist file, and connecting a power supply between the artificial net and the identified net for which it has been substituted.

Abstract: A transient analysis device in which a simulation executing unit uses a first net list produced by a net list producing unit to measure a settling time of an analog/digital mixed circuit to be analyzed, after a dummy pulse parameter setting unit sets a parameter of a dummy pulse based on the measurement result, the net list producing unit converts, into a net list, a transfer function of a new circuit obtained as a result of the addition of a dummy pulse generation circuit for generating a dummy pulse whose parameter has been set to the analog/digital mixed circuit, and the simulation executing unit executes transient analysis processing by using a second net list produced with respect to the new circuit.

Abstract: A fault diagnostic apparatus for the recognition of defective components of a technical system with fault-relevant process variables contains a diagnostic module which has a checklist and a table of predetermined conditions (in memory). The conditions are determined by a component fault simulation in a generated model of the operation of the system. The checklist provides a primary process variable and secondary process variables affected thereby, and the table of conditions gives for each combination of fault-relevant process variables, the corresponding components suspected of being faulty. During the operation of the system, the diagnostic module detects the condition values of the primary process variables and, upon the occurrence of a fault condition therein, activates a diagnostic process in which it compares the actual condition combination with the one stored in the table of conditions.

Abstract: A microcontroller software testing tool is disclosed for testing and debugging software for a semiconductor circuit. The microcontroller software testing tool includes a simulator for simulating the execution of the software program on the target semiconductor circuit and an emulator to permit emulation before the actual silicon exists. The emulator utilizes the same high definition language specification, such as VHDL models, that define the silicon during the fabrication process plus additional logic to model behavior of the emulated processor. In a simulation mode, the microcontroller software testing tool simulates the target semiconductor circuit on a general purpose computing device, by interpreting the instructions in the software using an instruction set of the target semiconductor circuit, and otherwise behaving like the target semiconductor circuit; and executes and evaluates the software on the simulated semiconductor circuit.

Abstract: Delay-independent cycle-based logic simulation of synchronous digital circuits with levelized compiled code simulation has substantially increased speed. Sweep, eliminate, and factor reduce the number of literals. The use of cofactoring, a register allocation and spill scheme, an inverter minimization scheme, and retiming further reduce the simulation time for two and four valued simulation. A shift minimization scheme reduces time in four-valued simulation. The faster simulation is embodied in a method, a computer system, and a computer program product.

Abstract: A method of generating R,C parameters corresponding to statistically worst case interconnect delays for computer simulation of integrated circuit designs, comprising the steps of: computing a statistically worst case interconnect delay from randomly generated material and geometry values characterizing an integrated circuit interconnect process; computing a representative set of material and geometry values corresponding to the statistically worst case interconnect delay; and computing R,C parameters corresponding to the statistically worst case interconnect delay from the representative set of material and geometry values.