Abstract: A method of simulation of an electronic circuit including a plurality of components having variable characteristics, including an initialization step consisting of giving each variable characteristic a value from a set of predetermined values deterministically linked to a single initialization value likely to be memorized.

Abstract: A method and apparatus for design validation of complex IC with use of a combination of an event tester and a field programmable gate array (FPGA) or an emulator board. The design validation method eliminates logic simulation which is a bottleneck in design validation today. Because of the elimination of slow simulation from the design validation flow, extensive design validation can be done before design is taped-out for manufacturing, and because extensive design validation become possible, it eliminates the need of a prototype before mass production.

Abstract: One aspect of the invention is a coverage metric to identify that part of a state space which is covered by properties verified by model checking. In each property, a signal is identified (or a proposition on several signals) as the observed signal in that property. The coverage metric measures the coverage of a set of properties with respect to the observed signal. The coverage metric identifies the reachable states in which the value of the observed signal determines the validity of the verified properties. Then a model checking algorithm can be used to check the correctness condition on the observed signal in these “covered” states to prove or disprove the property.

Abstract: A system and method is provided to accurately model bidirectional wire I/O using hardware description language (HDL). The preferred model and method uses an HDL model that provides two parallel paths between ports of the bidirectional wire I/O. During simulation, the ports are monitored for activity. When an event is detected on either port, the model checks both ports to see if they are different values. If the ports are different values, one of the two parallel paths is enabled and the other disabled. For example, the model enables the path in which the new signal has appeared and thus passes the signal to the other port. The preferred model allows for the use of HDL elements that support full timing annotation. The preferred embodiment also removes the possibility of high impedance transition error that can result from false transitions to a high impedance state.

Abstract: A system and method for modeling the power consumed by a logic cell in a computer controlled power estimation process estimating the power consumed for an integrated circuit represented by logic cells and connections between cells. The present invention models power consumption within a logic cell associated with a particular designated pin (output, internal, or bidirectional) based on which input (or internal or bidirectional) pin transitioned causing the designated pin to transition. This is referred to as path dependent power modeling. A different power consumption value can be provided for each different modeled transition. The logic cells and the power consumption model for them are stored in a logic cell “library” within the computer system. Path dependent power modeling of the present invention allows library designers to specify a different set of power values depending on which pin transition (e.g., input pin) caused the designated pin to transition.

Abstract: A design system for modeling bi-directional pad cells, the interaction of internal pull cells/resistors with pad cells of all types, and the interaction of external pull cells/resistors with pad cells of all types. This modeling technique involves the use of three separate pins on each bi-directional pad cell: an input-only pin, an output-only pin, and a resolved pin. The input-only pin reflects the data that is supplied to the pad from external sources. The output-only pin reflects the data that is supplied as output from the pad cell (strong data from the output driver). The resolved pin reflects the combination of the input and the output data that are present, as well as the effect of resistive data supplied by pull-up/down resistors/cells. The output-only and resolved pins are implemented as internal or hidden pins within a pad cell model. These pins are included in the model for the I/O pad cells in a given library. The existing pad pin serves as the input-only pin.

Abstract: An EDA tool is provided with a circuit simulator that simulates circuit operation using dynamic partitioning and on-demand evaluation. The circuit simulator includes a static partitioner, a dynamic partitioner and an evaluation scheduler. The static partitioner pre-forms a number of static partitions for the circuit. During simulation, the dynamic partitioner forms and re-forms a number of dynamic partitions referencing the static partitions. At each simulation time step, the evaluation scheduler determines which, if any, of the dynamic partitions have to be evaluated, and evaluating on-demand only those where evaluations are necessary. In one embodiment, when evaluations are performed, they are performed through matrix solution when accuracy is needed.

Abstract: A method is provided for the optimization of apodization circuits. An apodization circuit is provided and a multiplier within the apodization circuit is replaced with a first replacement multiplier. A window function of the apodization circuit is then replaced with a first replacement window function.

Abstract: A single pattern-matching algorithm which allows both exact and inexact pattern-matching so that transistor-level design automation tools can reliably perform timing analysis, electrical rules checking, noise analysis, test pattern generation, formal design verification, and the like prior to manufacturing custom logic. The user (circuit designer) specifies which of each of the pattern external nets may be matched inexactly (attached to Vdd, attached to GND, and shorted to other external nets), with the remainder of the pattern external net connections being matched using exact isomorphism constraints. The method described herein achieves a substantial reduction in the number of patterns which circuit designers must generate, and altogether eliminates the need for an exponential number of patterns by providing an inexact pattern matcher to circuit designers.

Abstract: An emulation system equipped to emulate multiple circuit designs concurrently is disclosed. The emulation system includes an emulator having reconfigurable emulation resources for emulating circuit designs, and a host system programmed with programming instructions that operate to generate coordinated configuration information for a number of circuit designs to enable the reconfigurable emulation resources to be configured in a coordinated manner to allow the circuit designs to be emulated concurrently.

Abstract: The present invention relates to hardware design and simulation thereof. In particular, it relates to a method and system for verifying hardware designs. It is basically proposed to provide a plurality of instruments, i.e., a kind of testcase language, which is able to simplify the hardware verification work. Each of the language elements contributes specifically to the general aim of the present invention, i.e., to improve the management of test cases and their execution. For example, a construct language element is provided which is able to be filled up with technical information about one or more hardware logic functions, and which checks their functionality by its own, returning an error value. Thus, the advantage results that due to the systematic management of testcases an efficient testcase generation and execution can be performed.

Abstract: The present invention provides a circuit simulation method for a semiconductor device in which the circuit configuration is specified by a netlist. First, variations in the layout pattern and arrangement of elements used in the semiconductor device are formulated into an equation including parameters (S110). Next, the parameters included in the equation are put into element parameter groupings corresponding to each element, and the element parameter groupings are stored in storage means (S120). Then, the parameters in the element parameter groupings are varied in accordance with the conditions obtained from variations in manufacturing process with respect to the semiconductor device (S130). Then, these varied parameters are used to execute a circuit simulation with processing means (S140).

Abstract: The apparatus comprises the syntax checking section that checks the syntax of a device model according to a check table showing the relation between the syntax of the device model showing electrical characteristics of a semiconductor device and an amendment when deviating from the syntax. The syntax error amendment creating section corrects the device model according to a corresponding amendment when a description deviating from the syntax is checked by the syntax checking section.

Abstract: Disclosed is a method of designing a memory device that has substantially reduced bitline voltage offsets. The method includes providing a memory core having a depth that defines a plurality of words, and a word width that is defined by multiple pairs of a global bitline and a global complementary bitline. The method also includes designing a six transistor core cell having a bitline and a complementary bitline, and designing a flipped six transistor core cell that has a flipped bitline and a flipped complementary bitline. Further, the method includes arranging a six transistor core cell followed by a flipped six transistor core cell along each of the multiple pairs of the global bitline and the global complementary bitline. Preferably, the bitline of the six transistor core cell is coupled with the flipped complementary bitline of the flipped six transistor core cell, and the complementary bitline of the six transistor core cell is coupled to the flipped bitline of the flipped six transistor core cell.

Abstract: Configurable interconnect resources of field programmable gate arrays (FPGA's) are tested by configuring at least some of the lookup tables (LUT's), registers and input signal acquirers to implement one or more sequential state machines that feed back their current states via at least some of the interconnect conductors to the inputs of the LUT's. The fedback signals are decoded by the LUT's for defining next-states of the one or more sequential state machines. Each sequential state machine may be programmed to sequentially step through a number of unique states, where the unique states challenge capabilities of the interconnect conductors to toggle through combinations of different signal levels. The sequential state machines are exercised to sequentially step through plural ones of their unique states.

Abstract: A method for defining electrical components enables a layout tool to include functionally extraneous cells in an integrated circuit design without significant adverse impact to the operation of the logically functional cells. The method defines the description of a first functionally extraneous cell for a layout tool so an initial layout of the die produced by the layout tool does not functionally couple the first functionally extraneous cell to a second functionally extraneous cell. The description of the functionally extraneous cell is altered so that the layout tool produces a second layout of the die that functionally couples the first and second functionally extraneous cells without altering the position of the second functionally extraneous cell with respect to a logically functional cell. The description of the functionally extraneous cell complies with the description constraints for cells.

Abstract: This invention describes a multithread HDL logic simulator that is unique from the prior arts. Specifically, it can process both VHDL and Verilog languages in a single program, and it uses special concurrent algorithms to accelerate the tool's performance on multiprocessor platforms to achieve linear to super-linear scalability on multiprocessor systems. Furthermore, the invention includes a unique remote logic simulation and job scheduling capabilities.

Abstract: A software method is disclosed for modeling dielectric losses in transmission lines, such as lines on a computer chip or circuit board, using a circuit simulation application, such as a SPICE program. Line resistance, self-inductance, and self-capacitance are calculated and modeled as a lumped element circuit having a resistor and an inductor connected in series, with a capacitance in parallel. A two-port scattering matrix is used to model the dielectric losses. The method uses a matrix that is related to the dielectric constant of the medium surrounding the line, the length of the line, and the frequency of the signal. The method assumes low loss conditions typical of circuit boards or integrated circuit chips, whereby the intrinsic impedance of the line is not affected by losses and the matrix is normalized to the intrinsic impedance.

Abstract: A computer-implemented method for matching parameters of outputs generated by a first and second process. The first process generates a first output having a characteristic measurable by a first parameter, and the second process generates a second output having the characteristic measurable by a second parameter. A computer having a processing unit and memory is provided. The computer generates a first model of the first parameter for the first process and a second model of the second parameter for the second process. The computer generates a first simulated output of the first process using the first model. A correction, which is a function of the second model and which compensates for the effect of the second process on the second parameter, is applied to the first simulated output to obtain a corrected output. The second process is applied to the corrected output to generate with the computer thereby a third output matching the first parameter of the first output.

Abstract: A low-complexity, high accuracy model of a CPU anti-resonance system has been developed. The model includes a load model that simulates the performance of the anti-resonance circuit, a transistor that models the performance of a high frequency capacitor, and a capacitor that models the performance of the intrinsic capacitance of a section of the microprocessor. All of the elements of the model are connected in parallel.

Abstract: A design system for modeling bi-directional pad cells, the interaction of internal pull cells/resistors with pad cells of all types, and the interaction of external pull cells/resistors with pad cells of all types. This modeling technique involves the use of three separate pins on each bi-directional pad cell: an input-only pin, an output-only pin, and a resolved pin. The input-only pin reflects the data that is supplied to the pad from external sources. The output-only pin reflects the data that is supplied as output from the pad cell (strong data from the output driver). The resolved pin reflects the combination of the input and the output data that are present, as well as the effect of resistive data supplied by pull-up/down resistors/cells. The output-only and resolved pins are implemented as internal or hidden pins within a pad cell model. These pins are included in the model for the I/O pad cells in a given library. The existing pad pin serves as the input-only pin.

Abstract: A semiconductor integrated circuit device is provided in which current consumption is reduced at the time a data access by consecutive addresses is performed to a ROM circuit or a RAM circuit. The semiconductor integrated circuit device incorporates a ROM circuit 1 and a control circuit 68 for controlling a data access to the ROM circuit, wherein an address generation circuit 69 included in the control circuit divides a clock to be input, performs a phase adjustment by sampling the divided clock and generates an address signal of several bits in which only a value of 1 bit changes in a sequential order when a data access by consecutive addresses is performed on the ROM circuit.

Abstract: An HDL circuit conversion and simulation method is described. One or more HDL source modules are converted to simulation program libraries and simulated. The simulation system and method compiles HDL models into linkable libraries. Resulting libraries include calls to the HDL's PLI so that the libraries along with HDL source can be simulated using any simulator of the HDL. The host simulator provides scheduling and system operations that are requested by the linkable simulation program libraries produced by the simulation system here disclosed. The system and method is called an HDL simulator independent PLI based model compiler. The simulation system allows utilization of HDL simulator advances without changing linkable libraries.

Abstract: A computer-implemented method and apparatus for creating a testable circuit design that includes one or more embedded cores. The method includes identifying an embedded core within the circuit design; associating certain pins of the embedded core with pins of the circuit design; and inserting into the circuit design access circuitry coupling the certain connection pins of the embedded core to the associated pins of the circuit design. The method further includes providing test vectors for the embedded core; and generating test vectors for the circuit design by mapping the core test vectors applicable to the certain pins of the embedded core to the associated pins of the circuit design. The cores within the circuit design can then be tested after manufacture by applying the design test vectors to the circuit design.

Abstract: Systems and methods for modeling multidimensional physical systems, including biological and chemical systems. A system to be treated as a model is represented by a geometrical structure. The geometry is superposed onto a lattice template. Functional elements are obtained to express relationships between portions of the system to be modeled. The functional elements are assigned to lattice regions. The initial conditions, boundary conditions and constraints on the model are specified. The lattice is solved using a circuit simulation package. The quantities determined for the circuit are used to compute system quantities. Optionally the computer information is displayed. Optionally, the system is modeled as multiple lattices, which can be solved either serially (iteratively) or in parallel, to obtain a consistent solution.

Abstract: A computerized method and system for automatically extracting an IEEE 1149.1 standard design from a netlist and performing compliance checking. The present invention receives the TAP (test access port) description and compliance enable ports of a netlist. The TAP controller is extracted and its state ports are identified, referenced in a boundary scan design database (BSDD) and its states are verified. The TAP controller is controlled so that the instruction register is located and referenced in the BSDD. The TAP controller is controlled so that the bypass register is found and the BSDD is updated. The TAP controller is controlled so that the shift and update cells of the boundary scan register (BSR) are found, the control, input and output BSR cells are characterized and the BSDD is updated. Primary input and output information is also inferred and the device_ID register is found. Frontier pins are used to locate signatures of the remaining instructions and their test data registers are found.

Abstract: A method and apparatus are provided for implementing multiple configurations of multiple input/output (IO) subsystems in a single simulation model. At least one bus routing switch is included in the single simulation model. Each bus routing switch includes a plurality of ports respectively connected to a plurality of IO busses. Predefined ones of the plurality of IO busses are connected to respective multiple input/output (IO) subsystems in the single simulation model. The bus routing switch is selectively configurable for interconnecting predetermined ones of the plurality of ports. The bus routing switch includes a variable delay latch structure to simulate the effect of long wires. Each bus routing switch includes a plurality of multiplexers. Each of the plurality of multiplexers includes inputs connected to the plurality of ports, an output connected to a respective one of the plurality of ports and has a control input for configuring the bus routing switch.

Abstract: An advanced control block that implements multiple-input/multiple-output control, such as model predictive control, within a process control system is initiated by creating an initial control block having generic control logic and desired control inputs and control outputs communicatively connected to process outputs and process inputs within a process control routine. A waveform generator within the control block systematically upsets each of the process inputs via the control block outputs using excitation waveforms designed for use in developing a process model. At the same time, a data collection routine collects data indicating the response of each of the process outputs to the waveforms delivered at each of the process inputs. After sufficient data has been collected, a process modeling routine generates a process model from the collected data and a control logic parameter creation routine creates control logic parameters for the control logic from the process model.

Abstract: There is provided a method for simulating the electrical characteristics of an electronic device including a step of specifying the material, electrical characteristics, and shape of a part of interest of the electronic device, the specification of the shape being performed by selecting it from among several preselected simplified shape models to obtain required data easily. Further, it is possible to reuse such data as input data for various simulators. The data can be accurately created in a shorter period of time.

Abstract: An output FIFO data transfer control device can comprise a geometric arithmetic core including one integer processing unit or IPU and a plurality of floating-point processing units or FPUs. Each processing unit includes an intermediate buffer or data output buffer for storing a data on an arithmetic result. When an instruction of data transfer from at least one of the plurality of processing units to one output FIFO is issued, a write/read pointer generating unit generates a write pointer identifying a specific location where data on an arithmetic result associated with the instruction is to be stored in the intermediate buffer of at least one of the plurality of processing units. The write/read pointer generating unit also generates a read pointer identifying a specific location where data is to be read out of the intermediate buffer of at least one of the plurality of processing units.

Abstract: This invention relates to matched instruction set processor systems and methods to efficiently design and implement the matched instruction set processor systems. A method to efficiently design and implement a matched instruction set processor system includes analyzing and mapping design specifications of the matched instruction set processor into application components, wherein each application component represents a reusable function commonly used in digital communication systems. The method further includes decomposing the matched instruction set processor system into interconnected design vectors, wherein the design vectors are presented in the Java programming language. The method also includes analyzing and mapping the interconnected design vectors into specific hardware and software elements.

Abstract: This invention relates to matched instruction set processor systems and a method, system, and apparatus to efficiently design and implement matched instruction set processor systems by mapping system designs to re-configurable hardware platforms. The method includes decomposing the matched instruction set processor system into interconnected design vectors, each of the interconnected design vectors including a binding header method, a run method, a conjugate virtual machine (CVM), a binding trailer method, and an invocation method. The method also includes analyzing and mapping the interconnected design vectors into a re-configurable platform.

Abstract: This invention relates to matched instruction set processor systems and a method, system, and apparatus to efficiently design and implement matched instruction set process systems using interconnected design components. The method includes decomposing the matched instruction set processor system into interconnected design vectors. The method further includes analyzing and mapping the interconnected design vectors into specific hardware and software elements.

Abstract: A method for functional verification of a design for a parallel processing device includes receiving a sequence of single instructions from a dynamic test program generator, and assembling a plurality of the instructions from the sequence into an instruction word, in accordance with predetermined rules applicable to the parallel processing device. The instruction word is input to a simulator of the parallel processing device so as to determine a response of the device to the instruction word.

Abstract: A computer is operated to generate electronic data defining a system model by loading into the computer a class definition defining instructions which are processed by the system, the definition including a set of functional methods to which the instruction is subjected by the system and a set of locations for members representing the instruction. A model execution program is then executed on the computer which calls the class definition for each instruction, invokes one of the functional methods and loads the locations of the entry with state information depending on the functional method to create a functional component. The functional component is loaded into memory and the state information of the functional component modified independence on a subsequently invoked functional method by the model execution program.

Abstract: A configuration software tool is disclosed for analyzing circuit design violations detected by an E-CAD tool and proposing solutions. An E-CAD tool analyzes a circuit design and outputs violations of design specifications. The configuration tool reads the violations to identify symptoms. The configuration tool accesses a solutions database that stores solutions to common violations encountered with the design. Based on the symptoms, the configuration tool outputs possible solutions for each violation. The user selects one of the proposed solutions or another solution. Based on the selected solution, the configuration tool edits the configuration file of the E-CAD tool. Once all solutions are resolved, the E-CAD tool is re-run on the design. The configuration tool may be stored in a computer system that operates the E-CAD tool, or it may be stored in a remote location accessed by multiple computer systems, such as network server connected to the computer systems.

Abstract: An efficient method for optimizing RC circuit design to reduce delay. The method comprises: calculating a first moment and a second moment of impulse response for an RC circuit; (2) computing a delay value for each node of the RC circuit utilizing the first and second moments by multiplying the natural logarithm of 2 with a division of the squared power of the first impulse moment by the square root of the second impulse moment; and (3) analyzing each node to determine if the delay at that node is at a desired optimization condition for optimizing the circuit response.

Abstract: A virtual computer verification platform is provided with a verifying and debugging environment so as to develop a new microprocessor chip, a new system software, a new firmware and a new peripheral chip. The virtual computer verification platform includes a simulation system and a set of on-line debugging auxiliary tools, wherein the microprocessor chip can be designed in a Behavior model, a RTL model and a Gate model. The message communication for integrating the whole simulation system is implemented through a message passing mechanism supported by UNIX IPC (Inter-Process Communication) and PLI (Programming Language Interface) supported by Verilog.

Abstract: A molecular computer is formed by establishing arrays of spaced-apart input and output pins on opposing sides of a containment, injecting moleware in solution into the containment and then allowing the moleware to bridge the input and output pins. Moleware includes molecular alligator clip-bearing 2-, 3-, and molecular 4-, or multi-terminal wires, carbon nanotube wires, molecular resonant tunneling diodes, molecular switches, molecular controllers that can be modulated via external electrical or magnetic fields, massive interconnect stations based on single nanometer-sized particles, and dynamic and static random access memory (DRAM and SRAM) components composed of molecular controller/nanoparticle or fullerene hybrids. The current-voltage characteristics that result from the bridging between input and output arrays can be ascertained using another computer to identify the bundles of inputs and corresponding outputs that provide a truth table for the specific functions of the computer.

Abstract: A method for providing a mathematical expression representing the operation of a field-effect transistor in its saturation region is disclosed. Data representing the operation of the transistor is divided into data segments with a monomial function fitted to each of the segments. The data segments are selected for a particular operating parameter such as transconductance based on knowledge of the transistor operation. The error at the transition from one function to another is checked and the data segments redivided to minimize the error. The resulting expression lends itself to global solution with geometric programs.

Abstract: A system and method for circuitry design verification testing using a structure of interface independent classes to provide for rapid prototyping and design modification while maximizing test code re-use. A circuit simulation subsystem is interfaced with a test subsystem. The test subsystem employs a system transaction class for collecting common routines and pointers to device transactions. One or more configuration transaction classes derived from the system transaction class define transactions between functional models within the simulation subsystem and cause instantiation of the respective functional models. Operations are performed on the functional models via pointers to interface independent transaction classes which define interfaces to the devices. The operations are mapped to the current designs of the functional models by subclasses of the interface independent transaction classes.

Abstract: A hardware design language V++ is described. V++ provides an automatically designed and implemented communications protocol, embedded by a compiler in the design itself. This protocol permits transparent, automatic communication between modules in a hardware design. The protocol generalizes current design practice and impacts neither the cycle time, nor the area, of a typical system. Incorporating this protocol in the language itself frees the designer from the task of writing communications code, and ensures that two communicating modules follow the same low-level protocol. In V++ each program is directly interpreted as a network of communicating finite state machines. The composition of two V++ programs is a V++ program, with well-defined, deterministic semantics.

Abstract: An aspect of the present invention provides a method of carrying out a simulation with simulation data, including, determining whether or not the simulation data includes boundary conditions set for a boundary of a calculation area set for the simulation, computing the influence of the boundary conditions on the inside of the calculation area if the simulation data includes the boundary conditions, displaying the influence of the boundary conditions on the inside of the calculation area, prompting to enter an instruction whether or not the boundary conditions are changed, and if an instruction to make no change in the boundary conditions is entered, carrying out the simulation with the simulation data.

Abstract: A switch level simulation system includes a netlister, a cross-coupled device detector, a cross-coupled device transformer and a switch level simulator. The user provides a circuit a design to the netlister, which generates a netlist of the circuit. The cross-coupled device detector searches the netlist to find all of the cross-coupled devices in the circuit design. The cross-coupled device detector also determines whether the cross-coupled device has a “rail” node directly connected an external voltage source line. The cross-coupled device transformer transforms each cross-coupled device having a rail node into a transformed cross-coupled device by inserting in the netlist a device at the rail node mirroring the enable device. The mirror device allows the transformed cross-coupled device to provide a high impedance state to emulate the meta-stable state of the cross-coupled device during switch level simulation.

Abstract: A method and system are described in a logic simulator machine for efficiently creating a trace of an array which includes a plurality of storage locations. The logic simulator machine executes a test routine. Prior to executing the test routine, an initial copy of all data included within each of the storage locations of the array is stored as a first trace of the array. During execution of a first cycle the test routine, all of the write control inputs into the array are read to identify ones of the storage locations which were modified during the execution of the first cycle. A new trace of the array is generated which includes a copy of all of the data of the first trace. In addition, only those ones of the storage locations in the first trace which were modified during the first cycle are updated. A trace is thus generated by updating only those ones of the storage locations which were modified during execution of a cycle of the test routine.

Abstract: A method and system are described in a logic simulator machine for overriding a value of a net during execution of a test routine. A model of a logic design to be simulated is built utilizing the logic simulator machine. The logic design includes multiple nets. One of the nets whose actual value may be overridden is selected. A multiplexer is inserted into the model. The multiplexer receives as its inputs the actual value of the selected net, a control bit, and an override value bit. An override value is input into the multiplexer using the override value bit. The multiplexer outputs a current value of the selected net. The current value is thus propagated to other nets. The override value is propagated as the current value of the net instead of the net's actual value throughout execution of the test routine when the multiplexer control bit is set.

Abstract: A method and structure for predicting semiconductor product costs at a fabricator entailing a storage medium which includes a database of historical critical dimensions and historical critical groundrules correlated to cost functions at the fabricator. The user interface has user inputs for new design parameters and new critical groundrules associated with a new device to be produced at the fabricator and a computer adapted to receive the user inputs, extract data from the storage medium, and compute semiconductor costs for the new device. The historical critical dimensions and the new critical dimensions are gate dimensions and the new critical dimensions are smaller than the historical critical dimensions. This device includes a future technology generation. Fabrication hardware and fabrication methods for producing the future technology generation are unknown and the relationships comprise base models and models that include options.

Abstract: A method and system are described for efficiently overriding a value of a net in an array during execution of a test routine. The logic simulator machine is simulating a logic design which includes the array and multiple nets. A current value of the net is set equal to an override value. A normal update to the array is permitted to occur during execution of a single cycle of the test routine. A determination is then made regarding whether the override value is still stored in the array for the particular net. If the override value is not still stored in the array for this net, normal updates to the array are prohibited during a single cycle of the test routine. During this cycle of the test routine, the override value is then again stored in the net as the current value of the net. This override value is thus made available to be read during this cycle of the test routine while writes to the array are disabled.

Abstract: Data processor emulation information that has been collected and arranged into a plurality of first information blocks during the collection process is re-arranged into a plurality of second information blocks which differ in size from the first information blocks. A sequence of the second information blocks is output from the data processor via a plurality of terminals thereof.

Abstract: In device numerical analysis by a computer, in the case of analysis involving an external circuit, much better initial values are given so that calculation time is shortened. A device simulation apparatus 10 includes: a presumed potential designation unit 12 for a user to designate presumed potentials in device electrode nodes; a physical quantity initial value setting unit 14 to acquire a physical quantity by analyzing the above described presumed potentials to set the above described physical quantity as an initial value of a physical quantity at internal nodes in the device; a potential initial value setting unit 16 to set an initial value of potential at nodes of the external circuit based on the above described presumed potential; and a device analyzing unit 18 to analyze a device involving an external circuit with the above described set initial values. Usage of device electrode node potentials presumed by the user makes better initial values available.