Abstract: Disclosed herein is a method of managing data results of simulation processing of a hardware description language (HDL) model based upon keywords. In accordance with the method, a restriction list associated with the HDL model is received. The HDL model has a maximum number of possible keyword/value pairs sets for which result data can be obtained, and the restriction list specifies a fewer number of keyword/value pair sets for which the result data can be queried based upon at least one keyword. In response to receipt of result data obtained by simulation of the HDL model, the result data are stored within a data storage subsystem by reference to the restriction list, such that particular result data attributable to each of the plurality of keyword/value sets is separately accessible.

Abstract: Translating to a hardware description language (HDL) from an architecture description language (ADL) is disclosed. An architecture description that is written in the ADL and has a hierarchical organization is received. Decoders are generated, described in the HDL, from the architecture description written in the ADL. Control signals are generated, described in the HDL, from the architecture description written in the ADL. The decoders are configured to output the control signals and the control signals are input to functional units in order to preserve the hierarchical organization of the architecture description written in the ADL.

Abstract: Systems and methods for simulating signal coupling in electronic devices are disclosed. In an exemplary implementation a computer program product executes a computer process to simulate a victim signal having a toggling bit pattern relative to a quiet culprit signal. The process also simulates a culprit signal having a toggling bit pattern relative to a quiet victim signal. The computer process generates test results for each simulation and combines the test results to determine effects of signal coupling in an electronic device.

Abstract: A method for generating and evaluating a table model for circuit simulation in N dimensions employing mathematical expressions for modeling a device. The table model uses an unstructured N-dimensional grid for approximating the expressions.

Abstract: A novel hybrid stochastic gradient adaptation apparatus and method for calibrating the gain of an RF or non-RF digitally controlled oscillator (DCO). The adaptation algorithm determines a true stochastic gradient between a forcing function and its corresponding system measure to estimate the system parameters being adapted. A momentum term is generated and injected into the adaptation algorithm in order to stabilize the algorithm by adding inertia against any large transient variations in the input data. In the case of adaptation of DCO gain KDCO, the algorithm determines the stochastic gradient between time varying calibration or actual modulation data and the raw phase error accumulated in an all digital phase locked loop (ADPLL). Two filters preprocess the observable data to limit the bandwidth of the computed stochastic gradient providing a trade-off between sensitivity and settling time.

Abstract: The present invention provides an electronic circuit analyzing apparatus for evaluating the reliability value of an analysis result, an electronic circuit analyzing method, and an electronic circuit analyzing program. The electronic circuit analyzing apparatus comprises an input information storage unit 1 that stores input information, an analytic model creation unit 12 that creates an analytic model of an electronic circuit on the basis of the input information, an analysis unit 3 that calculates an analysis result of the electronic circuit using the analytic model, a partial model reliability value database 21 that defines the accuracy of each part of the analytic model and stores the accuracy value as a partial model reliability value, a partial model influence database 22 that defines the magnitude of influence of each part of the analytic model and stores the influence value as a partial model influence, a reliability value evaluation unit 23 that calculates an analysis result reliability value, i.e.

Abstract: A method for identifying isomorphic cones with sub-linear resources by exploiting reflexivities, the method comprising: identifying a gate g1 and a gate g2 in a netlist; mapping source gates of g1 with any permutation of source gates of g2 by using calls to an isomorphism detection algorithm; determining whether a permutation exists of pairings between the gates sourcing g1 and g2; resetting pairing of gates if the permutation exists; and eliminating pairwise-identical source gates of g1 and g2.

Abstract: In a design system using virtual hardware models, a filtering manager for filtering execution results and determining which software instructions are candidates for restructuring. In some examples, illegal address range instructions are identified based on exception records and restructured software instructions may redirect memory access to an appropriate memory location thereby enabling the use of hardware device drivers in conjunction with hardware emulations, simulations or virtual models without requiring driver source code modifications. Using different filtering criteria, some or all legal and/or illegal memory access software instructions may be redirected to mapped memory locations enabling control over memory access functions. In some cases, debugging tools may be configured or altered to reduce, limit or disable exception handling trace messages, thereby improving overall processing performance by eliminating or reducing unnecessary or burdensome error or trace report generation.

Abstract: The present invention generally relates to hardware development and design, and in particular it relates to a method for simulating hardware. A meta model (22) is compiled for integrating a plurality of n different instantiations (12A, . . . 12N) of the same hardware model, and facilities and signals of different instantiations are resolved by instantiation-specific name space specifications in a code switch (24,26). Thus, computing time is saved because by simulating the meta model, the processor resources, for instance, storage spaces, are utilized more efficiently.

Abstract: The present invention provides a method, an apparatus, and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set up in a simulator. Next, a user sets up an external LBIST block, which comprises pre-verified internal clock and data pattern logic, and connects this block to the logic in the simulation model. The internal clock and data pattern logic provides the input patterns used in OPCG modes of LBIST. This internal clock and data pattern logic is already verified through the design effort. Therefore, the internal pattern generators become the external pattern generators in the simulation model. The external LBIST block applies the external clock and data patterns, and subsequently, the user receives and processes these output patterns to determine if the logic operates correctly.

Abstract: In the field of integrated circuit design and testing, especially directed towards integrated circuits intended to operate at low power, a method and system are provided for circuit design and simulation and testing for mapping portions of a circuit, such as a power domain or portion of a power domain, to a test mode. Thereby only those portions of the circuit which need to be powered up in a particular test mode are powered up both in the design (simulation) phase and in the actual testing. This conserves power usage during actual testing as against powering up all portions of the circuit, which is not desirable during the testing of the circuit after manufacture. This ensures that the power conditions required to excite and observe any circuit faults during testing exist for the power conditions that are applied during, for instance, manufacturing testing.

Abstract: To perform a simulation, a design can be divided into “blocks” described by models. To ensure that data is efficiently transferred from an source model to a destination model, a dynamic first-in first-out (FIFO) can be placed between these models. The initial size of the dynamic FIFO can be set to a relatively small value. To prevent deadlock, the size of the FIFO can be automatically increased in size by increments. In this manner, the memory resources of the FIFO can be tightly controlled. Advantageously, the size of the optimized dynamic FIFO can be used as the desired size of the FIFO implemented in silicon, thereby also ensuring efficient use of silicon resources.

Abstract: A computer readable medium includes computer executable code stored thereon, the code for estimating power consumption of an integrated circuit, comprising code for simulating logic of basic and mega cells of the integrated circuit, code for estimating a current consumed by the mega cells by obtaining logic states for each mega cell, determining an average operation frequency for each logic state, and determining an alternating current component and a direct current component for each logic state to calculate said current consumed by the mega cells for estimating a first value of electric power consumed by said mega cells based on said logic simulations and pre-established power consumption data, code for estimating a current consumed by the basic cells for estimating a second value of electric power consumed by said basic cells based on said logic simulations and pre-established power consumption data and code for combining said first and second values to obtain the power consumption of the integrated circui

Abstract: A method for selecting and/or producing automation hardware which is appropriate or necessary for controlling and/or monitoring a technical process to be automated (10) according to an automation solution is provided. The method includes developing the description of the automation solution, analyzing this description with an analysis tool (20) and selecting and, where applicable, producing respective automation hardware on the basis of the analysis of the description.

Abstract: A method, a system, and an apparatus for quantification of the quality of diagnostic software by applying a coverage tool are provided, wherein the diagnostic software is used for testing a computing system. The method involves executing the diagnostic software in an Integrated Circuit (IC) verification environment. The diagnostic software is executed by a Virtual Computer-processing Unit (V-CPU), which models (Central Processing Unit) CPU of the computing system to be tested.

Abstract: A technique to verify, evaluate, and estimate the performance of an integrated circuit is embodied in a computer software program that is executable by a computer system. When simulating performance, scalars for transient performance are determined for strongly couple components. The technique accurately estimates of the performance (e.g., transient delays) of an integrated circuit, and has fast execution times. The technique is applicable to small circuits having relatively few transistors, and especially well suited for integrated circuits having millions of transistors and components. The technique handles the effects of deep-submicron integrated circuit technology.

Abstract: A method, apparatus and computer program product are provided for facilitating combinatorial logic modeling at an asynchronous clock domain crossing. The modeling technique employs a simulation value of X in combinatorial logic at the asynchronous clock domain crossing of a circuit being modeled to facilitate modeling of a potential combinatorial logic glitch at the crossing during metastability periods thereof. Employing the simulation value of X includes: generating one or more equivalent functional equations for one or more combinatorial paths through the combinatorial logic at the crossing; propagating the simulation value of X through the combinatorial logic using the at least one equivalent functional equation; and then converting the simulation value of X at an output of the combinatorial logic of the asynchronous clock domain crossing to a random logic value for further propagation within the circuit being modeled.

Abstract: A method for building a hierarchical representation of a circuit for simulation includes 1) receiving a source file containing SPICE-like netlist descriptions of the circuit in a flattened representation; 2) generating a primitive database using the source file, where the primitive database includes a geometries-describing section for storing a plurality of primitive subcircuit blocks; 3) generating an instance database using the geometries-describing section, where the instances database includes instance subcircuit blocks corresponding to explicitly-expressed primitive subcircuit blocks with predefined geometric values; 4) generating a simulation database using the instance database, where the simulation database includes simulation subcircuit blocks corresponding to fully-flattened instance subcircuit blocks; and 5) simulating the circuit using the simulation database, the instance database, and the primitive database.

Abstract: There are provided a printed circuit board design instruction support method between a circuit design and a printed circuit board design, a printed circuit board design instruction support device between a circuit design and a printed circuit board design, a Web system, a program, an a computer-readable recording medium which improve the work efficiency of the printed circuit board designing and the quality of the printed circuit board design. By selecting a circuit part to which the design rule is applied, a circuit program and a portion-to-be-checked on the printed circuit board are simultaneously displayed by cooperation between the circuit design system and the printed circuit board design system, thereby reducing the time and labor required for check.

Abstract: A system that facilitates generation of code from a HMI representation of objects in an industrial automation environment. A component analyzes the HMI representation of objects, and a code generation component generates code based at least upon the analyzed HMI object.

Abstract: A method of and an apparatus for designing a test environment providing reliable test signal integrity, and of evaluating performance of the test environment and an electronic device during testing of the electronic device. A virtual test environment is created emulating an actual test environment in which the electronic device is to be tested. A virtual calibration of the virtual test environment may be performed, to more closely emulate the actual test environment. A virtual device emulating the actual electronic device is implanted into the virtual test environment, and that virtual device is stimulated with an input test signal emulating the actual input signal that is applied to the actual electronic device in the actual test environment. The integrity of the input test signal and the resulting output signal is evaluated.

Abstract: A method and programmable oscillator model are provided for implementing high frequency clock generation for a simulation environment. The programmable oscillator model includes an internal ring oscillator for generating a high frequency clock. The internal ring oscillator counts a number of clocks and determines when to switch the reference clock. For example, a clock edge time is recorded as a two-byte field, where a high byte records a programmable number of fast clocks per clock edge, and a low byte records a fraction of a clock edge. Each time the reference clock switches a count down counter is loaded with the high byte, and the low byte is added to the current fraction. If the fraction has a carry, an additional fast clock is added to the count down counter.

Abstract: Disclosed is a permanent recloser simulator feature for use in a single-pole trip capable recloser control. The permanent recloser simulator feature includes a first logic circuit capable of enabling and disabling operation of the permanent recloser simulator feature in response to receipt of a binary logic signal, and a second logic circuit coupled to the first logic circuit where the second logic circuit is configured to provide an indication of a status of a first pole to a logic engine of the single-pole trip capable recloser control. The permanent recloser simulator feature may further include a third logic circuit associated with a second pole, and a fourth logic circuit associated with a third pole where both are coupled to the first logic circuit. Disabling means of the first logic circuit allow the first, second, third and fourth logic circuit to permanently reside in logic of the recloser control.

Abstract: A system and method for testing a development device includes extracting multiple parameters of the development device from a product specification for the development device. The parameters being arranged in a predetermined first order. The parameters are stored in a testing data file. The testing data file can be input into a test bench system being coupled to the development device. The test bench system can test the development device.

Abstract: An event queue for use with a software-enabled logic simulation tool can include a heap array and a hash table data structure. The heap array can include time slots organized such that each time slot conforms to heap properties which specify, at least in part, that a root node of the array indicates a time slot having a minimum simulation time value. The hash table data structure can include a plurality of entries, wherein selected ones of the entries specify references to at least one of the time slots.

Abstract: An electrical circuit can be described with a reference model that has a plurality of states and a plurality of state transitions. Acceptable and/or unacceptable instruction sets are predefined for each state. Acceptable and unacceptable instruction sets are generated randomly in succession from the reference model and applied to a mapping of the electrical circuit for processing. By comparing the instruction sets processed by the mapping of the electrical circuit with the instruction sets determined from the reference model, conclusive information relating to the mapping of the electrical circuit is obtained.

Abstract: A code coverage tool provides that a netlist is instrumented with gates for providing a comparison of an output of the design gates on one cycle with their output on a next cycle to determine if the gate was exercised during an emulation.

Abstract: A method of simplifying a logic circuit for enabling cycle-by-cycle equivalence checking is provided. To accomplish this, first, a logic circuit is identified to be a variable delay circuit or a fixed delay circuit. If the logic circuit is a variable delay circuit, it is converted to a fixed delay circuit by using additional circuitry to obtain a fixed delay circuit. If the fixed delay circuit is a logic circuit that performs multiple cycle computations, it is converted to a logic circuit that performs the same computation in a single cycle. Circuit acceleration includes concatenating multiple copies of the fixed delay circuit. After performing circuit acceleration on all sub-circuits in the fixed delay circuit, a combined accelerated circuit is obtained. Thereafter, redundant flip-flops are identified and removed from the combined accelerated circuit and the combined accelerated circuit is optimized.

Abstract: While simulating a circuit described by the netlist, a circuit simulator produces a dump file containing a set of waveform data sequences, each corresponding to a separate signal within the circuit, and representing states of its corresponding signal at a succession of times during the circuit simulation. Based on a mapping of the waveform data sequences to lines of a bus, and on transaction data models describing characteristic signal patterns appearing on the bus during each type of transaction that can occur on the bus, a transaction analysis system identifies transactions that occurred on the bus during the simulation. The transaction analysis system also notes a time during the circuit simulation in which each transaction occurred, and generates a display including a separate representation of each identified transaction positioned to represent the time the transaction occurred.

Abstract: An encryption process is employed in the LSI design so as to improve confidentiality of the circuit design data over conventional examples. In the encryption process, confidential circuit design data is encrypted to produce encrypted design data and a cipher key. The encrypted design data is provided to the user who conducts a design/verification process. The key is also provided as required. In the design/verification process, the encrypted design data is subjected to various processes without disclosing the contents of the original circuit. In a decoding process, the encrypted design data subjected to the design/verification process is decoded to produce original circuit design data.

Abstract: A technique for performing signal integrity analysis of a system includes providing a stimulus pattern and a model of the system and performing analog simulation of the model utilizing the stimulus pattern. The stimulus pattern includes sequences of signal transitions with associated transition times and the sequences of signal transitions conform to a bus protocol and the associated transition times are according to characteristics of the system. The stimulus pattern is generated by initializing each of the sequences of signal transitions to an initial signal value and the associated transition times to an initial time, generating subsequent signal values and subsequent transition times by applying protocol rules and calculating timing adjustments for each of a list of transactions; the subsequent signal values and subsequent transition times to be added to the sequences of signal transitions.

Abstract: An extractor extracts descriptions unexecuted in the logic simulation according to code coverage information for the circuit description. An examiner examines whether or not there is a possibility of executing the extracted unexecuted descriptions. A prohibited-input-checker generator generates a test pattern. The test pattern is to execute descriptions including unexecuted descriptions that there is a possibility of executing and excluding unexecuted descriptions that there is no possibility of executing as determined by the examiner. The prohibited-input-checker generator also generates a prohibited-input checker to check whether or not an input pattern of a logic simulation to be carried out is equal to an input pattern of the test pattern to execute the unexecuted description if the test bench is regarded as a prohibited input under a specification at a logic simulation using the test pattern to execute the unexecuted description.

Abstract: The present invention includes a method for modeling devices having different geometries, in which a range of interest for device geometrical variations is divided into a plurality of subregions each corresponding to a subrange of device geometrical variations. The plurality of subregions include a first type of subregions and a second type of subregions. The first or second type of subregions include one or more subregions. A regional global model is generated for each of the first type of subregions and a binning model is generated for each of the second type of subregions. The regional global model for a subregion uses one set of model parameters to comprehend the subrange of device geometrical variations corresponding to the G-type subregion. The binning model for a subregion includes binning parameters to provide continuity of the model parameters when device geometry varies across two different subregions.

Abstract: A verification method foe an integrated circuit includes identifying an equivalence class including a set of candidate gates suspected of exhibiting equivalent behavior and identifying one of the candidate gates as a representative gate for the equivalence class. Equivalence gates of an XOR gate are sourced by the representative gate and a candidate gate. A speculatively reduced netlist is generated by replacing the representative gate as the source gate for edges sourced by a candidate gate in the original design. The speculatively reduced netlist is then used either to verify formally the equivalence of the gates by applying a plurality of transformation engines to the speculatively reduced netlist or to perform incomplete search and, if none of the equivalence gates is asserted during the incomplete search, any verification results derived from the incomplete search can be applied to the original model.

Abstract: A method for simulating a circuit includes representing the circuit as a hierarchically arranged set of branches, including a root branch and a plurality of other branches logically organized in a graph. The method further includes arranging the subcircuits from the hierarchically arranged set of branches into one or more groups, determining a data structure for each subcircuit in a group that supports a combination of selectively flattened and selectively expanded group of subcircuits, selecting a subcircuit as a simulation leader and identifying remaining subcircuits as followers in the group, where the simulation leader have states substantially equivalent to the followers, simulating the respective simulation leader of each group using a selectable simulation driver, and replicating simulation results of the respective simulation leader of each group to its followers.

Abstract: A method for transforming a behavioral specification involves converting the behavioral specification into a diagram representation, converting a delay from the diagram representation if the behavioral specification comprises a delay, generating a compliant cycle diagram from the diagram representation, and deriving a cycle equivalent behavioral specification from the compliant cycle diagram.

Abstract: Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.

Abstract: A statistical delay simulation apparatus includes: a circuit simulator for simulating a circuit operation of a circuit cell constituting an LSI; a statistical delay library generator for driving the circuit simulator and generating, based on a process parameter and the like, a statistical delay library in which the dependency of a delay variation on a predetermined operation condition in each circuit cell is described; a delay calculator for calculating a delay amount of each circuit cell to generate a statistical LSI delay information file containing data on the calculated delay amount; and a static timing analyzer for simulating, based on data of the statistical LSI delay information file, an operation with a delay variation of the LSI to generate a statistical LSI delay analysis result file.

Abstract: A method, data processing system, and program product for building an instrumented simulation model of a digital design are disclosed. According to the method, a model build tool locates, within design data collectively defining a simulation model of the digital design, a definition of a configuration construct specifying a relationship between values of one or more configuration latches within the digital design and settings of the configuration construct. In response to locating the definition of the configuration construct, the model build tool automatically creates an instrumentation entity within the design data. The instrumentation entity has one or more inputs logically coupled to the one or more configuration latches and one or more outputs for providing signals indicating characteristics of the configuration construct during simulation.

Abstract: The present invention provides a method and mechanism for simulating complex digital circuits using hybrid control and data flow representations. Specifically, the invention provides a method of simulating a digital circuit in such a way that the simulation is stopped at desired functions for subsequent analysis. A hardware design code describing the digital circuit is converted to an assignment decision diagram (ADD) representation that is then annotated with one or more control nodes that are used for maintaining control flow through a simulator. In this way, one or more break points are created that allow the simulator to stop at associated points in the simulation.

Abstract: A distributed simulation system is provided in which timesteps may be divided into a first phase (referred to as the zero time phase herein) and a second phase (referred to as the real time phase herein). In the first phase, each distributed simulation node in the system may process one or more received commands without causing the simulator to evaluate the model in that distributed simulation node. In the second phase, each distributed simulation node may cause the simulator to evaluate the model in response to a command supplying one or more signal values to the model. In one embodiment, the second phase may iterate the evaluation of the model for each command received which supplies signal values. Each iteration may optionally include transmitting a command including the output signal values produced by the model during that iteration.

Abstract: In accordance with the present invention there is provided a method for performing a glitch check in simulating a circuit. Current maximum and minimum values for optimization parameters of the circuit are determined. Next, a signal pulse characteristic for the circuit simulation is determined based on the maximum and minimum optimization parameters. A current averaged optimization parameter is determined from the current maximum and minimum optimization parameters. A prime criterion parameter is calculated based on the optimization parameters and the signal pulse characteristic value. If the prime criterion parameter converges into a specified range then measurement results from the circuit simulation are parsed and reported as final. If the prime criterion parameter does not converge, then the process continues by recalculating the optimization parameters until the prime criterion parameter converges.

Abstract: An aspect of the present invention provides a semiconductor integrated circuit verification system that includes a compiler configured to receive circuit descriptions of a semiconductor integrated circuit to be verified and create a circuit database, a circuit analysis unit configured to receive the circuit database to analyze the circuitry inside the semiconductor integrated circuit based on the circuit database, the circuit analysis unit configured to determine the timing at which the abstraction level of the circuit is switched and generate a simulation object, and a simulation execution unit configured to receive the simulation object and conduct a simulation of the semiconductor integrated circuit based on the simulation object.

Abstract: A method for routing a message from a source node to a destination node, where the source node and the destination node are connected by a plurality of nodes in a cycle-based system, is disclosed. The method includes generating a maze data structure including the plurality of nodes, where each of the plurality of nodes is associated with a dimension corresponding to time, and routing the message from the source node to the destination node using the dimension corresponding to time.

Abstract: Methods and apparatus are provided for efficiently generating test components for testing and evaluating a design under test. As a design is being configured, generated test components are made available. In one example, test components are automatically generated and included in a simulation testbench based on selected components in the design. Generally, the test components complement the selected components in the design. Moreover, the test components can be automatically seeded with initial contents.

Abstract: A method and apparatus for accumulating arbitrary length strings of input values, such as floating point values, in a layered tree structure such that the order of adds at each layer is maintained. The accumulating utilizes a shared adder, and includes means for directing initial inputs and intermediate result values.

Abstract: Method and apparatus for simulating operations of a circuit design that includes high-level components and HDL components. The high-level components of the design are simulated in a high-level modeling system (HLMS), and the HDL components of the design are simulated with an HDL simulator. Data values are converted from a data type of the HLMS to a logic vector compatible with the HDL simulator for each data value to be input to the HDL simulator, and a logic vector is converted from the HDL simulator to a data value of a data type compatible with the HLMS for each logic vector output from the HDL simulator. Events are scheduled for input to the HDL simulator as a function of the time of HLMS events and a maximum response time of the HDL components.

Abstract: Disclosed herein is a method of storing data results of simulation processing of a hardware description language (HDL) model based upon keywords. In accordance with the method, result data obtained by simulation of at least one HDL model are received. In association with the result data, a plurality of value sets is received, where each value set includes at least one keyword having an associated value. Each keyword identifies a parameter external to the HDL model that affected the result data. The data results are stored within a data storage subsystem in association with the plurality of value sets such that particular result data are attributable to particular ones of the plurality of value sets. In one embodiment, a keyword table is built in the data storage system that indicates which data subdirectories store result data associated with particular value sets. The result data can then be queried based upon selected keywords of interest, for example, by reference to the keyword table.

Abstract: A method for identifying predictable data sharing locations includes generating a testcase thread of code, creating a list of data lines used by the generated testcase thread of code, and generating a list of predictable data sharing locations based on the data line list.

Abstract: Various methods and apparatuses are described in which a software programming interface connects one or more functional checker components and one or more protocol checker components to an interconnect monitor component. A computer readable medium stores code for the one or more functional checker components for Intellectual Property (IP) cores, one or more protocol checker components, the interconnect monitor component, and the software programming interface. The monitor component has code to build data structures containing protocol data types requested by a checker component and code on where to deliver data based upon a particular type of data requested by the checker component.