Abstract: A method and system for short-circuit current modeling in CMOS circuit provides improved accuracy for logic gate power dissipation models in computer-based verification and design tools. The model determines the short circuit current for each complementary pair within a CMOS circuit. Input and output voltage waveforms provided from results of a timing analysis are used to model the behavior one device of the complementary pair. The device is selected as the limiting device (the device transitioning to an “off state) from the direction of the logic transition being modeled, which is also the device that is not charging or discharging the output load. Therefore, the current through the selected device can be determined from the input and output waveforms and is equal to the short-circuit current prior to the saturation of the selected device.

Abstract: A method for positioning components of a system onto a target device utilizing programmable logic devices (PLDs) is disclosed. A location is determined for a user defined region on the target device that allows the system to satisfy timing constraints.

Abstract: A method of preparing a circuit model for simulation comprises decomposing the circuit model having a number of latches into a plurality of extended latch boundary components and partitioning the plurality of extended latch boundary components. Decomposing and partitioning the circuit model may include decomposing hierarchical cells of the circuit model, and using a constructive bin-packing heuristic to partition the plurality of extended latch boundary components. The partitioned circuit model is compiled, and simulated on a uni-processor, a multi-processor, or a distributed processing computer system.

Abstract: In at least one hardware definition language (HDL) file, a design entity containing a functional portion of a digital system is specified. The design entity logically contains a plurality of configuration latches each having multiple different possible latch values. The latch values of the plurality of configuration latches collectively define at least a portion of a configuration of the functional portion of the digital system. With a statement in the at least one HDL file, a read-only Dial entity is associated with the plurality of configuration latches. The read-only Dial has at least one output and a mapping table indicating a mapping between each of a plurality of possible output values that can be present at the output and a respective corresponding setting of the read-only Dial. The setting of the read-only Dial indicates which of a plurality of different possible configurations is represented by the latch values of the plurality of configuration latches.

Abstract: A method and system for dynamic characterization observability using functional clocks for system or run-time process characterization. Silicon characterization circuitry may be read after silicon chips have been assembled in a package and installed in a system. A characterization circuit comprising one or more oscillators generates signal pulses, wherein the signal pulses represent a frequency of a circuit in the processor chip. A sampler circuit is connected to the characterization circuit, wherein the sampler circuit counts the number of the signal pulses from the characterization circuit within a predetermined time period. A control unit is connected to the sampler circuit, wherein the control unit comprises macros for collecting count data from the one or more oscillators to determine the silicon characterization. Based on the silicon characterization, the optimal operating frequency of the processor chip may be identified, as well as possible lifetime degradation of circuits on the chip.

Abstract: A system and method for providing interface compatibility between two hierarchical collections of integrated circuit (IC) design objects. Upon establishing an associative correspondence between a design object from a first hierarchical collection and a design object from a second hierarchical collection, a port compatibility map is generated based on determination that a particular associative correspondence includes a pair of design objects, one from each hierarchical collection, that are port-compatible. Thereafter, the port compatibility map is reduced to determine a set of design object pairs that allow interface-compatible replaceability between the first and second hierarchical collections.

Abstract: Analyzing interactions between vias in multilayered electronic packages that include at least two spaced-apart conducting planes, and multiple vias that connect signal traces on different layers. Voltages at active via ports are represented as magnetic ring current sources, which generate electromagnetic modes inside the plane structure. Substantial electromagnetic coupling between vias occurs. A full-wave solution of multiple scattering among cylindrical vias in planar waveguides is derived using Foldy-Lax equations. By using the equivalence principle, the coupling is decomposed into interior and exterior problems. For the interior problem, the dyadic Green's function is expressed in terms of vector cylindrical waves and waveguide modes. The Foldy-Lax equations for multiple scattering among the cylindrical vias are applied, and waveguide modes are decoupled in the Foldy-Lax equations.

Abstract: A method of improving performance of a dual Vt integrated circuit is disclosed in which a first value is calculated for each transistor of the integrated circuit that has a first threshold voltage level. The first value is based at least in part on delay and leakage of the circuit calculated as if the corresponding transistor had a second threshold voltage level. One transistor is then selected based on the first values. The threshold voltage of the selected transistor is then set to the second threshold voltage level. The area of at least one transistor within the circuit is modified, and the circuit is then sized to a predetermined area. The process may then be repeated if the circuit performance fails to meet a defined constraint.

Abstract: A method for automatically mapping state elements between a first circuit and a second circuit is described. The method proceeds by comparing, in a structural phase, structural features of state elements in the first circuit to structural features of state elements in the second circuit for equivalence. Mappings between state elements of the first circuit and the second circuit are determined based on the comparison of structural features. “Don't care” input conditions are then accounted for prior to determination of functional features. During an inversion detection phase, the polarity of the mappings found in the prior structural phase are determined. A functional phase follows in which the functionality of state elements in the first circuit are compared to the functionality of state elements in the second circuit for equivalence using a three-valued random simulation and further mappings are determined based upon the functional comparison.

Abstract: A method for inferring a requested data input function of a sequential cell from a library of candidate cells, wherein the requested cell and the candidate cell are expressed as polynoms and then divided. The method generates polynomial expressions of the inhibition, transformation and inference steps necessary to convert the candidate cell into the requested cell. The use of polynomial expression and division greatly reduces the number of rules necessary to accommodate the varying combinations of requested cell and candidate cell functions.

Abstract: A method and system for minimizing redundancy in collected harvest event testcases from a batch simulation farm which includes a harvest testcase server that collects simulation data for a simulation model from at least one simulation client. In accordance with the method of the present invention, a testcase is executed on the simulation model within a simulation client. Responsive to the testcase triggering a harvest event, the harvest event is compared with a list of harvest events that have previously been triggered within the simulation model. In response to determining that the harvest event has not been previously triggered within the simulation model, the testcase is delivered to the harvest testcase server.

Abstract: An exemplary method and system for generating integrated circuit (IC) simulation information regarding the effect of design and fabrication process decisionn includes creating and using a data store of profile-based information comprising metrology signal, structure profile data, process control parameters, and IC simulation attributes. An exemplary method and system for generating a simulation data store using signals off test gratings that model the effect of an IC design and/or fabrication process includes creating and using a simulation data store generated using test gratings that model the geometries of the IC interconnects. The interconnect simulation data store may be used in-line for monitoring electrical and thermal properties of an IC device during fabrication. Other embodiments include utilizing a metrology simulator and various combinations of a fabrication process simulator, a device simulator, and/or circuit simulator.

Abstract: A method of providing accelerated post-silicon testing for a silicon hardware includes computing a simulation cumulative record of state using a plurality of test instructions and a cycle breakpoint, performing a simulation of an instrumented logic design using the plurality of test instructions and the cycle breakpoint, manufacturing the silicon hardware using the instrumented logic design, computing a silicon cumulative record of state by executing the plurality of instructions using the silicon hardware; and comparing the simulation cumulative record of state to the silicon cumulative record of state.

Abstract: A preemptive reloading technique is employed in a test program generator. Initialized resources are reset with needed values by reloading instructions. The actual reloaded value is chosen later, when the instruction that actually needs the value is generated. The test program generator distances the reloading instruction from the instruction that actually needs the value, thus making it possible to avoid fixed test patterns and to generate interference-free test segments during design verification.

Abstract: Logic simulation includes storing a first state to identify in a simulation of a logic design whether a node included in the logic design has a logic high value Logic simulation also includes storing a second state to identify in simulation of the logic design whether the node has a logic low value and storing a third state to identify in simulation of the logic design whether the node has an undefined state. The logic simulation determines an output of the node in simulation of the logic design based on the first state, the second state, and the third state.

Abstract: The operating characteristic of a transistor, modeled by a resistive element having fixed resistance and a power source voltage that varies with time, is segmented into a linearity region in which a current increases as a gate potential varies and a saturation region in which the current gradually decreases as the gate potential remains at a constant level, so that gradual decrease in current in a saturation region of the transistor is properly reflected and a delay time is estimated in a precise manner.

Abstract: A system and method for creating a graphical program including a plurality of portions to be executed sequentially. User input may be received, e.g., during development of the graphical program, wherein the user input indicates a desire to specify a plurality of portions of graphical source code to be executed sequentially. In response, a plurality of frames may be displayed in the graphical program, such that two or more frames from the plurality of frames are visible at the same time. A portion of graphical source code may be included in each frame in response to user input. The plurality of frames may define an execution order for the corresponding portions of graphical source code, such that during execution of the graphical program, the portions of graphical source code are executed sequentially according to this execution order. In the preferred embodiment, all of the frames are visible at the same time, thus giving the program developer a complete view of the graphical program.

Abstract: The invention is a sequential machine for solving boolean satisfiability (SAT) problems for functions of n variables and m clauses in linear time with complexity O(m), independent of the number of variables in the function. With current hardware technology, a value of n=32 variables can be achieved. The machine can serve as a basic building block to develop faster SAT solvers.

Abstract: A method for designing an electronic system having at least one digital part. The method includes representing a behavioral description of the system as a first set of objects with a first set of relations therebetween. Furthermore, the method includes refining said behavioral description into an implementable description of said system, said implementable description being represented as a second set of objects with a second set of relations therebetween. Also, the method includes retaining at least one of said second objects for reuse in the design of a second electronic system.

Abstract: Simulating a logic design having combinatorial logic and state logic includes representing the combinatorial logic and the state logic using separate graphic elements, identifying clock domains for the combinatorial logic and the state logic using the separate graphic elements, generating computer code that simulates operation of portions of the logic design, the computer code being generated based on the clock domains, and associating the computer code with graphic elements that correspond to the portions of the logic design.

Abstract: A circuit designing apparatus comprising: unit for specifying the changed points of the circuit description automatically in predetermined unit, and classifying the plural test vectors into those related with the changed points and others not; wherein the second and subsequent logic verification processes are executed by using only the test vectors relating to the changed points. As a result, the time required for circuit design can be substantially curtailed.

Abstract: The high-frequency-corresponding simulation apparatus includes a control section that calculates a sum of the DC resistance value and skin resistance value of each of a plurality of elements corresponding to wiring patterns in accordance with circuit deign information, sorts resistance values corresponding to the elements by using a high-frequency element delay as a key when the total resistance value is equal to or larger than a first threshold value, integrates resistance values starting with a resistance value having the smallest high-frequency element delay, and which determines whether the result of the integration reaches a value immediately before a second threshold value whenever the integration is executed and a RLC-model analysis section.

Abstract: Method and system for modeling and automatically generating an embedded system from a system-level environment. A plurality of user-selectable system-level design objects are provided in the system-level environment. Each system-level design object is defined by a system-level function and is selectable by a system-level designer. A plurality of hardware-level design objects are also provided. Each hardware-level design object is configured to generate a hardware definition of a hardware-level function. Each system-level design object maps to one or more hardware-level design objects. A processor design object is provided which defines a processor. In response to selections made by the designer, a system-level design is instantiated in a system-level design file. The system-level design includes user-selected ones of the system-level and processor design objects.

Abstract: A method for functional verification of a design for a parallel processing device includes receiving a sequence of single instructions from a dynamic test program generator, and assembling a plurality of the instructions from the sequence into an instruction word, in accordance with predetermined rules applicable to the parallel processing device. The instruction word is input to a simulator of the parallel processing device so as to determine a response of the device to the instruction word.

Abstract: A method for compiling a cycle-based design involves generating a parsed cycle-based design from the cycle-based design, elaborating the parsed cycle-based design to an annotated syntax tree, translating the annotated syntax tree to an intermediate form, and converting the intermediate form to an executable form.

Abstract: A debugger produces a display based on instructions executed by a circuit simulator or verification tool and on waveform data produced by the simulator or verification tool when executing the instructions. The instructions include a set of statements, each corresponding to a separate circuit signal generated by a circuit and each including a function defining a value of the circuit signal as a function of values of other circuit signals. The simulator evaluates the statements at various simulation times to compute signal values at those simulation times. The waveform data indicates signal values the simulator computes when evaluating the statements. The debugger display includes a set of statement event symbols, each corresponding to a separate evaluation of a statement and each positioned in the display to indicate a simulation time at which the simulator evaluated the statement.

Abstract: A method for evaluating a logic state of a design node involves compiling a logic design to generate an annotated symbol table and a levelized design, obtaining a logic evaluation cost from the levelized design, locating a strategic node using the logic evaluation cost, marking the strategic node, and computing the logic state of the design node using the annotated symbol table, the strategic node, and the levelized design.

Abstract: A method for generating a test vector for functional verification of circuits includes providing a representation of a circuit, where the representation includes a control logic component and a datapath logic component. The method also includes reading one or more vector generation targets, and performing word-level ATPG justification on the control logic component to obtain a control logic solution. The method further includes extracting one or more arithmetic functions for the datapath logic component based on the control logic solution, and solving the one or more arithmetic functions using a modular constraint solver. The modular constraint solver is based on a modular number system.

Abstract: A method and system for providing simulation of an integrated circuit during development of the integrated circuit is disclosed. The integrated circuit has an island that includes an interface. The method and system include a snooper, a checker and a generator. The snooper is coupled with an interface and is for obtaining an output provided by the island during simulation. The checker is coupled with an interface and is for checking the output to determine whether the output is a desired output. The generator is coupled with an interface and is for providing an input to the interface during simulation. The generator is coupled with a test case that directs the generator.

Abstract: Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.

Abstract: A modeling method and a simulation method enable a circuit board to undergo modeling without deterioration of simulation precision while describing with no matrix shape. A circuit simulator analyzes power/ground noise of a circuit board with single current change source. A process regards the circuit board as an aggregate of thin doughnut boards of concentric circle shape with the current change source as the center, subsequently, approximating the aggregate of the doughnut boards to be an aggregate of rectangular boards with respective circumferences of the doughnut boards as widths and respective cut-lengths of the same as lengths, then forming respective transmission line models taking respective rectangular boards of the aggregate of the rectangular boards as the transmission line, thus connecting respective transmission line models in series to make it a simulation model of the circuit board.

Abstract: The present invention relates generally to a logic arrangement, system and method which aid in a design of a fieldbus network configuration. In particular, the present invention includes certain functions for an automatic generation and verification of block and device tags, function block verification and modifications for function block type consistency based on information in the block profile, automatic allocation of function blocks into devices by an off-line scheduler, and a control strategy configuration system (which uses artificial intelligence to generate and maintain a fieldbus design knowledge-base). Accordingly, the user is able to easily configure the fieldbus network and devices residing thereon in an effective manner, as well as use the previously used configurations for establishing new fieldbus networks.

Abstract: A method of automated enumeration of one or more devices comprising the steps of (A) generating an enumeration of a plurality of fuses and (B) compiling data for each one of said plurality of fuses, wherein the data comprises (i) one or more schematic path data, (ii) one or more simulation path data and/or (iii) one or more physical location data.

Abstract: A system is provided to increase the accessibility of registers and memories in a user's design undergoing functional verification in a hardware-assisted design verification system. A packet-based protocol is used to perform data transfer operations between a host workstation and a hardware accelerator for loading data to and unloading data from the registers and memories in a target design under verification (DUV) during logic simulation. The method and apparatus synthesizes interface logic into the DUV to provide for greater access to the registers and memories in the target DUV which is simulated with the assistance of the hardware accelerator.

Abstract: A method for accelerating hardware simulation is presented wherein cycle based simulations of digital system designs are generated by raising the level of abstraction in a hardware simulation environment. Behavioral models of the digital system components are created in a high level general purpose programming language. Function calls created in a high level general purpose programming language provide a transaction based communication interface. During a simulation of the system design, the behavioral models communicate with each other through the transaction based communication interface. Additionally, the behavioral models employ an execute and update method of instruction processing that generates cycle accurate information for the simulation.

Abstract: A method, named the product terms method that allows to implement and/or to change dynamically the logical behavior of any combinational or synchronous sequential circuits has been presented. The method uses for every product term of logical equations, expressed as a sum-of-product, three memory words: mask word, product word and function word. The words of all product terms are ranged in a table, which characterize the logical behavior of the circuit. The invention provides the hardware structure of several new types of VSLI circuits, having re-configurable logic behaviors. A first embodiment implements any type of multiple output combinational circuit, a second embodiment implements any synchronous sequential circuit with only clock input and, a third embodiment implements any synchronous sequential circuit s with data inputs and clock input.

Abstract: A method for selecting a process for forming a device, includes generating a plurality of equations using a response surface methodology model. Each equation relates a respective device simulator input parameter to a respective combination of processing parameters that can be used to form the device or a respective combination of device characteristics. A model of a figure-of-merit circuit is formed that is representative of an integrated circuit into which the device is to be incorporated. One of the combinations of processing parameters or combinations of device characteristics is identified that results in a device satisfying a set of performance specifications for the figure-of-merit circuit, using the plurality of equations and the device simulator.

Abstract: A system is provided for determining voltage at the output of a gate in an integrated circuit. The system locates a gate within the integrated circuit and looks up a set of output current waveforms as a function of time for different effective capacitances at the gate's output. The system applies each output current waveform to its corresponding effective capacitance to calculate a first set of output voltages and applies each output current waveform to a model of the net coupled to the output of the gate to calculate a second set of output voltages. For each time step in a series of time steps, the system selects an output current waveform for which a voltage in the first set of output voltage waveforms matches a voltage in the second set of output voltage waveforms. The system uses the selected output current waveform to determine the output voltage.

Abstract: A method, system, and data structure for processing and managing a simulation event during model simulation. In accordance with the present invention, a design entity identifier is associated with the simulation event within a simulation event declaration statement. The event declaration statement includes a design entity name field containing data representing an entity name of a design entity from which the simulation event is generated. Occurrences of the simulation event are evaluated within said simulation model in accordance with the design entity identifier. An instantiation identifier field may be included within the event declaration to enable hierarchical and non-hierarchical processing of the event.

Abstract: A system designed, including commercially distributed modules protected as intellectual property (IP), is verified in a manner that the IP provider and the user communicate with each other over a communication line to complete the system design verification. A system verification equipment to be operated by the IP provider receives from the system designer across the communication line an input vector at time n to a module provided to the system designer who designed the system integrated using one or more provided IP modules. After simulating the module operation with the input vector, the verification equipment returns an output vector obtained at time n+1 to the system designer over the communication line. The verification equipment examines the input vectors to the provided IP modules and records statistics information thereof, based on which the provider will quantitatively understand how the provided modules have been used.

Abstract: A simulator and/or simulation process operates by receiving a message from a system; comparing the received message to information stored in a response file used to simulate system response; and simulating a response to the system by outputting a response stored in association with a stored message matching the received message. The response file includes at least one message, a message marker associated with each message, at least one response associated with each message, and an end-of-response marker associated with each response. At least two responses are stored in association with a message, and the at least two responses are sequentially output in response to sequential receipt of the message. As such, the simulator can reply to any message by looking up its associated response in the response file. If more than one associated response appears in the response file, receipt of identical messages will illicit sequential and differing responses.

Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract: A method of efficiently simulating logic designs comprising signals that are capable of having more than two unique decimal values and one or more unique drive states, such as designs based upon the new N-nary logic design style, is disclosed. The present invention includes a signal model that models N-nary signal value, drive strength, and signal definition information in a specific format that supports the ability of the simulator to simulate the operation of the N-nary logic gates such as adders, buffers, and multiplexers by arithmetically and logically manipulating the unique decimal values of the N-nary signals. The simulator comprises an input logic signal model reader, an arithmetic/logical operator, an output logic signal model generator, and an output message generator that generates one or more output- or input-signal-specific output messages that pack relevant simulation data into a format optimized to the architecture of the simulation host.

Abstract: A circuit simulator simulates a circuit described by a circuit logic model as having a set of clocked registers interconnected by un-clocked logic to produce waveform data indicating states of each circuit input signal and of each register output signal as functions of clock signal edge timing. The waveform data and the logic model are then processed to produce a temporal schema model characterizing the circuit's logic and behavior. A display based on the temporal schema model depicts circuit behavior using separate symbols to represent successive circuit input signal states and register output signal states at various times during the simulation. The same display also graphically depicts fan-in or fan-out logical relationships by which circuit input signal states and register output signal states influence register input signal states.

Abstract: A method and system for disabling an instrumentation event in a simulation model within a batch simulation farm in which a simulation client communicates with an instrumentation server to process simulation data with respect to the simulation model. An instrumentation event disable list is assembled within the instrumentation server. The assembly of the event disable list includes identifying an instrumentation event to be disabled during simulation processing of the simulation model, and delivering to the instrumentation server an instrumentation event name corresponding to the instrumentation event to be disabled. Prior to simulating the simulation model within the simulation client, the instrumentation event disable list is retrieved from the instrumentation server, and instrumentation events are disabled as specified within the instrumentation event disable list.

Abstract: An integrated circuit development library is provided that characterizes several different logic device cells. The library specifies a number of different timing relationships for each of the logic device cells. These timing relationships are evaluated for each of the logic device cells at a first derating condition with a first simulator to provide a first set of derated condition values. The first set of derated condition values each correspond to one of the timing relationships evaluated. A first derating factor is calculated from the first set of derated condition values for estimating derated performance of an integrated circuit with a second simulator. This integrated circuit is developed from one or more of the logic device cells of the library.

Abstract: A design tool and method characterizes a circuit at a hardware level description. A behavioral level description of the circuit is created. Symbolic equations for components of the behavioral level description are created. The behavioral level description is partitioned by inserting a marker component into the behavioral level description of the circuit to simplify subsequent processing used to prove equivalence between the behavioral and hardware level descriptions. The symbolic equations are back-substituted until output variables are expressed in terms of input variables that determine the output variables. The marker component is defined using a unique symbolic name. Current time counts of each clock cycle are used to compute an index for the marker component. The behavioral level description is transformed to produce symbolic and numeric files for compilation to gates and proof of functionality.

Abstract: The present invention is a design apparatus compiled on a computer environment for generating from a behavioral description of a system comprising at least one digital system part, an implementable description for said system, said behavioral description being represented on said computer environment as a first set of objects with a first set of relations therebetween, said implementable description being represented on said computer environment as a second set of objects with a second set of relations therebetween, said first and second set of objects being part of a design environment.

Abstract: Each circuit simulation performed on unique layout of circuit devices generates a design point (DP) that includes device variable values and performance goal values. Circuit models for at least one performance goal are determined as a function of a first subset of the DPs. A performance goal value is determined for each circuit model based on the device variable values obtained from a second subset of the DPs. Errors are determined between the thus determined value of each performance goal and values of the corresponding performance goals obtained from the second subset of the DPs. Input values of device variables are processed with at least one of the circuit models having the smallest error associated therewith to determine therefor a performance goal value. A layout of the circuit devices is generated based on the input device variable values associated with at least one of the thus determined performance goals.

Abstract: In a method and apparatus for carrying out circuit simulation which performs circuit simulation on a circuit to be simulated, a plurality of partial circuits to be inspected for equivalence in order to check if they exhibit equivalent operational characteristics are extracted from the circuit to be simulated, and the intensity of the influence of an external terminal of the circuit to be simulated is assessed by tracing paths linking the external terminal and given terminals of the partial circuits. Moreover, based on the configurations of the partial circuits, the connectional relationships of corresponding input terminals of the partial circuits, the operational characteristics of corresponding component elements of the partial circuits, and the intensity of the influence of the external terminal, the plurality of partial circuits are inspected for equivalence in order to detect partial circuits exhibiting equivalence.