Abstract: Experimental studies can be conducted in an environment where one or more laboratories communicate with a network instrument monitoring center over a network. In such an environment, an individual at the network instrument monitoring center can be enabled to simultaneously oversee studies at multiple remote laboratories, rather than requiring dedicated individuals at each of the laboratories to oversee the studies at their respective labs.

Abstract: A technique for operating a system including a plurality of processors and a shared resource includes executing a first instruction by a first processor of the plurality of processors. The first instruction generates a reservation of the shared resource for the first processor. The technique includes, after generating the reservation of the shared resource for the first processor, executing a spin lock by the first processor until successful execution of a second instruction acquires a lock of the shared resource. The technique includes disabling interrupts of the first processor in response to an indicator of the successful execution of the second instruction. The first instruction may be a load and reserve instruction and the second instruction may be a conditional store instruction.

Abstract: Aspects of the disclosure provide for mechanisms for managing related devices for virtual machines in a computer system. A method of the disclosure includes: associating, by a processing device executing a hypervisor, hypervisor data with a first bridge device; attaching a first device associated with a virtual machine to the first bridge device; identifying a second device related to the first device; associating, by the processing device, the hypervisor data with the second device. In some embodiments, the second device is a failover device of the first device.

Abstract: A method for preserving a media access control (MAC) address of a virtual server is provided. The method includes assigning a physical computing resource to a virtual server, assigning a physical storage memory resource to the virtual server, and assigning a physical network resource to the virtual server. The method includes assigning a virtual MAC address to the virtual server, the virtual MAC address to remain with the virtual server despite reassignment of one or more of the physical computing resource, the physical storage memory resource or the physical network resource, wherein at least one method operation is performed by a processor. A computing and storage system is also provided.

Abstract: Synthesis of functional coverage (e.g., covergroups) is optimized for hardware emulation. The optimization may reduce the number of logic gates used to implement the hardware emulator circuits or reduce the computer resources used to synthesize the hardware emulator circuits. The optimization may also prevent the synthesis of unnecessary circuits. In another aspect, the optimization may result in a representation that may be used both to synthesize hardware emulation circuits and as part of formal verification. This may result in a model that can be used for formal verification, hardware emulation, and software simulation.

Abstract: Responsive to a detected user access by a user to help content of an application, at least one subsequent detected user interaction with the application is recorded that documents the user's actual use of the application in response to instructions within the accessed help content. The help content includes tracking metrics that include at least one configured expected user interaction with the application to perform the instructions within the accessed help content. The usability of the application is improved by automatically changing the application based upon results of a comparison of the recorded at least one subsequent detected user interaction with the application after the help content was accessed with the at least one configured expected user interaction with the application to perform the instructions within the accessed help content reaching a threshold for modification of the application.

Abstract: The invention relates to a computerized method and computer-based system for generating elements of recorded information for a secondary user in response to the secondary user's natural language input. The recorded information could be in the form of, for example, video, audio, audiovisual, text files, or other recordable media. The method and system of the invention permit a secondary user to access, in real time, information of an original source (e.g., allows a descendant to obtain a multimedia response stored by or on behalf of an ancestor) via a computer network, with the response being accessible via a television, audio player, Bluetooth or wireless device, or any other electronic and digital system. The access to such information can be initiated by the secondary user's input provided through use of, for example, voice response technology, including speech recognition and natural language software.

Abstract: The present disclosure relates to a 5G or pre-5G communication system to be provided for supporting a data rate higher than that of a 4G communication system such as LTE. A dynamic resource allocation method of an intelligent orchestrator in a software-defined network (SDN) according to the present invention includes acquiring operation data related to resource allocation in the SDN, adjusting at least one of virtual switch and host parameters based on the operation data and a preconfigured scheduling policy, and allocating resources dynamically according to the adjustment result.

Abstract: Capturing user presence at a workstation of a local network using an identity directory comprises detecting an unlock event, generating first and second arrays of all instances of respective first and second processes currently occurring in the local network, each instance being associated with a session ID, comparing the first and second arrays to ascertain whether any of the session IDs present in the second array are missing from the first array, performing a query in the identity directory to locate a user account associated with any session ID present in the first array and missing from the second array, and updating a record of the user accounts found in the query in regard to the user presence having been captured in association with the detected unlock event.

Abstract: A compaction circuit in an emulation system may store in a data array emulation data that may be read in subsequent emulation steps. For each emulation step, the compaction circuit may receive keeptags from a local control store word of the emulation step and store portions of emulation data identified by the keeptags. The keeptags in the control store words may be inserted by a compiler based upon whether a corresponding read port of emulation processor reads the stored data in the subsequent steps. The compaction circuit may also translate the logical read address of the stored data to a physical read address in the shared data array. A dynamic modification engine may enable dynamic modification of netlists while using the compacted data array. In response to a request, the dynamic modification engine may modify one or more keeptags and update read addresses in the control store words.

Abstract: The present application discloses a multi-media interactive story-telling system that provides natural conversational interactions between a human user and a contributor who appears in multi-media recordings. The multi-media interactive story-telling system includes an intake device for recording interview sessions in which a contributor tells a life story about her life experience. The contributor may rely on a script when creating the life story. The multi-media interactive story-telling system further comprises storage devices for storing the recorded interview sessions and processors for organizing the recorded interview sessions. The multi-media interactive story-telling system further comprises an interactive device for retrieving and playing a recorded interview session in response to a query from a user.

Abstract: A network connectivity mode is activated at a vehicle during which an on-board wireless LAN interface and an on-board wireless WAN interface are collectively operated in a higher-power consumption state with respect to a set of on-board batteries to collectively support communications between one or more LAN-side client devices and one or more WAN-side network resources. Operation of the vehicle entering a predefined operating state is detected, and in response thereto, the network connectivity mode is deactivated after a period of time during which the on-board wireless LAN interface and the on-board wireless WAN interface are collectively operated in a lower-power consumption state with respect to the set of on-board batteries and communications are discontinued between the one or more LAN-side client devices and the one or more WAN-side network resources via the on-board wireless LAN interface and the on-board wireless WAN interface.

Abstract: A computer system includes a BMC and a host of the BMC. The BMC receives a first message from a first remote device on a management network. The BMC determines whether the first message is directed to a storage service or fabric service executed on a central processing unit of the host. The host is a storage device. The central processing unit is in commutation with a RDMA controller through an external communication channel. The RDMA controller being managed by the storage service. The BMC extracts a service management command from the first message, when the first message is directed to the storage service or fabric service. The BMC sends, through a BMC communication channel to the host, a second message containing the service management command to the host. The BMC communication channel has been established for communicating baseboard management commands between the BMC and the host.

Abstract: A system and method of stopping program execution includes tagging an entry in a virtual cache with an indicator bit where the virtual address of the entry corresponds to a virtual address range in a break point register, in response to a second virtual cache data access demand matching the entry tagged with the indicator bit, determining whether the second data access demand matches the virtual address range of the breakpoint register, and in response to the second data access demand matching the virtual address range of the break point register, flagging an exception and stopping execution of the program. In an embodiment, the method or system enters a slow-mode in response to the second data access demand matching the virtual cache entry with the indicator bit, and performs a full comparison between the second data access demand and the break point register virtual address range.

Abstract: Systems and methods for providing one or more services to a device are disclosed. The device may be remote from a first network. The one or more services may be associated with the first network.

Abstract: Systems and methods are described for modifying input and output (I/O) to an object storage service by implementing one or more owner-specified functions to I/O requests. A function can implement a data manipulation, such as filtering out sensitive data before reading or writing the data. The functions can be applied prior to implementing a request method (e.g., GET or PUT) specified within the I/O request, such that the data to which the method is applied my not match the object specified within the request. For example, a user may request to obtain (e.g., GET) a data set. The data set may be passed to a function that filters sensitive data to the data set, and the GET request method may then be applied to the output of the function. In this manner, owners of objects on an object storage service are provided with greater control of objects stored or retrieved from the service.

Abstract: Changes to information are managed by storing information as a plurality of objects. Each object has one or more states. One or more temporal histories are maintained for each object based on the plurality of states of the object at a plurality of time instances. For each state of the object, whether or not the state is a user of another state of the object or another object is determined. When a request to change the information is received, at least one state of at least one of the plurality of objects is selectively changed. When it is determined that the at least one state is the user of another state, then the changing is further responsive to changes in the another state.

Abstract: Examples described herein include imaging servers which may support asynchronous imaging of one or more computers (e.g., computing nodes). The imaging server may use out-of-band communication to install requested images on one or more computing nodes. The imaging server may support multiple concurrent installation sessions, and may maintain a log specific to each session. This may facilitate session-specific status reporting. In this manner, operating systems, hypervisors, or other software may be installed on computing nodes.

Abstract: According to a computer-implemented method, an update package that includes update operational files is received at a computing device. At least one update operational file is to replace a corresponding original operational file for the computing device. It is determined which of the original operational files are to be replaced with corresponding update operational files. A delta file is stored at the computing device, which delta file indicates the original operational files that are replaced with corresponding update operational files and the update package is installed at the computing device.

Abstract: A method of capturing signals during hardware verification of a circuit design utilizes at least one field-programmable gate array (FPGA) and includes selecting, at run time and using one or more pre-compiled macros, a group of signals to be captured during verification of the circuit design and storing values of the group of signals in at least first and second random access memories disposed in the at least one FPGA. The first and second random access memories may be addressable spaces of the same random access memory.

Abstract: An electronic device is described herein. In accordance with one embodiment, the electronic device includes an embedded controller having a debug logic, an interface circuit coupled to the debug logic, and a memory coupled to the interface circuit. The interface circuit is operative to read debug information stored in the debug logic and to transmit the read debug information to the memory. The interface circuit is further operative to receive debug information stored in the memory and write the received debug information into the debug logic.

Abstract: Techniques are provided for inlining data in inodes of a file system. In an example, data (e.g., a file) is to be written to storage. Where the data is small enough to fit in an inode, it can be written to a dynamic area of the inode. Where dynamic attributes of the inode conflict with storing the data, the dynamic attributes can be spilled to a metadata block. Where the inlined data becomes too large to be stored in the inode, it can be spilled to a data block, and a metadata tree can be written to the inode. Where data that was previously too large to inline is truncated so that now it can be written to the inode, the data is inlined in the inode from a data block.

Abstract: Computer implemented methods of designing integrated circuits and computing systems are provided. A computer implemented method of designing an integrated circuit according to the inventive concepts may be performed by a processor and may include performing a placement and routing (P&R) operation for standard cells defining the integrated circuit, extracting characteristic values from a result of the P&R operation, generating a physical-aware annotation file by determining a plurality of representative characteristic values that respectively correspond to a plurality of groups based on the extracted characteristic values, and performing a physical-aware synthesis operation to generate a netlist from input data for the integrated circuit, based on the generated physical-aware annotation file.

Abstract: A system for providing automatic management of low latency computational capacity is provided. The system may be configured to maintain a plurality of virtual machine instances. The system may be further configured to identify a trend in incoming code execution requests to execute program code on a virtual compute system, determine, based on the identified trend, that the plurality of virtual machine instances should be adjusted, and adjust the plurality of virtual machine instances based on the identified trend.

Abstract: Method and systems for data switching, including receiving first input data at a network switching system comprising a crosspoint switch and a data processing card; transmitting the first input data from the crosspoint switch to the data processing card; making a first determination, by the data processing card, that the first input data meets a first pre-determined filtering criterion; and transmitting, based on the first determination, the first input data from a first crosspoint switch port of the crosspoint switch towards a first client.

Abstract: An example method comprises receiving a begin time to initiate storage network traffic data collection from a plurality of data probes integrated within an enterprise network, collecting network data identifying HBA ports used to communicate with storage ports from the probes, analyzing the network data to determine attributes of network traffic, determining for each storage unit: a penalty score for each of the storage ports determining a reconfiguration of a storage unit or HBA based at least in part on the total penalty score, simulating changes of the reconfiguration of the storage unit or the HBA and simulate storage network traffic, applying the simulated storage network traffic on the simulated changes of the reconfiguration of the storage unit or HBA to determine improvements, and outputting instructions to enable reconfiguration of the storage unit or HBA.

Abstract: A method and apparatus for simulating target program code on a host data processing apparatus, the simulation mapping load-exclusive instructions in the target program code to load instructions, and mapping store-exclusive instructions in the target program code to compare-and-swap instructions.

Abstract: Disclosed are systems and methods for emulating execution of a file based on emulation time. In one aspect, an exemplary method comprises, generating an image of a file, emulating an execution of instructions from the image for a predetermined emulation time, the emulation including: when an emulation of an execution of instruction from an image of another file is needed, generating an image of the another file, detecting known set of instructions in portions read from the image, inserting a break point into a position in the generated image corresponding to a start of the detected set of instructions, emulating execution of the another file by emulating execution of instructions from the generated image, and adding corresponding records to an emulation log, and reading a next portion from the image of the another file and repeating the emulation until the predetermined emulation time has elapsed.

Abstract: An event-driven simulation system is provided. The simulation system classifies events into bypass-events and perform-events. The simulation system performs simulation by executing instructions based on the perform-events and skips simulation for the bypass-events. The simulation system produces partial simulation result data based events that are actually simulated but not the events that are skipped. A post processor is provided to generate the missing simulation result data for the bypass-events and to merge the bypass-event with the partial simulation result to generate a complete simulation result.

Abstract: A system and method for image testing is configured to apply at least one display property to a test image to generate a display modified test image and applying the at least one display property to a reference image to generate a display modified reference image. The system also applies a human eye model to the display modified test image to generate an eye modified test image and applies the human eye model to the display modified reference image to generate an eye modified reference image. The system may compare the eye modified test image with the eye modified reference image to determine human perceivable differences between the test image and the reference image.

Abstract: Isochronous endpoints of a redirected USB device can be accelerated. When a USB device is redirected, each of the device's endpoints can be identified. A UDP socket can then be created between the client-side proxy and the server-side agent for each isochronous endpoint, while a TCP socket can be created for each other endpoint. A lookup table can also be created which maps pipe handles to socket IDs. The lookup table can be employed to route USB request blocks pertaining to a particular endpoint over the corresponding socket. In this way, USB request blocks pertaining to an isochronous endpoint will be transferred over the network using UDP while USB request blocks pertaining to non-isochronous endpoints will be transferred using TCP.

Abstract: Performing breakpoint detection via a cache includes detecting an occurrence of a memory access and identifying whether any cache line of the cache matches an address associated with the memory access. When a cache line does match the address associated with the memory access no breakpoint was encountered. When no cache line matches the address associated with the memory access embodiments identify whether any cache line matches the address associated with the memory access when one or more flag bits are ignored. When a cache line does match the address associated with the memory access when the one or more flag bits are ignored, embodiment perform a check for whether a breakpoint was encountered. Otherwise, embodiments process a cache miss.

Abstract: A system and method is provided for performing computations on a virtual machine without a special hardware computation unit, such as a discrete graphics processing unit (GPU). The described method uses a computation module to intercept requests from a user application executing in a virtual machine on a first physical computer. The intercepted requests may include requests to configure GPU computation grids, start and finish accelerated code execution, and transfer data to and from the special computation unit. The computation module offloads accelerated code to a second physical computer having a physical special hardware unit (e.g., discrete GPU).

Abstract: Apparatus, systems, or methods for a programmable circuit to facilitate a processor to boot a computing device having the processor. A programmable circuit may include non-volatile storage and firmware stored in the non-volatile storage. The firmware may configure the programmable circuit as a memory controller of a memory device coupled to the programmable circuit, to facilitate the processor to boot the computing device having the processor, the programmable circuit, and the memory device, into operation. Other embodiments may also be described and claimed.

Abstract: The present invention facilitates efficient and effective device testing and debugging. In one embodiment, a tester system includes a controller processor; a plurality of programmable accelerator circuits coupled to and controlled by the controller processor; and a plurality of load boards respectively coupled to the plurality of programmable accelerator circuits. The plurality of load boards can apply the input test signals to a plurality of devices under test (DUTs) and capture the output test signals therefrom. The plurality of programmable accelerator circuits can provide input test signals and capture output test signals. In one exemplary implementation, each of the plurality of load boards comprises: a first set of connections for transmitting input test signals to a respective DUT; a second set of connections for receiving output test signals from the respective DUT; and sideband connectors. The sideband connectors receive test related information from the DUT.

Abstract: A method for execution by a dispersed storage and task (DST) processing unit includes receiving a write request that includes a data object. Characterization data is generated by determining a data type of the data object. Object constraint data is generated by determining a compressibility of the data type and a processing cost of the data type. Optimized trade-off data is generated by optimizing a plurality of trade-off constraints based on the object constraint data. A compression algorithm is selected from a plurality of compression algorithm options based on the optimized trade-off data. A compressed data object is generated by performing the selected compression algorithm on the data object. A plurality of data slices are generated for transmission to a plurality of storage units for storage by performing an information dispersal algorithm on the compressed data object.

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

Abstract: A stream application may use small chunks of executable code configured to process data tuples flowing into a processing element. A scheduler allocates the processing elements to individual compute nodes or hosts for execution. However, the stream application may assign various constraints that stipulate which hosts are suitable for a particular processing element. To assign hosts to processing elements such that the constraints are satisfied, the scheduler may use hostpools associated with the processing elements. Once a host is identified that satisfies the constraints, it may be pinned at a particular index within the hostpool.

Abstract: Methods, systems, computer-readable media, and apparatuses for providing search disambiguation using contextual information and domain ontologies are presented. In some embodiments, a computing device may receive a natural language input from a user. The computing device may identify a plurality of hypotheses for the natural language input. The computing device may map the plurality of hypotheses to one or more concepts of a plurality of concepts of an ontology by annotating the one or more concepts. The ontology may include the plurality of concepts respectively connected by a plurality of relations. The computing device may determine that there is an imperfect match between the annotated one or more concepts and annotations of answers. In response, the computing device may disambiguate the annotated one or more concepts using the ontology. The computing device may present output to the user based on the disambiguation.

Abstract: A computer-aided method for configuring a hardware verification system is presented. The method includes receiving, by the computer, a first data representative of a first design of an integrated circuit, when the computer is invoked to configure the verification system, and transforming, using the computer, the first data into a second data representative of a second design. The second design includes a functionality of the first design, and a first circuit adapted to compute a third data representative of a power consumption of a first portion of the first design when the hardware verification system is configured with the second data and run. The first circuit is programmable without reconfiguring the second design.

Abstract: A method of emulating an instruction includes identifying a fault instruction. The fault instruction is saved in a register. The fault instruction is associated with a software emulated operation. The software emulated operation is initiated with an access to the fault instruction in the register.

Abstract: A digital crosspoint switch of a network switching system (NSS) replicates input data received via a first network interface to a first data processing port of a data processing card. The input data includes a digital market data feed comprising market-data packets. The crosspoint switch has internal crosspoint ports and external crosspoint ports. The data processing card includes a programmable logic device and a plurality of data processing ports connected to the internal crosspoint ports. The NSS includes a plurality of network interfaces connected to the external crosspoint ports. The data processing card processes the input data and generates processed data on the second data processing port at least in part by only including market-data packets that meet a first predetermined filtering criterion in the processed data. The crosspoint switch replicates the processed data from the second data processing port to the second network interface.

Abstract: Performance analysis for test automation frameworks is described. A test is executed of an application. Performance indicators are logged during execution of the test, wherein the performance indicators include a first performance indicator. A correlation is identified between the first performance indicator and a second performance indicator recorded during the execution of the test or an execution of a previous test of the application. An output device outputs the correlation as a performance issue.

Abstract: A computer-implemented method generates a plurality of clusters based on components included in a design under test (DUT); classifies a subset of clusters of the plurality of clusters as tangled clusters; modifies at least two tangled clusters of the subset of clusters based on overlap between the at least two tangled clusters; determines, for each tangled cluster in the subset of clusters, a gate count based on the interconnectivity of the tangled cluster; and partitions the DUT among a plurality of field-programmable gate arrays (FPGAs) based on the gate count determined for each tangled cluster from the subset of clusters.

Abstract: Methods, systems, and computer programs for integration of user interface technologies. One of the methods includes receiving, from a user device, a user request to execute a web application, the web application being associated with one or more rendering systems, and each of the rendering systems executing one or more respective remote applications. Respective video streams for the remote applications are obtained from each of the rendering systems. Each of the video streams is provided for presentation on the user device. While the video streams are provided, data identifying a user event is received from the user device. The user event is determined to be intended for a first rendering system. The user event is provided to the first rendering system.

Abstract: A method is provided for controlling processing of target program code on a host data processing apparatus to simulate processing of the target program code on a target data processing apparatus. In response to a target memory access instruction of the target program code specifying a target address within a simulated address space having a larger size than a host address space supported by a memory management unit of the host data processing apparatus, an address space resizing table is looked up to map the target address to a transformed address within said host address space, and information is generated for triggering a memory access based on translation of the transformed address by the memory management unit of the host data processing apparatus.

Abstract: A memory manager of a processor identifies a block of data for eviction from a first memory module to a second memory module. In response, the processor copies only those portions of the data block that have been identified as modified portions to the second memory module. The amount of data to be copied is thereby reduced, improving memory management efficiency and reducing processor power consumption.

Abstract: Behavioral analysis of a mobile application is performed to determine whether the application is malicious. During analysis, various user interactions are simulated in an emulated environment to activate many possible resulting behaviors of an application. The behaviors are classified as hard or soft signals. A probability of the application being malicious is determined through combining soft signals, and the application is classified as malicious or non-malicious. Users of the application, the developer of the application, or a distributor of the application are notified of the application classification to enable responsive action.

Abstract: Disclosed herein are systems and methods of an emulation system. A hardware emulator of an emulation system includes one or more processors configured to generate data in an emulation cycle. Each bit of the generated data is associated with a tag. The hardware emulator may include a compaction unit configured to receive the data generated by the one or more processors, and select one or more bits from total bits of the data based on valid tags associated with the bits of the data. The hardware emulator further includes a data array comprising non-transitory machine-readable storage media configured to store the one or more bits of the data received from the compaction unit.

Abstract: A system and method is provided for performing computations on a virtual machine without a special hardware computation unit, such as a discrete graphics processing unit (GPU). The described method uses a computation module to intercept requests from a user application executing in a virtual machine on a first physical computer. The intercepted requests may include requests to configure GPU computation grids, start and finish accelerated code execution, and transfer data to and from the special computation unit. The computation module offloads accelerated code to a second physical computer having a physical special hardware unit (e.g., discrete GPU).