Abstract: An integrated circuit for a smart card may include a transceiver and a controller for cooperating with the transceiver to receive operating requests from a host device. The controller may perform smart card operations based upon respective operating requests. Moreover, the controller also may cooperate with the transceiver to receive at least one advance request from the host device to indicate that at least one operating request will follow. By way of example, the standby operation may include loading data in at least one buffer, which may be sent to the host device based upon receiving the at least one operating request. Other standby operations may include disabling data transmission to the host device, such as when the communications bus of the host device is preoccupied, and ceasing performing a current smart card operation to allow a higher priority smart card operation to be performed, for example.

Abstract: A method of arbitration within a data processing apparatus between a plurality of transfers to be routed over a corresponding plurality of paths provided by an interconnect circuit. The plurality of paths include a shared connection, the data processing apparatus having a plurality of initiator logic elements for initiating transfers and a plurality of recipient logic elements for receiving transfers, for each transfer the corresponding path coupling the initiator logic element responsible for initiating that transfer with the recipient logic element destined to receive that transfer. The method comprises the steps of providing to arbitration logic an indication as to whether the ready signal from a storage element has been asserted, and employing the arbitration logic to select, in dependence on predetermined criteria including at least that indication, one of the plurality of transfers for routing via the shared connection.

Abstract: A method, apparatus, system, and signal-bearing medium that in an embodiment set a resource indicator to indicate that a processor is using a resource in a logically-partitioned electronic device, determine whether a current partition in the logically-partitioned electronic device owns the resource, and clear the resource indicator after the processor is done using the resource. When a partition gives up ownership of a resource, a resource ownership state is changed to indicate that the partition does not own a resource, and the partition waits to continue executing until other processors have cleared their respective resource indicators. In an embodiment, the resource indicator is in a cache line that is local to the processor, which allows resources to be dynamically allocated with improved performance.

Abstract: A request is received from a first requester to write a second indicator that includes an identifier of the first requester to a first indicator that indicates if a component is available. In response it is determined whether the component is available. If the component is available, the first indicator is replaced with the second indicator reducing access to the component and permitting access to the component by the first requester.

Abstract: A processor chip is provided. The processor chip includes a plurality of processing cores, where each of the processing cores are multi-threaded. The plurality of processing cores are located in a center region of the processor chip. A plurality of cache bank memories are included. A crossbar enabling communication between the plurality of processing cores and the plurality of cache bank memories is provided. The crossbar includes an arbiter configured to arbitrate multiple requests received from the plurality of processing cores with available outputs. The arbiter includes a barrel shifter configured to rotate the multiple requests for dynamic prioritization, and priority encoders associated with each of the available outputs. Each of the priority encoders have logic gates configured to disable priority encoder outputs. A method for arbitrating requests within a multi-core multi-thread processor is included.

Abstract: There is provided a media access controller with a power-save mode. Particularly, the media access controller of the present invention minimizes power loss by disabling clocks applied to all blocks, including CPU, of the media access controller during the power-save mode. The media access controller of the present invention includes: a power-save master for securing stable transmission/reception of data through bus by respective processors contained in the controller; a wake-up timer for noticing that the power-save mode is expired; a power control unit for determining whether to supply a power to a phase-locked loop, and a timing when clocks for the media access controller are applied and disabled; and a locktime register for storing a locktime when an output of the phase-locked loop is settled. Additionally, there is provided a method of efficiently changing the media access controller from the active mode to the power-save mode, and vice versa.

Abstract: The present invention provides a method of arbitration for resources which allows requestors from multiple frequency domains. Most requestors generate requests at full speed. A small number of low-speed requesters generate requests every two full-speed cycles, and hold their requests for two full-speed cycles. The arbitration method gives priority to the requests from the low-priority requesters and guarantees that two requests made by the half-speed requestors at the beginning of a low-speed cycle will be granted over the course of the low-speed cycle. The requests generated by the low-speed requestors are issued in phases. Issuance of later phases of a request is blocked when the request has been granted in an earlier phase.

Abstract: A statistic method for arbitration is provided, implementing in an arbitration system comprising a bus, a main controller connected to the bus, and a plurality of peripheral devices able to be accessed by the main controller through the bus. The statistic method for arbitration is in response to various conditions where a bus is shared by peripheral devices, characterized in that a host at arbitration dynamically modulates the peripheral devices' access through the bus by utilizing an attenuation function to perform operation on a preceding cycle and a statistic value representing the use of the bus by the peripheral devices in response to the peripheral devices' access through the bus.

Abstract: In a multiprocessor, access to shared resources is provided by a semaphore control mechanism, herein disclosed. The semaphore control mechanism provides for a high degree of programmable firmware reuse requiring relatively few modifications from a uniprocessor. A machine check abort (MCA) handling mechanism is disclosed, which works with the semaphore control mechanism in the multiprocessor to provide improved system availability and reliability. The MCA handling mechanism provides for synchronization of multiple processors and shared resources and for timely execution resumption within the processors that remain on-line.

Abstract: Various techniques are described for improving the performance of a multiple node system by allocating, in two or more nodes of the system, partitions of a shared cache. A mapping is established between the data items managed by the system, and the various partitions of the shared cache. When a node requires a data item, the node first determines which partition of the shared cache corresponds to the required data item. If the data item does not currently reside in the corresponding partition, the data item is loaded into the corresponding partition even if the partition does not reside on the same node that requires the data item. The node then reads the data item from the corresponding partition of the shared cache.

Abstract: A two-stage arbiter system comprises a first-stage arbiter to grant a request to one of a plurality of requestors in accordance with a first arbitration scheme and a second-stage arbiter to grant one of the remaining requests in accordance with a second arbitration scheme. The first arbitration scheme may be a fast arbitration scheme such as a fixed-priority scheme, and the second arbitration scheme may be a rotating priority-based arbitration scheme or a least-recently-granted arbitration scheme. The first-stage arbiter may operate in a first pipelined stage, and the second-stage arbiter may operate in a second pipelined stage. Two-stage arbitration may help improve access of lower-priority requestors in a pipelined system. In one embodiment, a rotating-priority arbitrator includes a pseudo-random number generator to generate an amount for rotating priorities prior to arbitration. The rotating-priority arbiter may use either a counter or linear-feedback shift register to rotate priorities of requests.

Abstract: In a system having a plurality of bus masters, system and method for enhancing data bus utilization are disclosed. This system comprises: a data bus connected to a peripheral apparatus and composed of a plurality of unit data buses each capable of carrying out data transfer independently; a plurality of bus masters each for sending a request signal requesting a use of the data bus in unit data buses, and using the data bus in unit data buses requested when a request by means of the request signal is granted; and a bus controller for giving a grant signal which grants the use of the data bus in unit data buses requested in unit data buses to the bus masters in accordance with an availability of the data bus in unit data buses, thereby split-controlling the data bus in unit data buses for the plurality of bus masters.

Abstract: Data shared by plural processes of a program are identified and identification information is affixed to the shared data. When the program is linked by a linker, only the shared data to which identification information is affixed are extracted and a shared data area is created for the shared data. During program execution, this shared data area is prevented from being and the main memory is referred to or updated or the cache is invalidated prior to access of the shared data area by the linker. An address of data in a processor is computed from an address of the data in another processor based on a specific expression.

Abstract: A method, apparatus, and computer program product includes identifying a plurality of memory transactions to be sent over a memory bus to a memory having a plurality of memory banks, each memory transaction addressed to one of the memory banks, the memory bus incapable of transmitting the plurality of memory transactions simultaneously; identifying a plurality of bank readiness signals, each bank readiness signal indicating the readiness of one of the memory banks to accept a memory transaction; and selecting one of the memory transactions for transmission over the memory bus based on the bank readiness signals.

Abstract: A delay interval is calculated for a processor that attempts to reserve a reserved shared resource in a multiprocessing system. The delay interval is based on the relationship of a requesting processor and a reservation holding processor. Each delay interval is unique without consistent bias against a processor. The requesting processor queries the reservation status of a shared resource without invalidating an existing reservation. If a shared resource is reserved, the requesting processor waits for an amount of time corresponding to the delay interval before again attempting to reserve the shared resource. The present invention substantially reduces arbitration conflicts within multiprocessor systems.

Abstract: An improved method and apparatus for resource arbitration. Four priority classes, managed high (MH), managed low (ML), opportunistic high (OH) and opportunistic low (OL), are defined. A priority class is assigned to each resource access request. An access request concentrator (ARC) is created for each resource, through which the resource is accessed. An access request is chosen at each ARC using the priority order MH, ML, OH, and OL, in decreasing order of priority. If OH priority class resource access requests are locked out, the priority order is temporarily changed to OH, OL, MH, and ML, in decreasing order of priority. If OL priority class resource access requests are locked out, the priority order is temporarily changed to MH, OL, OH, and ML, in decreasing order of priority.

Abstract: A resource access control mechanism for a multi-threaded computing environment associates a sequence of one or more mutexes with a resource. When a requesting thread attempts to access the resource, a mutex is locked and allocated to the requesting thread, and if a previous mutex in the sequence is present, an attempt to lock the previous mutex is made. If the previous mutex is already locked, the requesting thread is suspended until the previous mutex is unlocked.

Abstract: A reconfigurable radio processor comprises a task interface and an execution kernel. The processor can be applied to a platform comprising a main processor and on-chip bus, and uses a task-based interface between the main processor and the radio processor. The radio processor simplifies the designs for control system, instruction set and data path. The bus interface includes a task dispatcher. The execution kernel comprises a global control unit, at least one function unit, an operation network, and a data network. The radio processor meets the reconfigurable and scalable requirements. It allows system designers to realize many applications on an IC chip, as well as increases the add-on values for the product. It provides system designers with the possibility of replacing another main processor under a special consideration.

Abstract: Disclosed is a method for and an apparatus using various factors including system performance feedback data to optimize the time suggested to attempt retry of a request. Among the factors used there is included present system performance, type of request, status of pending action, current number of retries pending, a predefined fixed interval, a pseudo random interval, a random interval, past history of retry requests, heuristically determined interval, and an interval based upon hang detection.

Abstract: Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a plurality of logic elements, programmably configurable to implement user-defined combinatorial or registered logic functions, and an embedded processor portion coupled to the programmable logic portion. The embedded processor portion includes a processor, and a memory block coupled to the processor. The memory block includes a first plurality of memory cells for storing data, a second plurality of memory cells for storing data, a first port coupled to the first and second pluralities of memory cells, a second port coupled to the first and second pluralities of memory cells, and an arbiter coupled to the first port and the second port.

Abstract: A multiprocessor array with a first shadow register unit (3) which operates within a first clock domain, at least one second shadow register unit (11) which operates within a second clock domain, and a peripheral unit (17) which operates within a peripheral clock domain. Within all clock domains there are provided register units (3, 11, 20) which have a construction that is functionally identical.

Abstract: A single memory bus multi-media computer system is provided, including a CPU/Sound/Graphic unit, a bus arbitrator, a program and sound and graphic memory for communicating with the CPU/Sound/Graphic unit and the bus arbitrator. Only a single memory bus is required as communication is through the bus arbitrator. The addition of the bus-arbitrator can relieve the CPU/Sound/Graphic unit from performing bus synchronization and waiting for the slow memory to catch up.

Abstract: An agent may be coupled to receive a clock signal associated with the bus, and may be configured to drive a signal responsive to a first edge (rising or falling) of the clock signal and to sample signals responsive to the second edge. The sampled signals may be evaluated to allow for the driving of a signal on the next occurring first edge of the clock signal. By using the first edge to drive signals and the second edge to sample signals, the amount of time dedicated for signal propagation may be one half clock cycle. Bandwidth and/or latency may be positively influenced. In some embodiments, protocols which may require multiple clock cycles on other buses may be completed in fewer clock cycles. For example, certain protocols which may require two clock cycles may be completed in one clock cycle. In one specific implementation, for example, arbitration may be completed in one clock cycle. Request signals may be driven responsive to the first edge of the clock signal and sampled responsive to the second edge.

Abstract: A storage element pending command queue prioritization system using multiple pending queues each assigned to a particular RAID command type. Pending commands from each of the queues are organized in such a way that lower priority commands are guaranteed a fixed amount of storage element bandwidth. Storage element throughput is optimized by limiting higher priority commands to a maximum service level and processing lower priority requests with the added storage element bandwidth, allowing lower priority requests to exceed their minimum service levels.

Abstract: An improved system is described for allowing an embedded controller and a host processor to share access to modules in a computer system. The shared access system of the present invention enables exclusive, one-at-a-time access by a processor to a module and concurrent access by more than one processor to a module. An internal bus with two power sources is used to allow continued access by one of the processors when one of the two power sources is not providing power. Asynchronous clocking is provided to allow increased throughput to modules. An example of a protocol that allows an embedded controller to access more than one module is also described.

Abstract: A method for filtering requests in portable devices is described. Nonvolatile flash memory is used to store allowable client addresses. The discovery, service discovery, and connection filter algorithms reduces power and processing bandwidth required from portable, mobile devices.

Abstract: Systems and methods are disclosed for arbitrating requests from a plurality of clients requesting access to a shared real-time resource. In one embodiment, a plurality of sub-clients are aggregated into an aggregate client. At the aggregate client, access requests from the sub-clients are arbitrated to generate an aggregate request. An aggregate deadline is determined and access requests from the aggregate client and other clients are arbitrated using the aggregate deadline as the deadline of the aggregate client. In one embodiment, a critical instant analysis of the system is performed using the aggregate deadline as the deadline of the aggregate client. In another embodiment, a block-out counter is employed at an aggregate client to regulate the rate at which the aggregate client provides access requests to the shared resource.

Abstract: A method of synchronizing or initiating channel lock in a serial loop formed by an initializing transceiver and subject transceivers disclosed. Should a transceiver in the serial loop detect that its receiving serial channel is desynchronized, it sends an unlock signal to the next transceiver in the loop. The unlock signal guarantees that the next transceiver's receiving serial channel will be desynchronized. Only the initializing transceiver may initiate a channel lock sequence.

Abstract: Plural arbiters arbitrate over a set of queues. The arbiters are constructed as a series of pipelined stages. Conflict detection logic detects conflicts among the arbiters in arbitrating across the queues, and, when a conflict is detected, the conflict detection logic alters processing related to conflicting queues in one arbiter when another arbiter has not passed a predetermined commit point in processing the queue.

Abstract: A computer system including a storage device, a first and second device driver, and a nexus driver. The storage device has multiple bit positions, and is coupled to a set of electrical terminals. A first portion of the electrical terminals is adapted for coupling to a first device, and a second portion of the electrical terminals is adapted for coupling to a second device. Each device driver controls a respective device by generating an access to the storage device, and writing a value to a respective portion of the bit positions. The nexus device driver is coupled between the first and second device drivers and the storage device, and arbitrates between the first and second device drivers for access to the storage device.

Abstract: Various embodiments of message gate pairs are described. A message gate pair may provide a mechanism for communicating requests from clients to services and response from services to clients. A message gate pair may be used to create a secure atomic bi-directional message channel for request-response message passing. The distributed computing environment may employ a message transport in which a message gate exists on both the client and the service. The two gates may work together to provide a secure and reliable message channel. Client and service gates may perform the actual sending and receiving of the messages from the client to the service using a protocol specified in a service advertisement. The message gates may provide a level of abstraction between a client and a service. A client may reference a service through a message gate instead of referencing the service directly.

Abstract: One embodiment of the present invention provides a circuit that preferentially grants requests. This circuit monitors at least two inputs for request signals and at least two inputs for enable signals, wherein each request signal is associated with a corresponding enable signal. If any enable signal is asserted and only one request signal is asserted, the circuit asserts a grant signal associated with the asserted request signal. Otherwise, if a single enable signal is asserted and multiple request signals are asserted, the circuit preferentially asserts the grant signal of the request signal associated with the asserted enable signal.

Abstract: Access to a bus is granted to one of a number of requesting communication circuits that each submitted a bus control request during a request period of an arbitration period in response to the entries in a priority table. If a requesting communication circuit has an identity and priority that match the identity and priority of a communication circuit stored in a row of the priority table that corresponds with the arbitration period, access to the bus is granted to the requesting communication circuit.

Abstract: Various methods and apparatuses to deactivating the mechanism to resolve instruction starvation if an agent which issued a first transaction does not reissue the first transaction within a predefined time period.

Abstract: Systems and methods for bus arbitration in an integrated circuit system, which prevent discrepancies of bus occupation rates (or the number of bus occupancies) and which provide programmable bus occupation rates for bus masters. In one aspect, a bus arbiter for an integrated circuit system including a plurality of bus masters, comprises a program file comprising a plurality of program registers, wherein each program register is associated with one of the bus masters and stores a predetermined value of a bus occupation rate assigned to the bus master, a temporary file comprising a plurality of temporary registers, wherein each temporary register is associated with one of the bus masters and stores a current value of the bus occupation rate of the bus master, and a point register that designates the bus master having the highest priority among the bus masters at a given time.

Abstract: Embodiments of the present invention provide a memory arbiter for directing chipset and graphics traffic to system memory. Page consistency and priorities are used to optimize memory bandwidth utilization and guarantee latency to isochronous display requests. The arbiter also contains a mechanism to prevent CPU requests from starving lower priority requests. The memory arbiter thus provides a simple, easy to validate architecture that prevents the CPU from unfairly starving low priority agent and takes advantage of grace periods and memory page detection to optimize arbitration switches, thus increasing memory bandwidth utilization.

Abstract: A bus system and a method of deciding a data transmission path are provided. The bus system includes a plurality of functional blocks; a ring bus which transmits data in a single direction; an arbiter which generates a bus grant signal according to a predetermined algorithm in response to a bus request from one of the functional blocks; and a plurality of bus connectors each of which connects a corresponding functional block to the ring bus, transmits data from the corresponding functional block to the ring bus, and transmits data from the ring bus to the corresponding functional block. The method includes synthesizing and laying out a bus system, simulating a case where a short-cut bus is used when data is transmitted between functional blocks and a case where the short-cut bus is not used, and generating a bus selection table, to be referred to for selection of a bus, based on the simulation results.

Abstract: An apparatus, program product and method to manage access to a shared resource by a plurality of processes in a multithreaded computer via a collection of atomic operations that track both the order in which requests that use a shared resource are received, and the order in which processing of such requests are completed after they are received. Dispatching of requests is effectively deferred until processing of all non-dispatched requests that were received earlier than a most recently completed request has been completed. In many instances, completion of processing of requests can be performed non-atomically, thus reducing contention issues with respect to the shared resource. Furthermore, dispatching of requests may be batched to reduce the overhead associated with individual dispatch operations.

Abstract: A method and system for controlling access to selected resources in a computer system. The system includes a processor and a device coupled to the processor. The device includes one or more sub-devices and one or more access locks. The access locks are configured to prevent access to the sub-devices when the access locks are engaged. The device may include a bridge. The sub-devices may include a duration timer, mailbox RAM, locks for a storage device, overrides for the locks for the storage device, a TCO counter, a monotonic counter, scratchpad RAM, and/or a random number generator. The method includes unlocking security hardware and accessing a first device. The method also includes locking the security hardware and calling an SMM exit routine.

Abstract: The time taken for connection establishment is monitored to aid in selecting load distribution among nodes in a data delivery system, such as a server cluster. The failure of a node to respond to a connection request may be used to identify a crashed node. The number of connections being maintained and the amount of bandwidth being consumed may also be monitored for each node, and this information may be used to determine when a node should be removed from contention for new connection requests and when a node should be reinstated to receive new connection requests.

Abstract: A method and apparatus is described for controlling accesses to a shared resource. An arbitration mechanism uses a register, accessible by each device sharing the resource. The register may be written by the device to request access to the resource, and read by the device to determine whether access to the resource has been granted. Advantageously, the register includes an override bit, which may be used by either device to override the peer device's request for the shared resource. In addition, the register includes a reset bit that may be used to reset arbitration logic controlling the access to the shared logic. The register is used by a straightforward arbitration mechanism that includes only IDLE and GRANT states for each device coupled to the shared resource. Such an arrangement provides a low cost method of controlling accesses to a shared resource.

Abstract: Disclosed are systems and methods for providing access to bus-mastered system resources comprising disposing a bus multiplexer between a first bus and a bus access arbiter, wherein the first bus is coupled to at least one system resource for which bus access is arbitrated by the bus access arbiter, and controlling the bus multiplexer to couple a second bus to the first bus thereby providing a link between the first bus and the second bus bypassing the bus access arbiter.

Abstract: The present invention is generally directed to a device including an asynchronous input/output (I/O) data cache. The device includes a single data storage area that is disposed in communication with both a system data bus and a I/O data bus. Similarly, the device includes an address storage area that is configured to store system addresses corresponding to data contemporaneously stored in the data storage area. The device further includes a first circuit configured to indicate validity status of data within the data storage area for immediate access from the I/O data bus. A similar, second circuit is also included and configured to indicate validity status of data within the data storage area for immediate access from the system data bus.

Abstract: A method (and structure) in a computer network of controlling the admittance of requests to at least one processing component, includes differentiating the type of received requests based on the message content in each request. Each request is admitted only if the differentiated type meets at least one criterion for admission.

Abstract: In digital signal processors serial data is passed in out and of the chip in a time division multiplexed (TDM) fashion. The TDM stream consists of many independent channels of serial data. The complexity of generating interleaved TDM serial data from multiple sources particularly in the case of multi-processor systems. This process is normally driven by a program resident on each processor. The proper sequencing of the TDM serial stream must be tested prior to making the multi-processor device ready for its application. This invention describes the use of minimal added hardware and a single output pin allowing the test and debug of program errors or device malfunctions in output serial data.

Abstract: A system may include at least a first agent and a second agent, and the first agent may be coupled to receive a block signal generated by the second agent. The block signal is indicative of whether or not the second agent is capable of participating in transactions. The first agent initiates or inhibits initiation of a transaction for which the second agent is a participant responsive to the block signal. The system may include additional agents, each configured to generate independent block signals. Other implementations may share block signals among two or more agents. For example, a memory block signal indicative of memory transactions being blocked or not blocked and an input/output (I/O) block signal indicative of I/O transactions being blocked or not blocked may be employed. In yet another implementation, a first agent may provide separate block signals to other agents.

Abstract: An apparatus and method for reducing LDRQ input pin count of a low pin count (LPC) host are provided. The LPC host is series of connecting with a plurality of peripheral devices, the peripheral device having a LDRQ control device within. The LDRQ control device comprises a LDRQ to DRQ decoder, a DRQ arbiter, and a DRQ to LDRQ encoder. In the LDRQ control device, a LDRQ signal is decoded into a DRQ signal via the LDRQ to DRQ decoder and then the DRQ signal is priority arbitrated via the DRQ arbiter. Next, the arbitrated DRQ signal is transferred into a LDRQ signal via DRQ to LDRQ encoder. Following, the LDRQ signal is outputted into the next stage peripheral device or to output into a LDRQ input pin of the LPC host, so as the LPC host only need one LDRQ input pin for purposing to effectively reduce the LDRQ input pin count and lower the manufacturing cost of the LPC host.

Abstract: Provided are a parameter generating circuit and a method of generating a parameter which decides priority of master blocks. An arbitration parameter generating circuit includes a counter, a short term arbitration parameter storage unit, a short term reference time measurement unit, a long term arbitration parameter control unit and a long term reference time measurement unit. The counter receives a request signal generated in order for a master block to occupy a system bus and a grant signal generated in order for an arbitrator to allow the master block to occupy the system bus, up-counts when the request signal is at a first logic level, down-counts when the grant signal is at the first logic level, and is reset in response to a predetermined short term reference time signal. The short term arbitration parameter storage unit receives and stores the counted signal as the short term arbitration parameter until the counter is reset in response to the short term reference time signal.

Abstract: Distributed arbitration in a full-duplex bus system. By distributing the arbitration function among the nodes of a tree topology full-duplex bus system such that arbitration at any particular time is handled by a node holding a grant of the bus at that time (the nominal root node), a reverse flow direction towards the nominal root node is available for arbitration flow. This allows the discrete arbitration phase to be eliminated and generally improves bus efficiency.

Abstract: A bus structure is implemented within a control chipset between a first control chip and a second control chip, comprising a first AD bus and a second AD bus. According to an arbitration method implemented to allow a dynamic adjustment of the direction of the AD buses transmission, the first control chip has a higher access priority in respect of the first AD bus, while the second control chip has a higher access priority in respect of the second AD bus. When the load of the first AD bus driving by the first control chip is high, a request signal is transmitted from the first control chip to the second control chip, so that if the second control chip is not currently using the second AD bus, the ownership of the second AD bus is handed over to the first control chip to improve the transmission efficiency, and vice versa.