Abstract: A method for implementing a spin lock in a system including a plurality of processing nodes, each node including at least one processor and a cache memory, the method including steps of: acquiring exclusivity to the cache memory; checking the availability of the spin lock; setting the spin lock to logical one if the spin lock is available; setting the spin lock to logical zero once processing is complete; and explicitly yielding the cache memory exclusivity. Yielding the cache memory exclusivity includes instructing the cache coherent hardware to mark the cache memory as non-exclusive. The cache memory is typically called level two cache.

Abstract: An integrated circuit device in which a CPU not to be used of a plurality of CPUs formed on one chip can easily be disconnected by an external signal in order to reduce the costs of developing an LSI. In accordance with a CPU selection signal inputted from the outside, a decoder generates an internal selection signal for selecting a CPU to be operated and sends the internal selection signal to the plurality of CPUs. Only the selected CPU can perform valid access to a bus to use peripheral modules.

Abstract: In a more efficient distributed control or monitoring arrangement there are devices in control, monitoring and/or vehicle systems that comprise locally deployed module units that carry out one or more functions, and one or more links connecting the units. The respective module unit is connected to a link via a connection arrangement or a connection point and requisite communication device for the CAN protocol. A CAN control unit is arranged to receive indication of falling edges on the bus in question, and to carry out measurement of the time between falling edges using clock pulses in its clock function. Information from two or more such measurements forms the basis for calculation of a bit frequency currently used in communication on the bus by active module units connected to the same.

Abstract: A processor context stored in a stack area at a time of an interrupt occurrence is saved in a context saving area of an ICB corresponding to an ISR that is interrupted. The ISR corresponding to the interrupt is set to an execution-waiting state. An ICB having a highest priority from among the ICBs that are set to the execution-waiting state is selected. A processor context saved in a context saving area of the selected ICB is stored in the stack area. An ISR corresponding to an ICB selected by an interrupt return command is executed.

Abstract: Methods and apparatus for peer-to-peer data transfers in a computing environment provide configurable control over the number of outstanding read requests by one peer device to another. A requesting peer device includes a control register that stores a high-watermark value associated with requests to a target peer device. Each time a read request to the target peer device is generated, the number of such requests already outstanding is compared to the high-water mark. The request is blocked if the number of outstanding requests exceeds the high-water mark and remains blocked until such time as the number of outstanding requests no longer exceeds the high-water mark. Different high-water marks can be associated with different combinations of requesting and target devices.

Abstract: A computer-implemented method of generating timeout errors based on shared register access by two processors is described. A processor access timer is started responsive to generation of an access request by a first processor. The generated first processor access request is transmitted to a shared storage component including a shared register and able to communicate with both the first and second processors. A timeout error is generated responsive to the processor access timer exceeding a processor predetermined timeout threshold value.

Abstract: In a multiprocessor, access to shared resources is provided by a semaphore control mechanism, herein disclosed. The semaphore control mechanism provides for a high degree of programmable firmware reuse requiring relatively few modifications from a uniprocessor. The semaphore control mechanism receives one or more semaphore modification requests from one or more requesting devices, identifies an ownership state of a semaphore corresponding to the one or more semaphore modification requests, arbitrates to identify modification request from a particular requesting device to succeed if the identified ownership state corresponds to the particular requesting device or if the identified ownership state corresponds to no ownership.

Abstract: A resource and partition manager of the preferred embodiments includes a lock mechanism that operates on a plurality of locks that control access to individual PCI adaptor slots. The resource and partition manager uses the lock mechanism to obtain a lock on an PCI adaptor slot when transferring control of the PCI adaptor slot to a logical partition that is powering on and when removing the PCI adaptor from a logical partition that is powering off. The resource and partition manager uses the lock mechanism to remove control of an PCI adaptor slot from, or return control to, an operating logical partition in order to facilitate hardware service operations on that PCI adaptor slot or on the physical enclosure in which it is contained.

Abstract: A bus system, which may prevent data from being incorrectly transferred when an early termination occurs during a burst mode, may include a bus, for example, an advanced high-performance bus (AHB), at least one bus master device, a bus arbiter and at least one transfer mode selection circuit. The at least one bus master device may generate a burst cycle control signal, a transfer start signal and a bus control request signal for requesting control of the bus, and may be activated in response to a bus control grant signal, so as to exchange data via the bus. The bus arbiter may generate the bus control grant signal in response to the bus control request signal and provide the bus control grant signal to the bus master device. The at least one transfer mode selection circuit may convert a burst mode into a single mode to generate a selection signal, when the bus control grant signal is deactivated before a burst mode operation is completed.

Abstract: A system provides dual use of a general purpose input/output (I/O) line. In an embodiment, the system comprises a controlling circuit having a dual purpose I/O line that is selectively operable in a serial transmit mode or an I/O mode. A first circuit that receives a serial data stream when the controlling circuit operates in the serial transmit mode is coupled to the I/O line. A second circuit that generates and transmits a signal when the controlling circuit operates in the I/O mode is also coupled to the I/O line. Finally, a third circuit is disposed between the second circuit and the I/O line. In an embodiment, when the controlling circuit operates in the serial transmit mode, the third circuit maintains the second circuit in an idle state, and when the controlling circuit operates in the I/O mode, the third circuit permits the second circuit to transmit the signal to the controlling circuit.

Abstract: A method and apparatus for providing peer-to-peer data transfer through an interconnecting fabric. The method and apparatus enable a first device to read and/or write data to/from a local memory of a second device by communicating read and write requests across the interconnectivity fabric. Such data transfer can be performed even when the communication protocol of the interconnectivity fabric does not permit such transfers.

Abstract: A data processing system includes a plurality of processing units, including at least a local master and a local hub, which are coupled for communication via a communication link. The local master includes a master capable of initiating an operation, a snooper capable of receiving an operation, and interconnect logic coupled to a communication link coupling the local master to the local hub. The interconnect logic includes request logic that synchronizes internal transmission of a request of the master to the snooper with transmission, via the communication link, of the request to the local hub.

Abstract: Method and system for arbitrating between plural arbitration requests is provided. The system includes a plurality of first stage arbiters that receive plural arbitration requests and a signal that indicates a previously granted request, wherein the first stage arbiters assert a high priority request signal if a high priority request is pending and a low priority request signal is asserted, if a low priority request is pending; a second stage arbiter that arbitrates between high priority requests, when high priority requests are pending; wherein if a high priority request is not pending, then a low priority request is granted; and a data handler module that operates in parallel with the second stage arbiter to immediately move data associated with a request that is granted at any given time.

Abstract: Embodiments of the present invention provide an advantage over prior art software architectures by allowing a kernel to send requests to and receive corresponding results from user space applications. Because the kernel can utilize user space applications, the kernel can use the results of complex calculations without requiring a significantly larger kernel. This provides advantages because programming and debugging of complex algorithms can occur at the user space level rather than the kernel space level.

Abstract: Technologies are described herein for governing access to a computing resource. A proxy receives a request to access a computing resource. In response to the request, the proxy determines whether the request can be granted without consulting a governor for the computing resource. If the request cannot be granted without consulting the governor, the proxy transmits the request to a broker. The broker, in turn, transmits the request to a governor for the computing resource. The governor determines whether the requested access to the computing resource should be granted. The governor generates a response to the request and transmits the response to the broker. The broker, in turn, transmits the response to the proxy. The broker may also request notifications from the governor.

Abstract: A method and apparatus for determining access protection (96) includes receiving a plurality of access requests (84) corresponding to a plurality of masters (12, 14), determining access permissions (86), providing state information (60), determining access permissions (86) based on the access request (84), and selectively modifying the access permissions based on the state information (90). The state information (60) may relate to debug operation, operation from unsecure or unverified memories, memory programming, direct memory access operation, boot operation, software security verification, security levels, security monitor operation, operating mode, fault monitor, external bus interface, etc (88).

Abstract: A device for data communication between a first host device or a further host device and at least one client device along a shared transmission path includes a first host device, which includes a host application; at least one further host device, which includes a host application; at least one client device, which includes a client application; a bus control module; the host devices and the client device(s) and the bus control module being connected to one another by the transmission path for exchanging data and/or signals and the bus control module being implemented to control the access of the host devices to the transmission path. A method of data communication running on this device provides the transmission path to the host device in the event the host device wishes access to the transmission path.

Abstract: A microcomputer includes a flash memory and a flash controller that controls access to the flash memory, the flash memory including a protection information storage section that stores protection information, the protection information indicating whether or not access to a given area of the flash memory is available; the flash controller including a flash protection section that performs a protection process relating to access to a given area of the flash memory based on the protection information; and the flash protection section performing the protection process relating to access to the flash memory when an access target is data.

Abstract: A network storage controller for transferring data between a host computer and a storage device, such as a redundant array of inexpensive disks (RAID), is disclosed. The network storage controller includes at least one channel interface module which is adapted to be connected to the host computer and storage device. The channel interface module is connected to a passive backplane, and selectively transfers data between the host computer and storage device and the passive backplane. The network storage controller also includes at least one controller memory module, attached to the passive backplane. The controller memory module communicates with the channel interface module via the passive backplane, and processes and temporarily stores data received from the host computer or storage device. In applications where redundancy is required, at least two controller memory modules and at least two channel interface modules are used.

Abstract: Access to a bus is granted to one of a number of requesting communication circuits that each submitted a bus control request during a request period of an arbitration period in response to the entries in a priority table. If a requesting communication circuit has an identity and priority that match the identity and priority of a communication circuit stored in a row of the priority table that corresponds with the arbitration period, access to the bus is granted to the requesting communication circuit.

Abstract: Disclosed is a method and system to partition hardware resources between operating systems. A determination is made whether a first PCI resource attached to a line of a bus is to be sequestered to a service operating system (OS). If so, the first PCI resource is sequestered to the service OS. It is next determined whether at least one other PCI resource shares the same line of the bus as the sequestered first PCI resource. If so, the at least one other PCI resource is selected and sequestered to the service OS. The first PCI resource and the other sequestered PCI resource are then hidden from a subsequently loaded host OS.

Abstract: A method and apparatus for dynamically arbitrating, in hardware, requests for a resource shared among multiple clients. Multiple data streams or service requests require access to a shared resource, such as memory, communication bandwidth, etc. A hardware arbiter monitors the streams' traffic levels and determines when one or more of their arbitration weights should be adjusted. When a queue used by one of the streams is filled to a threshold level, the hardware reacts by quickly and dynamically modifying that queue's arbitration weight. Therefore, as the queue is filled or emptied to different thresholds, the queue's arbitration weight rapidly changes to accommodate the corresponding client's temporal behavior. The arbiter may also consider other factors, such as the client's type of traffic, a desired quality of service, available credits, available descriptors, etc.

Abstract: A system and method to facilitate communication between a user interface and an associated process is disclosed. A first thread is associated with the user interface and a second thread is associated with the process for implementing requests by the user interface. At least one state buffer is operable to store state data for controlling ownership to the state buffer by the first and second threads for communicating data between the first and second threads. The architecture may be used in connection with a debugging system, such as to facilitate responsive interaction between the GUI and the associated debugging system.

Abstract: A random access memory system has a memory controller, a first memory device, a second memory device, and a memory bus. The memory controller is configured to control access to a plurality of memory devices. The memory bus is configured to alternatively couple the memory controller to the first memory device and to couple the memory controller to the second memory.

Abstract: A method, apparatus, and computer program product includes identifying a plurality of memory transactions to be sent over a memory bus to a memory having a plurality of memory banks, each memory transaction addressed to one of the memory banks, the memory bus incapable of transmitting the plurality of memory transactions simultaneously; identifying a plurality of bank readiness signals, each bank readiness signal indicating the readiness of one of the memory banks to accept a memory transaction; and selecting one of the memory transactions for transmission over the memory bus based on the bank readiness signals.

Abstract: Logic (also called “synchronizing logic”) in a co-processor (that provides an interface to memory) receives a signal (called a “declaration”) from each of a number of tasks, based on an initial determination of one or more paths (also called “code paths”) in an instruction stream (e.g. originating from a high-level software program or from low-level microcode) that a task is likely to follow. Once a task (also called “disabled” task) declares its lack of a future need to access a shared data, the synchronizing logic allows that shared data to be accessed by other tasks (also called “needy” tasks) that have indicated their need to access the same. Moreover, the synchronizing logic also allows the shared data to be accessed by the other needy tasks on completion of access of the shared data by a current task (assuming the current task was also a needy task).

Abstract: An apparatus and method for fairly arbitrating between clients with varying workloads. The clients are configured in a pipeline for processing graphics data. An arbitration unit selects requests from each of the clients to access a shared resource. Each client provides a signal to the arbitration unit for each clock cycle. The signal indicates whether the client is waiting for a response from the arbitration unit and whether the client is not blocked from outputting processed data to a downstream client. The signals from each client are integrated over several clock cycles to determine a servicing priority for each client. Arbitrating based on the servicing priorities improves performance of the pipeline by ensuring that each client is allocated access to the shared resource based on the aggregate processing load distribution.

Abstract: A bus system, which may prevent data from being incorrectly transferred when an early termination occurs during a burst mode, may include a bus, for example, an advanced high-performance bus (AHB), at least one bus master device, a bus arbiter and at least one transfer mode selection circuit. The at least one bus master device may generate a burst cycle control signal, a transfer start signal and a bus control request signal for requesting control of the bus, and may be activated in response to a bus control grant signal, so as to exchange data via the bus. The bus arbiter may generate the bus control grant signal in response to the bus control request signal and provide the bus control grant signal to the bus master device. The at least one transfer mode selection circuit may convert a burst mode into a single mode to generate a selection signal, when the bus control grant signal is deactivated before a burst mode operation is completed.

Abstract: Apparatus and methods to adaptively throttle accesses to memory employ a masking tool to specify the percentage of memory bandwidth available for access. The apparatus applies the mask and monitors the number of memory accesses during a throttle-monitoring window. If the number of memory accesses during the throttle-monitoring window exceeds or is fewer than the percentage of memory bandwidth specified by the mask, access to the memory continues until the end of the throttle-monitoring window and at the end of the throttle-monitoring window the apparatus selects the next lower mask for a lower memory bandwidth allocation or selects the next higher mask for a higher memory bandwidth allocation, respectively.

Abstract: A bus system including a bus arbiter and a plurality of masters. The bus arbiter grants bus control to one of the plurality of masters. When a master with bus control sends a read command, bus control is transferred to another one of the plurality of masters, thereby increasing the efficiency of the bus system. A method including sending a read command and transferring bus control to another one of a plurality of masters before receiving the response to the read command.

Abstract: A system and method of using metrics to control throttling and swapping in a message processing system is provided. A workload status of a message processing system is determined, and the system polls for a new message according to the workload status. The message processing system identifies a blocked instance and calculates an expected idle time for the blocked instance. The system dehydrates the blocked instance if the expected idle time exceeds a predetermined threshold.

Abstract: A multiple node network includes a plurality of terminal nodes. A management node manages the terminal nodes. A bus connects the respective terminal nodes and the management node to one another. The respective terminal nodes and the management node communicate with each other using a frame that includes at least an identifier field and a data field. The data field has a discriminative number. Each terminal node transfers the frame to the management node. A contention between the terminal nodes is arbitrated by comparing the respective identifier fields of the terminal nodes. When the arbitration fails, each terminal node repeatedly transfers the frame to the management node after a delay time that is unique for the particular terminal node and that is calculated based upon the discriminative number in the data field.

Abstract: In an ordered semaphore management system a pending state allows threads not competing for a locked semaphore to bypass one or more threads waiting for the same locked semaphore. The number of pending levels determines the number of consecutive threads vying for the same locked semaphore which can be bypassed. When more than one level is provided the pending levels are prioritized in the queued order.

Abstract: A method for arbitrating access to a resource shared by several electronic elements. Each element is allocated a first counting value and a first penalty, the first counting value is decremented in synchronization with a clock signal, and is incremented by a value equal to the first penalty every time the element is selected for an access cycle. When several elements are simultaneously waiting to access the shared resource, an element is selected to access the resource if its first counting value is lower than or equal to a determined threshold, and is lower than the first counting values of the other elements having sent an access request.

Abstract: A method and apparatus for providing channel bonding and clock correction arbitration in integrated circuits are disclosed. An arbitration device analyzes indicators to determine when clock correction request or a channel bonding request occur simultaneously. Then, the arbitration device determines whether to service the simultaneously occurring clock correction request first or a channel bonding request first based upon user selected arbitration logic.

Abstract: This invention provide a data processor capable of multiplexing data transfers with desired data transfer characteristics guaranteed, without multiplexing buses. The data processor includes: a transfer path that mutually connects plural processors and plural transfer element circuits such as memory; an arbitration circuit that controls data transfer in the transfer path; and a control register that defines the priority and minimum guaranteed bandwidth of data transfer. The arbitration circuit decomposes data packets sent from plural data transfer sources into subunits, and reconstructs plural data packets having the same data transfer target, based on priority and minimum guaranteed bandwidth stored in a control register. Thereby, the one reconstructed data packet can include subunits of plural data packets from transfer sources having different priorities, and data amounts of subunits contained in it can satisfy minimum guaranteed bandwidth of data transfer.

Abstract: An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding registers. An interrupt vector register has bit positions corresponding to different classes of interrupts. A read queue has inputs coupled to the plurality of interrupt holding registers and to the interrupt vector register. Detection logic is coupled between an arbiter, fed by the write and read queues, and a processor for: (a) indicating when an interrupt has passed from the write arbiter to the processor; (b) detecting the interrupt class of such passed interrupt; (c) enabling the one of the bit positions corresponding to the detected interrupt class in the interrupt vector register to store a state indicating the servicing requirement for such detected class of interrupt; and (d) wherein the data stored in the interrupt vector register is passed to the processor through the read queue and the arbiter selector.

Abstract: A method and system are provided for performing anticipatory changes to a resource governed by a locking mechanism. Entities (such as transactions in a database system) that want to modify a resource request permission to modify the resource. However, prior to receiving permission, they make anticipatory changes to a private version of the resource. The entities are prevented from making the anticipatory changes permanent until they receive permission to make the changes. Because they can make the changes, and proceed to other operations, before receiving permission, any delay in receiving permission has less adverse effect on their performance.

Abstract: An arbiter device arbitrating resource requests received at a plurality of input ports is proposed, which comprises an arbiter circuit that selects an input port to which a resource request is to be granted and successively grants a number of resource requests received at the selected input port.

Abstract: A system and method for migration of a virtual endpoint from one virtual plane to another are provided. With the system and method, when a management application requests migration of a virtual endpoint (VE) from one virtual plane (VP) to another, a fabric manager provides an input/output virtualization intermediary (IOVI) with an interrupt to perform a stateless migration. The IOVI quiesces outstanding requests to the virtual functions (VFs) of the VE, causes a function level reset of the VFs, deconfigures addresses in intermediary switches corresponding to the VP, and informs the fabric manager that a destination migration is requested. The fabric manager sends an interrupt to the destination IOVI which performs a function level reset of the destination VFs and reprograms the intermediary switches with the addresses of the destination VP. The destination VFs may then be placed in an active state.

Abstract: A system and method for migrating domains from one physical data processing system to another are provided. With the system and method, domains may be assigned direct access to physical I/O devices but in the case of migration, the I/O devices may be converted to virtual I/O devices without service interruption. At this point, the domain may be migrated without limitation. Upon completion of the migration process, the domain may be converted back to using direct physical access, if available in the new data processing system to which the domain is migrated. Alternatively, the virtualized access to the I/O devices may continue to be used until the domain is migrated back to the original data processing system. Once migration back to the original data processing system is completed, the access may be converted back to direct access with the original physical I/O devices.

Abstract: A communication module includes a switch circuit operable to connect an internal bus to an external bus for, e.g., diagnostics, verification, and fault analysis. The internal bus allows data communication between electronic components internal to the communication module, and the external bus allows data communication between at least one internal electronic component and a device external to the communication module. The switch circuit may be controlled via a programmable and password protected register within the communication module.

Abstract: A storage system is disclosed for performing control to match data among cache memories corresponding to shared volumes when multiple disk controllers containing cache memories are accessing shared volumes formed in the storage device. The storage system contains a switch for switching and connecting the multiple disk controllers containing cache memories, with a disk array containing the shared volumes capable of being commonly accessed from the multiple disk controllers. The switch performs exclusive access control of the multiple disk controllers' writing on the shared volumes, and performs control to match data other than modified data among the cache memories.

Abstract: The system includes an arbiter, a combined engine, a frame buffer, and a display processing unit. The arbiter provides three input channels: a first channel for graphics, a second channel for video and a third channel for processor. The arbiter performs prioritization and arbitration between the video and graphics and processor requests sent to the system. The arbiter has three output ports coupled to the combined engine. The combined engine is a hardware engine capable of processing either video data or graphics data. The output of the combined engine is provided to the frame buffer for the storage of pixel data. The output of the frame buffer is coupled to a display processing unit that renders the pixel data for display.

Abstract: A priority register is provided for each of a multiple processor cores of a chip multiprocessor, where the priority register stores values that are used to bias resources available to the multiple processor cores. Even though such multiple processor cores have their own local resources, they must compete for shared resources. These shared resources may be stored on the chip or off the chip. The priority register biases the arbitration process that arbitrates access to or ongoing use of the shared resources based on the values stored in the priority registers. The way it accomplishes such biasing is by tagging operations issued from the multiple processor cores with the priority values, and then comparing the values within each arbiter of the shared resources.

Abstract: Provided are an arbiter capable of improving memory access efficiency in a multi-bank memory, a memory access arbitration system including the arbiter, and an arbitration method thereof, where the arbiter detects requests that are not included in a busy bank, and allows the requests corresponding to a bank receiving the largest number of pending requests priorities; and write request information generated by masters is stored in a predetermined buffer to be output as additional master request information, and provides the corresponding master with an opportunity to generate new request information.

Abstract: A method, system, and firewall for controlling access to resources within an information technology (IT) system. Commands received from a requesting entity request access to a resource associated with each command. An assigned authority level of the requesting entity is identified. At least one required authority level of the requesting entity is determined for each command as a function of each command and a resource criticality classification of the resource associated with each command. The requesting entity is granted or denied the requested access to the resource associated with each command if a determination has been made that each condition of at least one specified condition has or has not been satisfied, respectively. The at least one specified condition is specific to each command and includes a condition of the assigned authority level matching or exceeding an authority level of the at least one required authority level of each command.

Abstract: Systems, methods, apparatus and software can utilize an extent guard to prevent modification (including relocation) of data in the storage resource while a third-party copy operation directed at the storage resource is occurring. A data transport mechanism such as a data restore application provides an extent list to the extent guard, which monitors read and/or write activity to storage resources described by the extent list. The data transport mechanism requests a data mover to perform a third-party copy operation whereby data is moved from a data source to the storage resource. If a modification attempt is made on the portion of the storage resource described by the extent list, the extent guard stalls the modification attempt until the third-party copy operation is aborted.

Abstract: A system control device comprises a system LSI section having a plurality of functional blocks, a system control microcomputer section for controlling the control register of each of the functional blocks, an address decoding section for decoding an access address to a predetermined byte in a control register which the system control microcomputer section attempts to access, and issuing an access control signal to the whole of a single control register including the predetermined byte, an access control section for changing the access control signal to the whole of the single control register to an access control signal to the predetermined bytes of the plurality of control registers included in the system LSI section, with respect to access to an address to the predetermined byte, and an access mode control register for indicating whether or not the changing by the access control section is to be performed.

Abstract: An apparatus and method for scheduling requests to a source device is provided. The apparatus comprises a high-priority request queue for storing a plurality of high-priority requests to the source device; a low-priority request queue for storing a low-priority request to the source device, wherein a priority of one of the high-priority requests is higher than the priority of the low-priority request; a history counter for storing an information related to at least one requesting interval between two adjacent high-priority requests; and a scheduling module for scheduling the high-priority requests and the low-priority request according to the information.