Abstract: A data processing system is provided comprising at least one processing unit for processing data; a memory means for storing data; and a cache memory means for caching data stored in the memory means. Said cache memory means is associated to at least one processing unit. An interconnect means is provided for connecting the memory means and the cache memory means. The cache memory means is adapted for performing a cache replacement based on reduced logic level changes of the interconnect means as introduced by a data transfer between the memory means and the cache memory means.

Abstract: A memory control apparatus disposed in a memory access system having a bus, a single storage unit with a bank structure and a bus arbitrating unit, includes: an access-request accepting means for accepting sequential access requests for data located at sequential addresses in the storage unit, sequential access requests for data located at discrete addresses in the storage unit as sequential access requests, or access requests for data located at sequential addresses in the storage unit which cannot be made into a single access request as sequential access requests; and an access-request rearranging means for rearranging sequential access requests accepted by the access-request accepting means in an order of banks of the storage unit within a range of access requests relating to either a data write request output from one of data processing units or a data read request output therefrom to control an access control of the storage unit.

Abstract: A method and apparatus for arbitrating on a high performance serial bus is disclosed. The invention provides for a plurality of arbitration phases and an arbitration advancing means.

Abstract: A technique for improving usage efficiency of a shared resource and improving processing capacity in an information processing apparatus, without increasing the transmission rate or the bit width of a bus is disclosed. Multiple bus interfaces are connected to at least one shared resource. The multiple bus interfaces are connected to a multi-layer bus respectively. Furthermore, data buffers for holding read data and write data respectively are provided for each bus interface. An arbiter arbitrates access requests from the respective bus interfaces, and the shared resource reads and writes data in response to the access request which has been given an access right.

Abstract: An arbitration device arbitrates among master devices such that each master device is allowed to access a shared memory at a predetermined bandwidth, and the arbitration device permits an access request in a first period that a designer has set as desired if the access request has been made by a specific master device beyond a bandwidth that has been allocated in advance. The arbitration device masks an access request from the specific master device in a second period that follows the first period.

Abstract: A system and method is disclosed for initializing PCI devices in a computer system or information handling system. Upon initialization of the system, each operating system instance of the system attempts to access a PCI bridge device. The first operating system to access the bridge device is granted ownership of the bridge device and the authority to initialize each PCI device coupled to the bridge device. The bridge device assigns each operating system to at least one context included in at least one of the PCI devices. After each of the PCI devices has been initialized, a configuration event is issued with respect to each operating system instance and each assigned PCI device, thereby causing each operating system to recognize each PCI device assigned to each respective operating system instance.

Abstract: The disclosure provides a system and method of provisioning a resource to an electronic device. The method comprises: after a triggering event, receiving from a network a data transmission at the device, the data transmission containing access information relating to a resource in a library that is in a remote server from the device, the resource relating to an application operating on the device; extracting the access information from the data transmission at the device; presenting the access information for the resource in a graphical user interface (GUI) on a display of the device; and after a selection event is initiated on the device for the resource, initiating a second data transmission containing a copy of the resource to the device and integrating the resource into the application as an output generated by the application.

Abstract: A memory system includes: a memory that has plural banks; a memory controller that includes a request queue and a bank monitor and controls access to the memory; a master group including plural masters that can request access to the memory; and a system bus which is connected between the memory controller and the master group and in which an arbiter is arranged, wherein the request queue has a scheduling function for receiving access requests issued from the master group through the system bus and appropriately rearranging the received access requests and provides the arbiter with queue information, the bank monitor monitors information concerning respective banks of the memory and provides the arbiter with the bank information, and the arbiter arbitrates requests issued in parallel from the masters of the master group on the basis of the queue information and the bank information provided thereto and transmits the information to the memory controller as access control information.

Abstract: A resource allocation method for performing resource competition between protocols based on a protocol in a home network environment using multiple protocols is provided. In the resource allocation method, a request of using a resource is received from an external device. An AIFS value is allocated according to a data type of the resource requested from the device. Then, the resource is not provided to the device for an AIFS period. After passing the period of the AIFS value, a back-off timer period is entered. In the back-off timer period, an application protocol of the external device requesting the resource is identified, and an idle time value is allocated according to a type of the identified protocol. Then, a corresponding resource is provided to the first device coming out of the allocated idle time.

Abstract: A device that includes: a first bus, connected between a first logic and a first circuit; a group of second buses connected between the first logic and between multiple non-high impedance circuit access logics associated with multiple circuits; wherein each circuit access logic is adapted to: (i) provide to the first logic, a circuit write value during a circuit writing period and during an idle period that follows the circuit writing period and ends when another circuit is allowed to write; and (ii) provide a default value when another circuit is allowed to write; and wherein the first logic is adapted to alter a state of the first bus in response to a change between two consecutive circuit write values.

Abstract: Requestors issue access requests to a memory controller. The access requests issued are accumulated in a command queue of the memory controller. When the amount of access requests accumulated in the command queue is smaller than or equal to a threshold, a free pass (FP) is granted to specified requesters. When issuing access requests, requesters request and acquire tokens before issuing the access requests if they have no FP granted. If the requesters have an FP, they simply issue the access requests.

Abstract: A data transfer system includes: a shared resource accessed from one or more devices; a plurality of request generation units each configured to generate a request for the device to access the shared resource, and output a remaining time value indicating how much time remains until the request is accepted before affecting an operation of an apparatus including the controller; and an arbitration unit configured to compare the remaining time values when the plurality of requests and the remaining time values are inputted from the plurality of request generation units, and give an access right to access the shared resource to a request with less remaining time.

Abstract: A data replication engine is controlled in a system that replicates data associated with a plurality of transactions from a source database to a target database. The system includes a change queue that contains transaction data associated with the transactions. The system maintains one or more attributes outside of the change queue which are associated with transactions. One or more attributes outside of the change queue are identified which are associated with a transaction. The one or more of the identified attributes are then used to control the replication engine.

Abstract: An arbitration device arbitrates among master devices such that each master device is allowed to access a shared memory at a predetermined bandwidth, and the arbitration device permits an access request in a first period that a designer has set as desired if the access request has been made by a specific master device beyond a bandwidth that has been allocated in advance. The arbitration device masks an access request from the specific master device in a second period that follows the first period.

Abstract: Provided is an access right managing method for a resource of a storage system, in which a management computer stores access right definition information of the resource, and resource correspondence information including information on a management program which manages another resource related to the resource managed by the management program. In case of which receiving an updating request of an access right of the resource, the management computer updates an access right based on the updating request of the access right, selects a management program of the resource whose access right is requested to be updated based on the resource correspondence information, transmits an updating request of an access right for a relative resource to a management computer which executes the selected management program, and in case of which the access right updating request of the related resource is received, updates the access right of the relative resource.

Abstract: For arbitrating access to a shared memory device among a plurality of masters, a master generates a request for access signal that is sent to the arbitrator concurrently with an indispensable command such as an auto-refresh command that is generated in series. The arbitrator generates an acknowledge signal sent to the master for indicating approval or rejection for access. Existing pins of the master are used for transmission of such arbitration signals.

Abstract: Techniques are provided for performing changes to a resource governed by a locking mechanism. An entity (such as a server instance in a database system cluster) requests permission to modify the resource. In response to the request, the entity receives a first lock on the resource, which grants permission to perform the change to the resource without making the change permanent. After receiving the first lock, the entity performs the change to a copy of the resource that resides in shared memory without making another copy of the resource. After performing the change and until receiving permission to make the change permanent, the entity prevents the change to the resource from becoming permanent. After performing the change, the entity receives a second lock on the resource, which grants the entity permission to make the change permanent. After receiving the second lock, the entity ceases to prevent the change to the resource from becoming permanent.

Abstract: The invention provides a system and method of provisioning a resource to an electronic device. The method comprises the steps of: (a) maintaining a library of resources at a remote server from the device; (b) after a triggering event, providing a data transmission to the device, the data transmission containing access information for the library that can be extracted by the device and used to access the library; and (c) after a selection event initiated on the device for a specific resource from the library, providing a second data transmission to the device, the second data transmission containing a copy of the specific resource. The system provides a server, a resource, a device and a communication link incorporating the method.

Abstract: Interoperable firmware for an information handling system supports embedded controller and chipset operations from a common SPI flash ROM. The embedded controller is disposed between the chipset and the flash ROM with a pass through port integrated in the embedded controller selectively providing primary access to firmware by the chipset or the embedded controller. The pass through port provides chipset access to firmware without inducing delays for normal system operations, yet provides an integrated switch for control and access of the firmware by the embedded controller for updating of firmware settings and firmware diagnostics. Application of power to the embedded controller allows access to chipset firmware even where the chipset lacks power, such as during manufacture of the information handling system.

Abstract: A method for preventing deadlocks in a multiprocessing environment is provided. The method comprises receiving one or more strongly connected components (SCCs) as input, wherein a first SCC represents a set of locks such that each pair of locks in the set may potentially be involved in a deadlock situation; creating a first gate lock for the first SCC, wherein a first process or process element acquires the first gate lock before acquiring a first lock in the first SCC and releases the first gate lock after releasing a number of locks in the first SCC; and removing the first gate lock, in response to determining that the first gate lock introduces new deadlocks.

Abstract: In a multi-tasking pipelined processor, consecutive instructions are executed by different tasks, eliminating the need to purge an instruction execution pipeline of subsequent instructions when a previous instruction cannot be completed. The tasks do not share registers which store task-specific values, thus eliminating the need to save or load registers when a new task is scheduled for execution. If an instruction accesses an unavailable resource, the instruction becomes suspended, allowing other tasks' instructions to be executed instead until the resource becomes available. Task scheduling is performed by hardware; no operating system is needed. Simple techniques are provided to synchronize shared resource access between different tasks.

Abstract: A dynamic arbitration controller includes components for reading current state information as well as records of known arbitration states which may cause a deadlock condition, comparing the current state to the records of known arbitration states and resolving deadlock conditions during arbitration. The dynamic arbitration controller may include circuits for storing and retrieving information related to the arbitration. The dynamic arbitration controller may be implemented as a circuit design or as a computer program product stored on machine readable media.

Abstract: The present invention provides a peripheral apparatus control method, and an information processing apparatus and control method that can correctly manage and display a status of each individual peripheral apparatus, even when a plurality of peripheral apparatuses is allocated to a single queue.

Abstract: A single bus apparatus enables the simultaneous execution of both high-speed data transfer, which requires real time operation, and low-speed data transfer. At least one of slaves I/F 22-0, 22-1, . . . that control slave devices SV0-SV3 upon the request from master devices MS0-MS3 connected to interconnection bus BS via master I/Fs 21-0 through 21-3 has a constitution made of multiport slave I/F 23 corresponding to a multi-access function that allows simultaneous access from plural master devices MS0-MS3.

Abstract: Systems, methods, and computer program products are presented for transiently clearing a reservation on a device, where the reservation belongs to a host that owns the device and the reservation blocks a host that does not own the device from performing an operation with the device. The reservation is cleared transiently by the host that does not own the device. While the reservation is cleared, the operation is performed with the device using the host that does not own the device.

Abstract: A method, apparatus, and computer program product are disclosed in a data processing system for migrating data pages subject to DMA access by temporarily disabling selected DMA operations within a physical I/O adapter. A determination is made as to whether to disable data access DMA capabilities of the physical I/O adapter. An operating mode of the physical I/O adapter is set to a particular mode utilizing a mode bit according to the determination of whether to disable data access DMA capabilities. Only data access DMA capabilities of the physical I/O adapter are disabled when the mode bit is set. Administrative services operations continue to be performed by the physical I/O adapter when the data access DMA capabilities of the physical I/O adapter are disabled.

Abstract: Plural arbiters simultaneously arbitrate among common elements of a resource. Conflict detection logic detects conflicts among the arbiters accessing the elements of the resource, and, when a conflict is detected, the conflict logic invalidates processing relating to the conflict in one of the conflicting arbiters.

Abstract: A method of operating a processor bus, with which a central unit (processor) makes accesses to various peripheral units, is described. The processor bus has the ability to change the order of the accesses as a function of the operating state of the peripheral units, and the peripheral units can either reject or delay the access.

Abstract: A resource-lock monitor detects when processors in a multi-processor system are stuck waiting for access to a shared resource. A lock-monitor register has a lock bit and a sticky-lock bit for each processor being monitored. The lock and the sticky-lock bits are both set when the processor executes a lock instruction that also sends a lock-request to a resource arbiter. The lock bit is cleared when the resource arbiter grants access to the processor, but the sticky-lock bit remains set until sticky-lock bits are cleared by monitoring software at the end of a monitoring period. At the end of each monitoring period, monitoring software reads the lock and sticky-lock bits and finds a locked processor when a processor's lock bit is still set, but its sticky-lock bit is cleared. When the locked processor remains locked at the end of another monitoring period, an error handler resets the locked processor.

Abstract: A job is submitted into a first selection of resources in a grid environment from among a hierarchy of discrete sets of resources accessible in the grid environment. Discrete sets of resources may include locally accessible resources, enterprise accessible resources, capacity on demand resources, and grid resources. The performance of the first selection of resources is monitored and compared with a required performance level for the job. If the required performance level is not met, then the discrete sets of resources are queried for available resources to meet the required performance level in an order designated by said hierarchy. Available resources in a next discrete set of resource from the hierarchy of discrete sets of resources are added to a virtual organization of resources handling the job within the grid environment.

Abstract: Anti-pirate circuitry is provided for combating the theft of intellectual property contained with semiconductor integrated circuits. The anti-pirate circuit includes a unique number generator that provides a multi-bit die ID data string that is unique to the integrated circuit associated with the anti-pirate circuit. One time programmable (OTP) EPROM circuitry reads the die ID data string at wafer sort and writes the data content to nonvolatile memory. During a subsequent verification cycle, ID comparator circuitry compares the data string provided by the unique number generator to the stored contents of the nonvolatile memory. If the comparison results in a mismatch between more than a predefined number of bits, then the integrated circuit associated with the anti-pirate circuit is not enabled for operation.

Abstract: A data processing system comprising a plurality of processing units (Dv1-DvM) for processing data, at least one memory means (MM) for storing data from said plurality of processing units (Dv1-DvM), an interconnect means (IM) for connecting said plurality of processing units (Dv1-DvM) and said at least one memory means (MM) is provided. Said processing units (Dv1-DvM) are adapted to request a write access to said at least one memory means (MM) via the interconnect means (IM) in order to write data into said at least one memory means (MM). At least one arbiter means (AU) is provided for performing an interconnect arbitration for the access to said at least one memory means (MM) from said plurality of processing units (Dv1-DvM), wherein said interconnect arbitration is performed based on the minimum logic level changes of said interconnect means (IM) as introduced by the write accesses of said plurality of processing units (Dv1-DvM) to said at least one memory means (MM).

Abstract: An adapter unit operative to support access of an SATA storage device by a plurality of hosts associated with separate host adapters. The adapter unit includes a multiplexer coupled to an arbiter. The multiplexer receives a plurality of sets of communication signals, one signal set for each host adapter. The multiplexer then selects one of the signal sets based on a control signal and couples the selected signal set to its output. The arbiter receives requests from the hosts to access the SATA storage device, selects a particular requesting host, and provides the control signal indicative of the specific host granted access. The host adapter for the granted host and the SATA storage device are placed in a PHY READY power management state, prior to a read or write access, and are placed in a PARTIAL power management state after the read or write access.

Abstract: Method and system for managing interrupts originating from multiple sources is provided. The method includes assigning interrupt sources to a group; notifying an adapter of interrupt groups; identifying each interrupt group; writing a first interrupt to an interrupt module, where the interrupt occurs from a first source of the multiple sources; monitoring for a second interrupt; suspending the second interrupt until the first interrupt is processed, if the second interrupt is requested from the first source; and processing the second interrupt, if the second interrupt occurs from a source other than the first source.

Abstract: Methods and apparatus provide for: assigning each of a plurality of requesters to a respective one of a plurality of requester groups; receiving tokens from a plurality of resources, where each token is an exchange medium for permitting one of the requesters having the token to access an associated one of the resources for a period of time; receiving requests for the tokens from one or more of the requesters; allocating the tokens to at least one of the respective requester groups and the requesters thereof based on token allocation criteria; and dynamically re-assigning one or more of the requesters among the requester groups based on feedback information concerning at least some prior token allocations.

Abstract: A method and a Fibre Channel switch element are provided that allows communication between a host system and a target device attached to a proprietary switch fabric in a network. The Fibre Channel switch element includes a first port that communicates with the target device through the proprietary switch fabric by logging on behalf of the host system so that the proprietary switch behaves as if it was directly communicating with the host system; and a second port that communicates with the host system and collects host bus adapter (“HBA”) identification information, wherein the HBA identification information is used to map the first port to the second port so that when the host system communicates with the target device the Fibre Channel switch element is transparent to the proprietary switch fabric.

Abstract: A system and firewall for controlling access to resources within an information technology system. Commands received from a requesting entity request access to a resource associated with each command. An assigned authority level of the requesting entity is identified. At least one required authority level of the requesting entity is determined for each command as a function of each command and a resource criticality classification of the resource associated with each command. The requesting entity is granted or denied the requested access to the resource associated with each command if a determination has been made that each condition of at least one specified condition has or has not been satisfied, respectively. The at least one specified condition is specific to each command and includes a condition of the assigned authority level matching or exceeding an authority level of the at least one required authority level of each command.

Abstract: A peripheral switching device includes an ownership switch request receiver unit configured to receive an ownership switch request for requesting to assign a peripheral to an operating system; an ownership request holding unit configured to receive and hold an ownership request for requesting to ensure or release an ownership of a peripheral to an operating system; a switching judgment unit configured to judge whether or not to execute an assignment of a peripheral to an operating system, in accordance with the ownership switch request and the ownership request; and a switching execution unit configured to execute the assignment of the peripheral to the operating system, in accordance with the judgment result.

Abstract: Method and apparatus for arbitrating prioritized cycle streams in a manner that prevents starvation. High priority and low priority arbitration pools are employed for arbitrating multiple input cycle streams. Each cycle stream contains a stream of requests of a given type and associated priority. Under normal circumstances in which resource buffer availability for a destination device is not an issue, higher priority streams are provided grants over lower priority streams, with all streams receiving grants. However, when a resource buffer is not available for a lower priority stream, arbitration of high priority streams with available buffer resources are redirected to the low priority arbitration pool, resulting in generation of grant counts for both the higher and lower priority streams.

Abstract: A system and method for real-time load balancing of user workload across a plurality of physical storage systems with shared back-end storage is provided. A load balancing process tracks usage metrics and determines a source and destination physical storage system and a virtual storage system (vfiler) to be migrated.

Abstract: The present invention discloses a host receiver synchronizer for passive optical networks, and in particular a burst clock data recovery circuit in a host receiver in a bursty asynchronous communication system having a non-data preamble of less than 250 ns, for recovering a clock signal from a subscriber data burst. The circuit comprises: an adjustable oscillator for generating an output clock signal in response to a signal at an input thereof; a first comparator for comparing a frequency and phase of the output clock signal to that of a reference signal and feeding back a first feedback signal to the oscillator input; and a second comparator for comparing the frequency and phase of the output clock signal to that of the data burst and feeding back a second feedback signal to the oscillator input once the output clock signal is locked in frequency with the reference signal. The output clock signal is locked in frequency and phase to the data burst before receipt of the last bit of the preamble.

Abstract: In one embodiment, the present invention includes a predictor to predict contention of an operation to be executed in a program. The operation may be processed based on a result of the prediction, which may be based on multiple independent predictions. In one embodiment, the operation may be optimized if no contention is predicted. Other embodiments are described and claimed.

Abstract: The system includes an arbiter, a combined engine, a frame buffer, and a display processing unit. The arbiter provides three input channels: a first channel for graphics, a second channel for video and a third channel for processor. The arbiter performs prioritization and arbitration between the video and graphics and processor requests sent to the system. The arbiter has three output ports coupled to the combined engine. The combined engine is a hardware engine capable of processing either video data or graphics data. The output of the combined engine is provided to the frame buffer for the storage of pixel data. The output of the frame buffer is coupled to a display processing unit that renders the pixel data for display.

Abstract: A system includes at least one memory and at least one processor. The at least one memory is operable to store a resource object associated with a resource. The at least one memory is also operable to store a plurality of requester objects associated with at least a portion of one or more processes. The one or more processes are associated with production of one or more products using the resource. The at least one processor is operable to arbitrate between multiple arbitration requests from multiple ones of the requester objects. Each arbitration request indicates that one of the requester objects is attempting to acquire the resource object so that the associated resource is used to produce one of the products. The at least one processor is operable to use one or more user-defined strategies to arbitrate between the multiple arbitration requests.

Abstract: The present disclosure relates to acquiring and releasing a shared resource via a lock semaphore and, more particularly, to acquiring and releasing a shared resource via a lock semaphore utilizing a state machine.

Abstract: A method and computer system for efficiently handling high contention locking in a multiprocessor computer system. The method organizes at least some of the processors in the system into a hierarchy, and processes an interruptible lock in response to the hierarchy. The method utilizes two alternative methods of acquiring the lock, including a conditional lock acquisition primitive and an unconditional lock acquisition primitive, and an unconditional lock release primitive for releasing the lock from a particular processor. In order to prevent races between processors requesting a lock acquisition and a processor releasing the lock, a release flag is utilized. Furthermore, in order to ensure that the a processor utilizing the unconditional lock acquisition primitive is granted the lock, a handoff flag is utilized.

Abstract: A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access by the function ports. The memory interface advantageously allows multiple simultaneous accesses of memory banks via a plurality of macro functions, each access under the control of a parent processor instruction. A standardized protocol used for memory read/write operations is also disclosed.

Abstract: In accordance with embodiments, there are provided mechanisms and methods for suspending work by a resource adapter. These mechanisms and methods for suspending work by a resource adapter can enable embodiments to provide the capability to start and stop work performed by a resource adapter to connector architectures. The ability of embodiments to provide the capability to start and stop work performed by a resource adapter can enable users of Connector Architectures to quiesce an adapter's inbound/outbound or work sections. Such capability can enable an adapter embodiment to complete in-flight transactions but not accept new inbound transactions until a request to resume operation is received. Resource adapters may be quiesced during a versioning or change out process or other maintenance processes for example.

Abstract: There is provided a media access controller with a power-save mode. Particularly, the media access controller of the present invention minimizes power loss by disabling clocks applied to all blocks, including CPU, of the media access controller during the power-save mode. The media access controller of the present invention includes: a power-save master for securing stable transmission/reception of data through bus by respective processors contained in the controller; a wake-up timer for noticing that the power-save mode is expired; a power control unit for determining whether to supply a power to a phase-locked loop, and a timing when clocks for the media access controller are applied and disabled; and a locktime register for storing a locktime when an output of the phase-locked loop is settled. Additionally, there is provided a method of efficiently changing the media access controller from the active mode to the power-save mode, and vice versa.

Abstract: A method and system that creates and maintains lock properties for a resource or object in a distributed environment. The method and system creates and/or updates lock objects to relate to multiple locks, i.e., multiple resources. The method and system creates and maintains lock properties for a resource or object in a distributed environment.