Abstract: A resource allocation method for performing resource competition between protocols based on a protocol in a home network environment using multiple protocols is provided. In the resource allocation method, a request of using a resource is received from an external device. An AIFS value is allocated according to a data type of the resource requested from the device. Then, the resource is not provided to the device for an AIFS period. After passing the period of the AIFS value, a back-off timer period is entered. In the back-off timer period, an application protocol of the external device requesting the resource is identified, and an idle time value is allocated according to a type of the identified protocol. Then, a corresponding resource is provided to the first device coming out of the allocated idle time.

Abstract: An arbiter is used so multiple users can use shared resources. The arbiter allocates at least one of the resources speculatively to one of the users for use during a particular access interval in the absence of a request for the resource from the user. The arbiter can also allocate one or more of the resources for use during the particular access interval in response to requests received by the arbiter for the resource(s). That is, a particular access interval may include both speculative and non-speculative allocation of resources by the arbiter.

Abstract: Methods and apparatus provide for: assigning each of a plurality of requesters to a respective one of a plurality of requester groups; receiving tokens from a plurality of resources, where each token is an exchange medium for permitting one of the requesters having the token to access an associated one of the resources for a period of time; receiving requests for the tokens from one or more of the requesters; allocating the tokens to at least one of the respective requester groups and the requesters thereof based on token allocation criteria; and dynamically re-assigning one or more of the requesters among the requester groups based on feedback information concerning at least some prior token allocations.

Abstract: A memory controller to arbitrate memory request queues based upon priorities corresponding to the request queues, comprising logic to serve the request queue whose priority is equal to the maximum of the priorities. An embodiment may further comprise a timer corresponding to a request queue, where the priority of the request queue is changed from a low value to a high value if the timer expires while the request queue is not empty. In some embodiments, when the request queue is emptied after its timer has expired, the timer is set, and then started again once a new request enters the empty request queue.

Abstract: An apparatus a first processor which receives a data transfer request and generates a service command that corresponds to a scalable logic block required to respond to the data transfer request, and a server computer that receives the service command and scales the scalable logic block in accordance with the service command.

Abstract: A method and a Fibre Channel switch element are provided that allows communication between a host system and a target device attached to a proprietary switch fabric in a network. The Fibre Channel switch element includes a first port that communicates with the target device through the proprietary switch fabric by logging on behalf of the host system so that the proprietary switch behaves as if it was directly communicating with the host system; and a second port that communicates with the host system and collects host bus adapter (“HBA”) identification information, wherein the HBA identification information is used to map the first port to the second port so that when the host system communicates with the target device the Fibre Channel switch element is transparent to the proprietary switch fabric.

Abstract: A data transfer apparatus includes a memory having first and second queues for storing data transfer information that includes information specifying a first memory area and information specifying a second memory area, a first processor which registers the data transfer information in the first or second queue, and a second processor performing a processing to transfer data stored in the first memory area to the second memory area. The second processor reads out the data transfer information registered in the first queue, transfers the data based on the read data transfer information, and decides if data transfer information succeeding to the read data transfer information is registered in the first queue. If the succeeding data transfer information is registered, the second processor reads out the succeeding data transfer information from the first queue, and performs the data transfer processing based on the read data transfer information.

Abstract: A method of verifying a circuit implementing a data transfer protocol is disclosed. According to one embodiment of the invention, the method comprises steps of providing a block under test that implements a variable latency data transfer protocol; coupling a verification circuit to the block under test; enabling variable latency data transfers to the block under test; and verifying that the block under test is implementing the variable latency data transfer protocol. The method could be implemented to verify the operation of a memory controller of an FPGA, for example. According to another embodiment, a method enabling a multi-stage verification is disclosed. Finally, specific implementations of a verification circuit coupled to an on-chip memory controller of an FPGA are disclosed.

Abstract: An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding registers. An interrupt vector register has bit positions corresponding to different classes of interrupts. A read queue has inputs coupled to the plurality of interrupt holding registers and to the interrupt vector register. Detection logic is coupled between an arbiter, fed by the write and read queues, and a processor for: (a) indicating when an interrupt has passed from the write arbiter to the processor; (b) detecting the interrupt class of such passed interrupt; (c) enabling the one of the bit positions corresponding to the detected interrupt class in the interrupt vector register to store a state indicating the servicing requirement for such detected class of interrupt; and (d) wherein the data stored in the interrupt vector register is passed to the processor through the read queue and the arbiter selector.

Abstract: In an arbitration device, the entire transfer efficiency is improved without increasing the operating frequency and the number of pins. An overflow monitor mechanism generates an alarm once detecting a danger of occurrence of an overflow in an internal buffer group. An arbiter dynamically changes the priority order of arbitration once receiving the alarm from the overflow monitor mechanism and gives priority to processing of a request from a buffer having a danger of occurrence of an overflow.

Abstract: An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding registers. An interrupt vector register has bit positions corresponding to different classes of interrupts. A read queue has inputs coupled to the plurality of interrupt holding registers and to the interrupt vector register. Detection logic is coupled between an arbiter, fed by the write and read queues, and a processor for: (a) indicating when an interrupt has passed from the write arbiter to the processor; (b) detecting the interrupt class of such passed interrupt; (c) enabling the one of the bit positions corresponding to the detected interrupt class in the interrupt vector register to store a state indicating the servicing requirement for such detected class of interrupt; and (d) wherein the data stored in the interrupt vector register is passed to the processor through the read queue and the arbiter selector.

Abstract: An arbitration method, for a data bus in an architecture having n functional blocks, regulates access to the bus. The method includes: receiving, at one of plural agents, information from one of the functional blocks via high level primitives. Each agent generates in response a critical rank vector comprising at least first and second components. An arbitrator receives the critical rank vectors generated by rival the agents and applies a maximum or minimum extracting mechanism to at least one of the two components of the critical rank vectors to uniquely identify the block accessing the resource. Thus, functional blocks can be separated from arbitration control, the agents implementing the arbitration control and being solely responsible for it.

Abstract: Disclosed is a method and apparatus for arbitration between multiple pipelines over shared resources for an SMP computer system. The computer includes logic to defer arbitration until later in the pipeline to help reduce latency to each pipeline. Also, introduced is the concept of retry tags for better priority to avoid lock-out. The system also includes round-robin tokens to manage rejected requests to allow better fairness on conflicts. While the processing logic employed specifically applies to cross-interrogation, the logic can be extended to other common resources. The illustrated SMP computer system also has self-correcting logic to maintain good round-robin tokens.

Abstract: A bus system includes one or more bus masters, one or more bus slaves, and a response unit. When an access request to a resource of a bus slave is sent from a bus master, the response unit outputs a wait response that is either a blocking wait response to cause the bus master to perform a blocking wait operation or a non-blocking wait response to cause it to perform a non-blocking wait operation to the bus master if the bus slave is in the wait state.

Abstract: In a bus arbitration device that utilizes a resource use management device, upon detecting that a processor is permitted to access a memory, a detection unit decreases a counter by 1 and starts a timer, in a delay circuit, that is not in operation to count time. When the timer counts to a predetermined cycle time period, the delay circuit increases the counter by 1. A control unit permits the processor to access the memory, if the counter is larger than 0.

Abstract: The present invention provides a DMA transfer controller includes: a transfer parameter storing unit for storing a bus occupation time value and transfer parameters of one set or a plurality of sets of DMA transfers for each of a plurality of logical processors; a data transfer performing unit for performing the DMA transfer on the basis of the DMA transfer parameters; a control unit for controlling the receive and transmit of the DMA transfer parameters and the start and the interruption of the DMA transfers; and a time measuring unit for starting to measure bus occupation elapse time when a first DMA transfer is started for each of the logical processors. When the bus occupation elapse time reaches the bus occupation time value, the control unit interrupts the DMA transfer that is currently performed to start the DMA transfers based on the transfer parameters related to the logical processors of a prescribed sequence.

Abstract: A task management system that inherit priority and that can reduce the queue operation required for transition to/return from a mutual exclusion awaiting state The task management system can execute a task without considering its priority, start or stop a server task and inherit priority without operating the dispatch queue. The task management system includes activity retaining information, context retaining information, and a dispatch queue used to select the highest priority task. Information on a task is divided and managed by the activity and the context, where each activity is inserted into/deleted from the dispatch queue. When the priority of a task is inherited by another task, only the correspondence between activity and context is changed.

Abstract: An apparatus for arbitration within a data processing apparatus between a plurality of transfers to be routed over a corresponding plurality of paths provided by an interconnect circuit. The plurality of paths include a shared connection, the data processing apparatus having a plurality of initiator logic elements for initiating transfers and a plurality of recipient logic elements for receiving transfers, for each transfer the corresponding path coupling the initiator logic element responsible for initiating that transfer with the recipient logic element destined to receive that transfer. The apparatus provides arbitration logic with an indication as to whether the ready signal from a storage element has been asserted, and employs the arbitration logic to select, in dependence on predetermined criteria including at least that indication, one of the plurality of transfers for routing via the shared connection.

Abstract: A method, system and computer program product for creating and dynamically selecting an arbiter design within a data processing system on the basis of command history is disclosed. The method includes selecting a first arbiter for current use in arbitrating between requestors for a resource. During operation of said data processing system, an arbiter selection unit detects requests for the resource and selects a second arbiter in response to the detected requests for the resource.

Abstract: A storage device for a multibus architecture includes at least one memory to store data, information, and/or addresses, along with a memory connection having a port to connect the memory to one of the buses of the multibus architecture. The memory connection, the port, and the bus have data lines to transmit data along with address lines to transmit addresses, and/or control information to control the memory and other devices connected to each specific bus within the multibus architecture. A switching device selectively connects the memory connection to one of the buses to enable a memory access to transmit data, addresses, and/or control information to or from the selected one of these buses.

Abstract: A redundant external storage virtualization computer system. The redundant storage virtualization computer system includes a host entity for issuing an IO request, a redundant external storage virtualization controller pair coupled to the host entity for performing an IO operation in response to the IO request issued by the host entity, and a plurality of physical storage devices for providing storage to the computer system. Each of the physical storage devices is coupled to the redundant storage virtualization controller pair through a point-to-point serial signal interconnect. The redundant storage virtualization controller pair includes a first and a second storage virtualization controller both coupled to the host entity. In the redundant storage virtualization controller pair, when the second storage virtualization controller is not on line, the first storage virtualization controller will take over the functionality originally performed by the second storage virtualization controller.

Abstract: A system, method and computer program product are provided which are capable of intercepting a call. Once intercepted, it is determined whether the call is associated with a previous sequence of calls in order to identify a correct sequence of calls associated with the intercepted call. Next, the call is associated with the correct sequence of calls. State information that is associated with the call is then gathered. Further, sequence state information is updated, and it is determined whether a process is unwanted based, at least in part, on such sequence state information. If it is determined that the process is unwanted, a reaction may be made to the unwanted process. If it is not determined that the process is unwanted, a next call may be intercepted, and so on.

Abstract: In a distributed system, a resource such as a storage device is protected by an owner node's exclusive access to it, wherein exclusive access is established via a persistent reservation on the resource. A persistent reservation is never removed, however the owner node's persistent reservation may be challenged in an arbitration process, to take it away from a failed owner node. A challenger node challenges by changing an owner's access key (that establishes the persistent reservation) to a challenge key, delaying, and determining whether the owner restored the owner's access key during the delay, because a properly operating owner replaces a challenge key with its owner access key. If the owner fails to restore its owner access key, the challenger node becomes the new resource owner by replacing the challenge key with an owner access key of the challenger node. The key may include additional information to provide extensibility.

Abstract: A storage controller that provides controlled access to storage devices by host computers is disclosed. The storage controller includes a host interface adapter that interfaces the storage controller to the hosts, a device interface adapter that interfaces the storage controller to the storage devices, and a microprocessor that processes requests by the hosts to access the storage devices. An access control table is created in response to user input in a memory accessible by the host interface adapter. When the host interface adapter receives a request, it determines from the access control table whether the requesting host has permission to access the specified storage device. If so, the host interface adapter forwards the request to the microprocessor. Otherwise, the host interface adapter transmits a response to the host denying access in one embodiment, or in another embodiment, provides an indication to the microprocessor that access should be denied.

Abstract: A method and apparatus for providing peer-to-peer data transfer through an interconnecting fabric. The method and apparatus enable a first device to read and/or write data to/from a local memory of a second device by communicating read and write requests across the interconnectivity fabric. Such data transfer can be performed even when the communication protocol of the interconnectivity fabric does not permit such transfers.

Abstract: A system and method for managing access to a shared resource employs mutually exclusive flags. The flags enable arbitration between all applications requesting the use of the shared resource and ensure that each application has exclusive and continuous use of the shared resource. The preferred embodiment uses hardware to realize the flags and the flag arbitrating means. In one embodiment, the applications control and observe the flags through read/write registers. Alternative embodiments provide a unique read/write register for each application using the shared resource.

Abstract: An arbitration structure, a method, and a computer program are provided for an arbitration scheme that can handle a plurality of memory commands in an operating system. Typically, in a memory system there are three types of memory commands: periodic, read, and write. An arbitration scheme determines the order of priority in which these commands are executed. This arbitration scheme is flexible because it contains a read/write priority module, which can be programmed to execute any order of priority combination of read and write commands. This enables an arbitration scheme for any memory system to be easily programmed for maximum efficiency.

Abstract: In a system in which a CPU contained LSI and an external CPU share a bus, when the external CPU accesses a device to be controlled which is connected to a bus, the access to a device mounted on the common bus is not prevented in the CPU contained LSI. A CPU contained LSI includes a CPUa, common address/data buses 111 and 112 connected to the CPUa, CPUb address/data buses 211 and 212 connected to a CPUb, and a bus adjusting circuit 105 disposed between the common address/data buses and the CPUb address/data buses to exclusively control accesses from the CPUa and the CPUb to a device connected to the common address/data buses and connect the CPUb adress/data buses to the common address/data buses only when the CPUb is permitted to access the device connected to the common address/data buses.

Abstract: Multiple data processing circuits may share a semiconductor memory circuit, such as double-data-rate synchronous dynamic random access memory (DDR-SDRAM). A data processing circuit (202-1 or 202-2) ending control of a semiconductor memory circuit (201) supplies a clock enable signal and chip select signal at predetermined levels. A data processing circuit (202-2 or 202-1) starting control of a semiconductor memory circuit (201) supplies a clock enable signal and chip select signal at the same predetermined levels, before the data processing circuit (202-1 or 202-2) ending control stops supplying a clock enable signal and chip select signal. Therefore, a clock enable signal and chip select signal do not enter an undefined state, and malfunctions that could otherwise occur are prevented.

Abstract: In a method of controlling transmitting and receiving buffers of a network controller and a network controller operating under such a method, at least one request for access to a system bus from the transmitting buffer and the receiving buffer is received, and the occupancy level of data in the receiving buffer and the vacancy level of data in the transmitting buffer are determined. Access to the system bus is granted based on the determination result. Buffers in the transmitting and receiving paths are treated as a single virtual transmitting buffer and a single virtual receiving buffer, respectively. Bus priority is determined by the data occupancy level in each virtual buffer and any change in the occupancy level. Therefore, it is possible to prevent or reduce underflow of the transmitting buffer and overflow of the receiving buffer, thereby impartially arbitrating which of the buffers can access the memory.

Abstract: A method and an engineering system, which reduce the extent of configuration work with regard to a possible expansion of the automation device. A configured automation device can thus be expanded during the control of the automation device by means of slave modules. During a configuration phase, the number of the slave units (11, 12, 13, 16, 17, 18) and a user data area for each slave unit can be configured. For each slave module of a slave unit, a portion of the user data area can be assigned. The user data area is prepared for a possible expansion of the slave unit by at least one slave module in that, in addition to the configured user data area of a respective slave unit required for the current control, a reserve user data area (11c, 11d, 13b, 13c, 13d, 16d, 18d) is configured for the at least one slave module.

Abstract: Machine-readable media, methods, and apparatus are described for performing direct memory access (DMA) transfers. In some embodiments, a device may generate an interrupt to request a DMA transfer. A DMA controller may claim the interrupt and may prevent a processor from receiving and/or servicing the claimed interrupt. The DMA controller may further transfer a data block in response to the claimed interrupt.

Abstract: The bus circuit of a master electronics card in a backplane-based communications system adaptively grants the upstream bus to the slave electronics cards by the early termination of a scheduled number of grants to a slave electronics card when the bus circuit on the master electronics card detects idle cells.

Abstract: A disk drive control system comprising a micro-controller, a micro-controller cache system adapted to store micro-controller data for access by the micro-controller, a buffer manager adapted to provide the micro-controller cache system with micro-controller requested data stored in a remote memory, and a cache demand circuit adapted to: a) receive a memory address and a memory access signal, and b) cause the micro-controller cache system to fetch data from the remote memory via the buffer manager based on the received memory address and memory access signal prior to a micro-controller request.

Abstract: A multi-channel serial advanced technology attachment (SATA) control system and control card thereof includes a first SATA control module, a first access-grant arbitration unit, a second SATA control module, a second access-grant arbitration unit and a path selection module. Through an arbitration process performed in the first and second access-grant arbitration units, an access-grant is determined. And a selection signal is generated based on the process result that is sent to the path selection module, to switch a transmission path to the SATA control module which has acquired the access-grant. Therefore, multi-channel SATA data access function may be achieved.

Abstract: A method and apparatus are provided for efficiently operating a round robin arbitration system in a given computer system. The system utilizes a series of banks of requestors and pointer. The banks of requestors and pointers operate on sequential AND-OR-Inverter/OR-AND-Inverter (AOI/OAI) logic to advance the pointer and efficiently select those requestors with pending requests. The use of the AOI/OAI logic circuitry in the banks of requestors and pointers allows for efficient selection and minimization of complex circuitry reducing the overall circuit area.

Abstract: An arbitration process ensures changes made by more than one node to the same data are propagated to each node holding the shared entity and applied in the same order on each node. An arbitration cycle for a particular entity is begun on a node (“instigator”) when the node broadcasts a proposal message or when the node (“observer”) receives such a proposal message. Multiple nodes can be instigators during a single arbitration cycle. Each node that receives a proposal message sends a response message to the corresponding instigator. After each instigator node receives all the proposals in the arbitration cycle, it determines whether it is the winner of the arbitration cycle and broadcasts a closure message if it is. Each node determines an order in which to apply the changes when it has received all the proposals. Arbitration cycles associated with different items can be running concurrently.

Abstract: In a first aspect, a first method is provided for allocating memory bandwidth. The first method includes the steps of (1) assigning a fixed priority of access to the memory bandwidth to one or more direct memory access (DMA) machines; and (2) assigning a programmable priority of access to the memory bandwidth to a processing unit. The programmable priority of the processing unit allows priority allocation between the one or more DMA machines and the processing unit to be adjusted dynamically. Numerous other aspects are provided.

Abstract: Methods and apparatus, including computer program products, implementing techniques for receiving a request for access to a memory space of an Advanced Switching device, the memory space including a first memory segment and a second memory segment, determining access permissions for the requested memory space, and processing the access request when an access is determined to be permitted. The techniques include identifying a source of the request as a node configuration packet processor, and denying the access if the node configuration packet processor is requesting access to the second memory segment which is assigned to a hidden storage device.

Abstract: A data processor has a first bus master module, first bus slave module and first bus right arbitrating circuit connected to a first bus, a second bus master module, second bus slave module and second bus right arbitrating circuit connected to a second bus, and a bus bridge circuit connecting the first and second buses. The bus bridge circuit has a first transfer controller, responsive to an access request from the first bus to the second bus, for obtaining a bus right of the second bus, and a second transfer controller, responsive to an access request from the second bus to the first bus, for obtaining a bus right of the first bus. The second bus has a first path connecting the second bus slave module and the first transfer controller and a second path connecting the second bus master module and the second transfer controller.

Abstract: An edge detecting circuit detects an input level change (edge) of a synchronous signal provided from a synchronous signal input terminal. A data latch unit latches digital data provided from an external data input terminal. An address generating circuit provides an address signal. A write control unit activates/deactivates a write enable signal for writing to a RAM. An arbitration circuit monitors a write control enable signal, a read enable signal and a write enable signal, and detects a cycle, in which a CPU does not access the RAM.

Abstract: A system for arbitrating access to a shared resource includes a plurality of microprocessors, a shared resource; and a controller coupled to the plurality of microprocessors and the shared resource by a first bus and a second bus, respectively, the controller including a register having a lock portion associated with each of the plurality of processors and at least one status portion, each of the lock portions indicating whether the associated one of the plurality of microprocessors has obtained access to communicate with the shared resource and each of the at least one status portion includes a bit indicating whether any of the plurality of microprocessors has obtained access to communicate with the shared resource.

Abstract: A data bus transfers data between at least one slave device and a plurality of master devices, and an arbiter grants access to each of the master devices. The slave device includes look-ahead apparatus that includes staging register for staging an identification of a master device and a decoder for comparing a staged identification to an identification of a command from the bus. The look-ahead apparatus issues split releases of a next master device while the slave device returns data associated with a prior command.

Abstract: An invention is provided for a synchronous transfer of control. An asynchronous interrupt exception is received, and in response, the value of a reference counter is determined. The value of the reference counter is based on the execution of synchronized code. Generally, the reference counter is initialized to a predetermined number, and altered based on the execution of synchronized code. When the asynchronous interrupt exception is received, the method is asynchronously interrupted when the value of the reference counter is equal to the predetermined number.

Abstract: A multiprocessor system having a plurality of processor elements each of which obtains right to use bus of a first or second shared bus in response to a transfer request for control system data or input/output data and as a master, conducts multiplex-transfer or burst-transfer, in which the processor element outputs a bus request signal for the first shared bus in response to a transfer request for the control system data and as a master, transfers and outputs a selection signal, a control signal and an address signal of a transfer destination and the control system data in one cycle in response to application of a bus grant signal, and is selected as a slave based on the selection signal through the first shared bus to receive input of the control system data and process the data based on the control signal and the address signal.

Abstract: A competition arbitration system in which chances for using a resource of a computer such as a bus or the like among devices are fair is provided. Pulses are sequentially generated periodically from a pulse generating circuit. It is assumed that first device outputted first bus request signal and second device continuously outputted second bus request signal before rising timing of the first pulse. When a bus arbiter outputs a bus grant signal to the first device at the rising timing of the first pulse, the bus master of the first device outputs a bus use acknowledgment signal. Then a use grant inhibiting circuit receives the acknowledgment signal and outputs an inhibition signal for inhibiting use of other devices. Thus, the first device holds the use right of a bus and bus use requests of other devices are reserved.

Abstract: A method and system that creates and maintains lock properties for a resource or object in a distributed environment. The method and system creates and/or updates lock objects to relate to multiple locks, i.e., multiple resources. The method and system creates and maintains lock properties for a resource or object in a distributed environment.

Abstract: The invention provides an interconnection architecture for semiconductor devices. Cross bar switches are traditionally placed in the center of the IC. However, this location may also be the preferred location for the centralized logic in the IC. This invention, known as a cross bar ring or CBR, provides cross bar switch functionality in a manner that can be easily distributed around the chip. Typically, it can fit in the routing channels between other functional blocks, thereby allowing other centralized functions to be placed in the center of the IC. The CBR is defined so that it can be partitioned into separate modules, which greatly aids in the placement and routing of wires. Furthermore, the architecture is defined such that the CBR can use storage elements, allowing it to be pipelined so that the wire distances can be increased while still maintaining a high internal clock speed.

Abstract: A PCI Express to PCI bridge enables upstream and downstream isochronous data transfer by modifying the PCI bus arbiter so that the PCI device on the PCI bus is treated as a virtual port for the bridge. Data from the PCI device is assigned via a port arbitration table to sufficient bandwidth so that the data from the PCI device can be transferred upstream isochronously. The bridge also handles downstream isochronous data transfer.

Abstract: Control of a loop of a fiber-channel arbitrated-loop serial communications channel is maintained (i.e., the loop connection is held open) as long as a minimum amount of data, which optionally is determined by programming (called a “programmable amount of data”), is available for transmission, in order to reduce the overall amount of time spent arbitrating for control of the loop. The improved communications channel system includes a channel node having one or more ports, each port supporting a fiber-channel arbitrated-loop serial communications channel loop, wherein each port arbitrates for control of that port's attached channel loop. The system also includes an arbitration-and-control apparatus to reduce arbitrated-loop overhead, wherein control of the channel loop, once control is achieved by arbitration, is maintained by the arbitration-and-control apparatus as long as a predetermined amount of data is available within control of the node.