Abstract: System and methods are provided for dynamically managing a first-in/first-out (FIFO) command queue of a system controller. One or more commands are received into the command queue, a command being associated with a priority parameter. A current command first in line to be executed in the command queue is determined, the current command being associated with a first priority parameter. A second command associated with a second priority parameter is determined, the second priority parameter being largest among priority parameters associated with the one or more commands. A final priority parameter for the current command is computed based at least in part on the second priority parameter.

Abstract: Methods, systems and data structures for determining a token master on a ring network are provided. According to one embodiment, determining a token master on a ring network includes receiving a packet containing a network token at a first node on the network. If the network token does not arrive within a preselected timeout period, generating an arbitration token. If the packet contains an arbitration token, determining if the arbitration token was modified by a higher priority node of the network and if not, setting the first node as a token master and converting the arbitration token to a packet transmission token. Arbitration tokens are used to identify a token master that is responsible for generating a packet transmission token onto the network, whereas the packet transmission token authorizes a transmitting node that has most recently received the packet transmission token to transmit locally generated packets onto the network.

Abstract: An aspect of this invention is a computer system, including: a storage apparatus for allocating real storage areas of a plurality of tiers of a tiered real storage area pool to a volume, and migrating and relocating data within the volume between the plurality of tiers; and a host apparatus that accesses the volume provided by the storage apparatus. The host apparatus is configured to refer to tier information including information on a corresponding one of the plurality of tiers to which an access destination address within the volume belongs to identify the corresponding one of the plurality of tiers to which the access destination address belongs and refer to settings predetermined for the plurality of tiers to perform I/O control for the access destination address based on settings of the identified corresponding one of the plurality of tiers.

Abstract: Some of the embodiments of the present disclosure provide a method comprising receiving a first set of memory access commands; modifying the first set of memory access commands to generate a second set of memory access commands; and in response to said generation of the second set of memory access commands, issuing the second set of memory access commands to a memory. Other embodiments are also described and claimed.

Abstract: Systems, mediums, and methods are provided for scheduling input/output requests to a storage system. The input output requests may be received, categorized based on their priority, and scheduled for retrieval from the storage system. Lower priority requests may be divided into smaller sub-requests, and the sub-requests may be scheduled for retrieval only when there are no pending higher priority requests, and/or when higher priority requests are not predicted to arrive for a certain period of time. By servicing the small sub-requests rather than the entire lower priority request, the retrieval of the lower priority request may be paused in the event that a high priority request arrives while the lower priority request is being serviced.

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract: A capability is provided for adaptive polling of a device based on a set of polling control regions configured to control polling of the device. The set of polling control regions is defined based on at least one of a set of control parameters and non-parametric control information. A transition within the set of polling control regions is determined based on a current polling control region and a target polling control region that is determined based on input information received while in the current polling control region. The input information may include at least one of values of one or more parameters in the set of parameters and non-parametric input information. The transition may include remaining in the current polling control region or transitioning to a new polling control region. The transition may be performed based on a rapid up controlled down (RUCD) transition scheme.

Abstract: A direct memory access (DMA) engine schedules data transfer requests of a data processing system according to both an assigned transfer priority and the deadline for completing a transfer.

Abstract: A memory device includes a memory array with a plurality of memory elements. Each memory element is configured to store data. The device includes an input/output (I/O) buffer coupled to the memory array. The I/O buffer is configured to receive data from an I/O interface of a memory device controller and write the data to the memory array. The device includes a memory control manager coupled to the memory array. The memory control manager is configured to pause a program operation to the memory array in response to receiving a pause command. The memory control manager is also configured to resume the program operation in response to receiving a resume command.

Abstract: The present invention is a clustered storage system with which, even when access to the processor of another controller is sent from the processor of one controller, the processor of the second controller is able to prioritize processing of this access so that I/O processing is also prevented from being delayed. With the storage system of the present invention, the first processor of the first controller transmits request information which is to be processed by the second processor of the second controller to the second processor by differentiating between request information for which processing is to be prioritized by the second processor and request information for which processing is not to be prioritized, and the second processor acquires the request information by differentiating between request information for which processing is to be prioritized and request information for which processing is not to be prioritized.

Abstract: A multi-chip memory device and a method of controlling the same are provided. The multi-chip memory device includes a first memory chip; and a second memory chip sharing an input/output signal line with the first memory chip, wherein each of the first memory chip and the second memory chip determines whether to execute a command unaccompanied by an address, by referring to a history of commands.

Abstract: An apparatus, system, and method are disclosed for managing operations for data storage media. An adjustment module interrupts or otherwise adjusts execution of an executing operation on the data storage media. A schedule module executes a pending operation on the data storage media in response to adjusting execution of the executing operation. The pending operation comprises a higher execution priority than the executing operation. The schedule module finishes execution of the executing operation in response to completing execution of the pending operation.

Abstract: Multiple variants of a data processing system, which maintains I/O priority from the time a process makes an I/O request until the hardware services that request, will be described. In one embodiment, a data processing system has one or more processors having one or more processor cores, which execute an operating system and one or more applications of the data processing system. The data processing system also can have one or more non-volatile memory device coupled to the one or more processors to store data of the data processing system, and one or more non-volatile memory controller coupled to the one or more processors. The one or more non-volatile memory controller enables a transfer of data to at least one non-volatile memory device, and the priority level assigned by the operating system is maintained throughout the logical data path of the data processing system.

Abstract: A file protecting method and system and a memory controller and a memory storage apparatus using the same are provided. The file protecting method includes performing a file protection enabling procedure for a file to generate an entry value backup according to at least one entry value corresponding to at least one cluster storing the file, which is recorded in a file allocation document, store the entry value backup in a secure storage area and change the entry value corresponding to the cluster storing the file in the file allocation document, wherein the file cannot be read according to the changed entry value. Accordingly, the file stored in the memory storage apparatus the can be effectively protected from being accessed by an un-authorized person.

Abstract: Systems, mediums, and methods are provided for scheduling input/output requests to a storage system. The input output requests may be received, categorized based on their priority, and scheduled for retrieval from the storage system. Lower priority requests may be divided into smaller sub-requests, and the sub-requests may be scheduled for retrieval only when there are no pending higher priority requests, and/or when higher priority requests are not predicted to arrive for a certain period of time. By servicing the small sub-requests rather than the entire lower priority request, the retrieval of the lower priority request may be paused in the event that a high priority request arrives while the lower priority request is being serviced.

Abstract: A storage system and method for setting parameters and determining latency in a chained device system. Storage nodes store information and the storage nodes are organized in a daisy chained network. At least one of one of the storage nodes includes an upstream communication buffer. Flow of information to the storage nodes is based upon constraints of the communication buffer within the storage nodes. In one embodiment, communication between the master controller and the plurality storage nodes has a determined maximum latency.

Abstract: A data storage system includes a plurality of non-volatile memory devices arranged in one or more sets, a main controller and one or more processors. The main controller is configured to accept commands from a host and to convert the commands into recipes. Each recipe includes a list of multiple memory operations to be performed sequentially in the non-volatile memory devices belonging to one of the sets. Each of the processors is associated with a respective set of the non-volatile memory devices, and is configured to receive one or more of the recipes from the main controller and to execute the memory operations specified in the received recipes in the non-volatile memory devices belonging to the respective set.

Abstract: A system and method for allocating resources on a shared storage system are disclosed. The system 10 can include a shared storage device 12 and a plurality of port schedulers 14 associated with a plurality of I/O ports 16 that are in communication with the shared storage device 12. Each port scheduler 14 is configured to enforce a concurrency level and a proportional share of storage resources of the shared storage device 12 for each application 18 utilizing the associated port. The system 10 can also include a resource controller 17 that is configured to both monitor performance characteristics of the applications 18 utilizing at least one of the I/O ports 16, and to adjust the concurrency level and the proportional share of storage resources parameters of the port schedulers 14 for at least a portion of the applications 18 in order to vary allocation of the resources of the shared storage device 12.

Abstract: A SAS expander configured to operate as a SAS expander hub receives IO requests from a plurality of connected SAS expanders. Each SAS expander determines if it is capable of servicing a received IO request and sending such IO requests to the SAS expander hub if necessary. The SAS expander hub relays the IO requests to SAS expanders connected to data storage devices capable of servicing such IO requests.

Abstract: A host I/F unit has a management table for managing an MPPK which is in-charge of the control of input/output processing for a storage area of an LDEV, and if a host computer transmits an input/output request for the LDEV, the host I/F unit transfers the input/output request to the MPPK which is in-charge of the input/output processing for the LDEV based on the management table, an MP of the MPPK performs the input/output processing based on the input/output request, and the MP of the MPPK also judges whether the MPPK that is in-charge of the input/output processing for the LDEV is to be changed, and sets the management table so that an MPPK which is different from the MPPK that is in-charge is to be in-charge of the input/output processing for the LDEV.

Abstract: An arrangement for facilitating remote booting in diskless client systems as just described. To this end, there is broadly contemplated herein the employment of a hypervisor that can freely accommodate a variety of booting arrangements for a given OS. This then ensures that few if any modifications, especially costly ones, would need to be made to the OS to ensure greater versatility.

Abstract: An approach is provided for distributed policy management and enforcement. A policy manager determines one or more domains of an information system. The one or more domains are associated at least in part with respective subsets of one or more resources of the information system. The policy manager also determines one or more respective access policies local to the one or more domains. The one or more respective access policies configured to enable a determination at least in part of access to the respective subsets, the one or more resources, or a combination thereof. At least one of the one or more respective access policies is configured to operate independently of other ones of the one or more respective schemas.

Abstract: Data-transfer transactions in the read and write directions may be balanced by taking snapshots of the transactions stored in a buffer, and executing transactions in the same direction back-to-back for each snapshot.

Abstract: Data-transfer transactions from multiple masters may be balanced by taking snapshots of the transactions stored in a buffer, and executing transactions from each master back-to-back.

Abstract: Embodiments of the invention include electronic communications devices having a memory in near field communication device, a memory arbitrator and a host processor. The near field communication (NFC) devices are configured to receive data and drive power from the communication signal. The memory arbitrator is connected to the NFC device and the memory. The memory arbitrator is also configured to access the memory in response to an access request from the NFC device. Additionally, the memory is configurable to be accessed by both the host processor and the NFC device according to embodiments of the present invention.

Abstract: Mechanisms are provided for remote direct memory access (RDMA) resource leak detection. A user space context is generated comprising a user space RDMA resource hierarchical data structure. A kernel context is generated comprising a kernel RDMA resource hierarchical data structure. The kernel RDMA resource hierarchical data structure comprises nodes of the users space RDMA resource hierarchical data structure. A request to close a RDMA resource is received and the user space RDMA resource hierarchical data structure is traversed to determine whether the RDMA resource has child RDMA resources allocated in the user space RDMA resource hierarchical data structure. A resource leak is detected in response to determining, based on at least one of the user space RDMA resource hierarchical data structure or the kernel RDMA resource hierarchical data structure, that the RDMA resource has a child RDMA resource allocated in the user space RDMA resource hierarchical data structure.

Abstract: Techniques are provided for managing, within a storage system, the sequence in which I/O requests are processed by the storage system based, at least in part, on one or more logical characteristics of the I/O requests. The logical characteristics may include, for example, the identity of the user for whom the I/O request was submitted, the service that submitted the I/O request, the database targeted by the I/O request, an indication of a consumer group to which the I/O request maps, the reason why the I/O request was issued, a priority category of the I/O request, etc. Techniques are also provided for automatically establishing a scheduling policy within a storage system, and for dynamically changing the scheduling policy in response to changes in workload.

Abstract: Disclosed herein is a nonvolatile memory including: a nonvolatile memory cell device including at least a nonvolatile memory cell array accessible in units of a word and further accessible at least with a fixed latency in a first access mode and with a variable latency in a second access mode; a first access path used in the first access mode; a second access path used in the second access mode; a first ECC processing part configured to be connected to the first access path and to perform error detection and correction using an ECC on the data output from the nonvolatile memory cell array in the first access mode; and a second ECC processing part configured to be connected to the second access path and to perform error detection and correction using the ECC on the data output from the nonvolatile memory cell array in the second access mode.

Abstract: A connection apparatus that connects a plurality of storage units and a controller that establishes connection with the respective storage units in response to a connection request issued from each of the plurality of storage units and accesses the storage units includes a processor; and a memory, wherein the processor transmits a connection request selected based on priority information that represents priority associated with the connection among a plurality of received connection requests to the controller, the priority information being stored in the memory, and changes priority information included in a connection request received from a certain storage unit among the plurality of storage units so that the priority information has higher priority than the priority information included in connection requests received from the other storage units for a period where a connection request is successively received from the certain storage unit and a predetermined condition is satisfied.

Abstract: Various embodiments of the invention provide resource management of available data bandwidth of a SAS system in a non-uniform way. In certain embodiments, arbitration wait time values are adaptively modified to achieve a specified performance quota for a link.

Abstract: An access method includes: obtaining, by a computer, a result of monitoring a busy rate and a number of access operations per unit time of a storage device, the storage device having a first storage area and a second storage area; calculating a characteristic of correlation between the busy rate and the number of access operations per unit time based on the result; calculating a second number of access operations per unit time based on the characteristic of the correlation such that a sum of a first busy rate corresponding to a first number of access operations per unit time and a second busy rate corresponding to a second number of access operations per unit time becomes equal to or lower than a given busy rate; and controlling a number of operations to access the second storage area per unit time based on the second number of access operations.

Abstract: Embodiments of the invention include electronic communications devices having a memory in near field communication device, a memory arbitrator and a host processor. The near field communication (NFC) devices are configured to receive data and drive power from the communication signal. The memory arbitrator is connected to the NFC device and the memory. The memory arbitrator is also configured to access the memory in response to an access request from the NFC device. Additionally, the memory is configurable to be accessed by both the host processor and the NFC device according to embodiments of the present invention.

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract: The present disclosure relates to a method for enabling a virtual processing unit to access a peripheral unit, the virtual processing unit being implemented by a physical processing unit connected to the peripheral unit, the method comprising a step of transmitting to the peripheral unit a request sent by the virtual processing unit to access a service provided by the peripheral unit, the access request comprising at least one parameter and an identifier of the virtual unit, the method comprising steps, executed by the peripheral unit after receiving an access request, of allocating a set of registers to the virtual unit identifier received, storing the parameter received in the register set allocated, and when the peripheral unit is available for processing a request, selecting one of the register sets, and triggering a process in the peripheral unit from the parameters stored in the selected register set.

Abstract: Multiple variants of a data processing system, which maintains I/O priority from the time a process makes an I/O request until the hardware services that request, will be described. In one embodiment, a data processing system has one or more processors having one or more processor cores, which execute an operating system and one or more applications of the data processing system. The data processing system also can have one or more non-volatile memory device coupled to the one or more processors to store data of the data processing system, and one or more non-volatile memory controller coupled to the one or more processors. The one or more non-volatile memory controller enables a transfer of data to at least one non-volatile memory device, and the priority level assigned by the operating system is maintained throughout the logical data path of the data processing system.

Abstract: An disclosed information processing apparatus includes a memory unit for storing first setting-values for setting-items for a program in accordance with multiple priority levels, a given one of the setting-items being for one or more of the first setting-values, and each of the first setting-values having one of the priority levels assigned thereto; a setting information management unit for obtaining the first setting-values from the memory unit, and creating second setting-values by selecting, as one of the second setting-values, one of the first setting-values for any given setting-item from the first setting-values for the given setting-item such that the one of the first setting-values selected for the given setting-item has a highest priority level among the first setting-values for the given setting-item; and a program management unit for starting the program that operates based on the created second setting values.

Abstract: Methods and apparatus relating to an inter-queue anti-starvation mechanism with dynamic deadlock avoidance in a retry based pipeline are described. In one embodiment, logic may arbitrate between two queues based on various rules. The queues may store data including local or remote requests, data responses, non-data responses, external interrupts, etc. Other embodiments are also disclosed.

Abstract: A disclosed data transfer device includes one or more data transfer control unit configured to control a command issuance and a data transfer separately, a command issuing unit configured to determine priorities of commands and issue the commands in an order from a higher priority, a memory communication control unit configured to perform the data transfer corresponding to the command from and to a memory, and a signal output unit configured to output a completion signal of the data transfer in a case where the data transfer is normally completed. The command issuing unit sets a priority of a command corresponding to a request for resetting the data transfer control unit lower than the priority of the command issued by the data transfer control unit when the request for resetting is received, and the signal output unit outputs a dummy completion signal to the memory communication control unit.

Abstract: A memory controller, system, and method for accelerating blocking memory operations. A memory controller reorders memory operations so as to maximize efficient use of the memory device bus. When data for a newer memory operation is retrieved from memory and ready to be returned to a source device, the newer memory operation can be held up waiting for an older memory operation to be completed. In response, the memory controller forwards a push request for the older memory operation to a memory channel unit. The memory channel unit then sets a push bit of the older memory operation, which expedites the scheduling of the older memory operation.

Abstract: According to a prior art data transfer method of a storage subsystem, when competition of data transfer accesses occurs, a free access destination port is allocated uniformly without determining the access type or the access state of the access destination, so that the performance of the device is not enhanced. The present invention solves the problem by selecting a data transfer access for completing data transfer with priority based on the access type or the remaining transfer data quantity of competing data transfer accesses, or by changing the access destination of an access standby data transfer access, thereby performing data transfer efficiently.

Abstract: According to one embodiment, an electronic device receives inputs of video signals from a plurality of input systems. The electronic device includes a priority determination table, a video switching instruction module, a video switching module. In the priority determination table, video display priorities of the video signals from the input systems are determined in advance. The video switching instruction module instructs to switch among the video signals from the input systems on the basis of the priorities determined in the priority determination table. The video switching module switches among the video signals from the input systems according to a switching instruction from the video switching instruction module.

Abstract: A prefetch controller implements an upgrade when a real read access request hits the same memory bank and memory address as a previous prefetch request. In response per-memory bank logic promotes the priority of the prefetch request to that of a read request. If the prefetch request is still waiting to win arbitration, this upgrade in priority increases the likelihood of gaining access generally reducing the latency. If the prefetch request had already gained access through arbitration, the upgrade has no effect. This thus generally reduces the latency in completion of a high priority real request when a low priority speculative prefetch was made to the same address.

Abstract: A method of communicating over a bus is disclosed. The bus includes a write address channel, a write channel, and a read address channel. The method includes sending an address from a sending device to a receiving device via the write address channel. The method further includes concurrently sending a portion of a payload to the receiving device via the write channel and another portion of the payload to the receiving device via the read address channel. When sending multiple sequential portions of the payload via the bus concurrently, the sending device is configured to give data ordering preference to the write channel over the read address channel by sending a first sequential portion of the multiple sequential portions via the write channel and sending a subsequent sequential portion of the multiple sequential portions via the read address channel.

Abstract: A host I/F unit has a management table for managing an MPPK which is in-charge of the control of input/output processing for a storage area of an LDEV, and if a host computer transmits an input/output request for the LDEV, the host I/F unit transfers the input/output request to the MPPK which is in-charge of the input/output processing for the LDEV based on the management table, an MP of the MPPK performs the input/output processing based on the input/output request, and the MP of the MPPK also judges whether the MPPK that is in-charge of the input/output processing for the LDEV is to be changed, and sets the management table so that an MPPK which is different from the MPPK that is in-charge is to be in-charge of the input/output processing for the LDEV.

Abstract: The present invention is a clustered storage system with which, even when access to the processor of another controller is sent from the processor of one controller, the processor of the second controller is able to prioritize processing of this access so that I/O processing is also prevented from being delayed. With the storage system of the present invention, the first processor of the first controller transmits request information which is to be processed by the second processor of the second controller to the second processor by differentiating between request information for which processing is to be prioritized by the second processor and request information for which processing is not to be prioritized, and the second processor acquires the request information by differentiating between request information for which processing is to be prioritized and request information for which processing is not to be prioritized.

Abstract: An image processing apparatus that has an interface section for connecting a measuring instrument and is capable of changing an operating mode to an adjustment mode in which an adjustment is carried out by using the results of measurements by the measuring instrument, the image processing apparatus comprising a control section detecting whether the measuring instrument is connected to the interface section, and when the measuring instrument is detected, changing the operating mode to the adjustment mode.

Abstract: A stream data control server includes: a processable flow rate managing unit which manages a processable flow rate corresponding to an amount of data per unit time, which can be processed in each of storage units serving as storing destinations; a classified data flow rate managing unit which manages a data flow rate corresponding to an amount of data processed per unit time for each class of data to which a data priority is attached; and a storing destination control unit which controls the storing destinations of respective data based upon the processable flow rate of each of the storage units and the data flow rate for each class in such a manner that the data having higher data priorities are stored in the storage units having higher priorities within a range of the processable flow rate of each of the storage units.

Abstract: A data processing apparatus and method for setting priority levels for transactions is provided. The data processing apparatus has a shared resource for processing transactions, and at least one master device for issuing the transactions to the shared resource. The at least one master device provides a plurality of sources of the transactions, and each of the transactions has a priority level associated therewith. Arbitration circuitry is used to apply an arbitration policy to select a transaction from amongst multiple transactions issued to the shared resource, the arbitration policy using the priority level associated with each of the multiple transactions when performing the selection.

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract: A data storage device accepts queued read and write commands that have deadlines. The queued read and write commands are requests to access the data storage device. The deadlines of the queued read and write commands can be advisory deadlines or mandatory deadlines.